DE2724165A1 - Junction FET with semiconductor substrate of first conduction type - has source and drain zones which reach no deeper in substrate than gate zone - Google Patents

Abstract

Source and drain zones of opposite conduction type are produced in the substrate surface. A gate zone with an insulation layer is between source and drain zones. A field insulation layer is around the source, drain and gate zones. Main boundary surfaces between substrate (20) and the source (22) and drain (24) zones lie in the substrate not deeper than the main boundary surface between gate insulating layer (26) and substrate, and between the field insulating layer (30) and the substrate. The insulating layer is typically of silicon dioxide and contains the gate electrode (28), which is typically of aluminium.

Description

Surface field effect transistor device

The invention relates to a surface field effect transistor device.

An integrated MOS circuit is known in which surface field effect transistors (hereinafter referred to as MOSFETs) integrated on a single semiconductor substrate are. Attempts have been made repeatedly to improve the integration density in such integrated MOS circuits increase. One of the cheapest ways to do this is in making the individual MOSFETs small.

However, simply shortening the channel length of the MOSFET leads to an unfavorable effect, known as the so-called "short channel effect" is known. When the channel length is shortened, the threshold voltage largely depends on the length of the canal. Recommends to avoid the problem in question it is preferable to design the source and drain regions flat or thin, which however the electric field near the major surfaces of the substrate the Junctions or barriers between the source region and the substrate as well is intensified between the drain region and the substrate. This results a reduction in the breakdown voltage at the pn junctions near the main surface of the substrate.

The details of these conditions are given below with reference to Figs. 1 and 2 explained in more detail. Fig. 1 is a schematic representation of part of a previous MOSFETs, whose source and drain areas are deep or deep in the substrate.

are made thick. In contrast, Fig. 2 shows schematically a part of a previous MOSFET in which the source and drain areas are flat or thin are designed. These figures also illustrate the distributions of the electrical Field in the vicinity of the source regions 1o and 11 in the respective cases when a Counter bias at the junctions or barrier layers between the source area and Substrate 12 is applied. The dashed lines in Figs. 1 and 2 indicate the Equipotential lines in the insulating layer 14 and the depletion layers 18, that between the source regions 10 and 11 on the one hand and the substrate 12 on the other hand are formed.

As can be seen from a comparison of these figures, the depletion layer becomes in the case of the thin source and drain regions when approaching the main surface of the substrate is narrower. The electric field prevailing in this area is therefore strong compared to the other areas, resulting in a reduction in the breakdown voltage at the pn junctions in this area.

The thin source and drain areas are used for source and drain areas provided metal electrodes made of e.g.

Aluminum melted together with these areas, whereby possibly an alloy is formed, which in turn reaches the substrate. this causes a reduction in the output of field effect transistors.

Of course, it is possible to reduce the foreign atom concentration To reduce the substrate to thereby reduce the breakdown voltage of the pn junctions of the Increase MOSFETs. However, this increases the width of the pn junction, which in turn runs counter to the tendency to make the MOSFETs small in size.

The object of the invention is thus to create a surface field effect transistor device, in which the effect of a short canal does not exist, but it does has a small size.

This task is accomplished in a surface field effect transistor device with a semiconductor substrate of one conductivity type, in the surface area This substrate formed source and drain regions of the semiconductor substrate of opposite conductivity type, a gate region with a gate insulating layer between source and drain area as well as one in the semiconductor substrate around source, Drain and gate areas formed around field insulating layer, according to the invention solved in that the main interfaces between the substrate and the source region and between the substrate and the drain region, in the direction of the depth of the semiconductor substrate seen, are practically no deeper than the major interfaces between the gate insulating layer and the substrate and between the field insulating layer and the substrate.

The following is a preferred embodiment of the invention in Compared to the prior art explained in more detail with reference to the accompanying drawing. 1 and 2 show partial schematic representations of previously common MOSFETs for Illustration of the distributions of the electric field in the vicinity of the source areas, FIG. 1 showing thick and FIG. 2 showing thin source and drain regions, FIG. 3 showing one Top view of a MOSFET device with features according to the invention, FIG. 4 a Section along the line IV-IV in FIG. 3, FIG. 5 a section along the line V-V in Fig. 3 and Fig. 6 to 11 are schematic sectional views for illustration of the manufacturing method for the MOSFET according to FIGS. 3 to 5.

3 through 5 is a preferred embodiment of a MOSFET shown according to the invention, in which in a surface area of a substrate 20 made of silicon of the p-conductivity type drain and source regions 22 or 24 are formed. The substrate 20 has between the source and drain regions 22 or 24 a recess. A gate insulating layer 26, such as silicon dioxide, covers the recess and parts of the source and drain regions 22 and

24. Furthermore, the gate insulating layer 26 has a gate electrode 28 made of aluminum, for example. In the field region there is a field oxide layer 3o trained, which source and drain area, the gate insulating layer 26 and surrounding the Gabs electrode 28.

At this point it should be noted that those formed in the substrate Source and drain regions 22 and 24 extend less far into substrate 20 as the gate insulating layer 26 and the field oxide layer 30.

With this construction, this takes place in substrate 20 under the gate insulating layer 26 generated electric field practically parallel to the underside of the gate insulating layer 26 running x equipotential lines. Even if the canal is shortened, it is thus possible, the disadvantageous effect that the shortened channel area is uneven Causes potential distribution and therefore the threshold voltage largely of the change in the channel length depends to avoid. In other words: with the MOSFET according to FIGS. 3 to 5, in the previous field effect transistors with thin Source and drain areas appearing short channel effect switched off will. It should also be pointed out that the source and drain regions 22 and 24 are formed on the plateau or mesa regions of the substrate 20 and therefore can be made with any desired thickness. This will thus prevents the contact electrodes from passing through the source and drain regions 22 and 24 penetrate into the substrate 20. In addition, the heat treatment necessary in the production of the thin source and drain regions 22 and 24, respectively can be performed while also reducing the key resistance of each of these areas can be.

As can be seen from FIGS. 4 and 5, the interfaces run between the substrate 20 and the source region 22 and between the substrate 20 and the Drain area 24, namely the interfaces of the pn junctions or Barrier layers, perpendicular to the sidewalls of the gate insulating layer 26 and the Field oxide layer 30, i.e. to the boundary layers between the source region, field oxide layer and gate insulating layer and between the drain region, field oxide layer and gate insulating layer. This consequently increases the concentration of the electric field in the vicinity of the Major surface of the substrate 20 according to FIG. 2 eliminated. As a result, there will be an improvement the breakdown voltage between the substrate on the one hand and the source and drain regions on the other hand achieved.

Figures 6-11 illustrate the method of making the MOSFET device according to FIGS. 3 to 5.

According to FIG. 6, a first layer 100 made of silicon oxide is first made (silo2) on the surface of a p-type silicon substrate 20 having an impurity concentration of about 1015 atoms cm3, whereupon a second layer is formed on this layer 1o2 is formed from silicon nitride (Si3N4). Then, as shown in FIG. 7, the two Layers 100 and 102 on substrate 20 except for the source and drain regions corresponding sections etched away. A p + region with an impurity concentration of about lo18 atoms cm3 is produced by diffusion or the use of ions in the field areas formed in the substrate to prevent the formation of an inversion layer. Thereafter For example, oxide layers 30 and 104 each have a thickness of about 2 µm in the field areas and formed in the gate area. The use of ions, for example, makes phosphorus injected into the areas of the substrate 20 on which the first and second Layer are applied, whereby source and drain regions 22 and 24 of the n + type are formed whose foreign atom concentration is about 1 o19 atoms; cm3 and the depth of which is about 0.8 tm.

In the next process step, the oxide layer 104 is placed on the gate area removed by etching, while the oxide layers 30 remain in the field areas, whereby in the gate region, i.e. between the source and drain regions 22 and 24, a Groove with a width of about 2 / um and a depth of about 1.2 .mu.m is formed. During this process, the two layers 100 and 1o2 are also stranded through worn away. The corresponding state is shown in FIG. According to FIG. 10, a gate oxide layer 26 with a thickness of about 0.1 / µm on the surface of the formed according to the method step according to FIG. 9 obtained semiconductor structure, for which the manufacturing techniques for common polycrystalline silicon gate MOSFETs are used will. In the last method step according to FIG. 11, a pQlycrystalline silicon electrode 28 on the gate insulating layer 26 and a polycrystalline silicon gate electrode 28 is made on the gate oxide layer 26. Then, for example, by chemical Vapor deposition also forms an oxide layer 34 which is used to produce contact holes is provided with bores through which source and drain electrodes be formed on the areas concerned. The gate electrode 28 is with a Contact electrode not shown connected in the field area.

Like the usual MOSFET devices, the Way manufactured MOSFET as a component of a so-called.

Bucket brigade device and as a switching and amplifier element Find use.

Of course, the invention is not limited to that described above Embodiment limited. For example, in the embodiment described the source and drain Areas with their bases on one Height above the undersides of the gate insulating layer 26 and the field oxide layer 30 arranged. However, the undersides of these source and drain regions can also slightly below both the insulating layer 26 and the field oxide layer 30 lying. As a result, the properties of the field effect transistor are only slightly changes.

Furthermore, the source and drain regions in the method step according to FIG. 9 also by diffusion instead of ion use or ion implantation getting produced.

L e r s e i t e

Claims (2)

PATENT CLAIMS 1. Surface field effect transistor device with a semiconductor substrate of one conductivity type, in the surface area this Substrate formed source and drain regions of the semiconductor substrate opposite Conductivity type, a gate region with a gate insulating layer between Source and drain area as well as one in the semiconductor substrate around source, drain and Field insulating layer formed around gate regions, thereby g e k e n n -z e i c h n e t that the main interfaces between the substrate (20) and the source region (22) and between the substrate and the drain area (24), in the direction of the animals of the semiconductor substrate, practically no deeper than the main interfaces between the gate insulating layer (26) and the substrate and between the field insulating layer (3o) and the substrate. 2. Apparatus according to claim 1, characterized in that g e k e n n -z e i c h n e t that the main interface between the substrate and the source region is perpendicular to the Interfaces or barriers between the source region on the one hand and the gate insulating layer and the field insulating layer on the other hand and that the main interface between the substrate and the drain region is perpendicular to the interfaces of the barrier layers between the drain region on the one hand and the gate insulating layer as well as the field insulating layer is arranged on the other hand.