DE2717654C2 - Memory protection arrangement - Google Patents

Description

The present invention relates to a memory protection arrangement for the main memory of a data processing system, by address keys that are dependent on the type of memory access and a Select data block address from a stack of block address registers, preferably without virtual address translation is addressed.

The protection of selected memory areas against unwanted writing or reading with the help of keys is known per se. Each program is assigned keys that contain the ium Identify access to permitted memory areas. So far this has only been a relatively simple and direct one Assignment possible, d. H. there was a fixed assignment between storage area and protection key.

The invention is based on the object for a main memory of the type specified above Specify storage school arrangement in which a very flexible, differentiated according to access or information types Protection of memory areas is possible.

According to the invention, this object is achieved by the arrangement described in the characterizing part of the main claim solved.

Through the combined use of memory protection keys on the one hand and access keys, which are assigned to different types of access or information, on the other hand, the protection of variable memory areas can be adapted very flexibly to the needs. Also is the proposed arrangement Compatible for systems with and without translation of addresses for dynamic memory use.

An advantageous further development of the invention is characterized in that switching devices are provided to select either one of the key selectors, in a key register the processor contained user key or a circuit-related, the monitoring program assigned special key.

This option allows the user key to be retained in the access key register and at the same time to achieve protection against unauthorized access by the monitoring program. It does not need a separate key for the monitoring program instead of the current one used user key to be stored in the access key register. Rather, that arises Ability to monitor access from the monitoring program in another way.

These and further advantageous developments of the invention can be found in the subclaims.

An embodiment of the invention is described below with reference to drawings. It shows

Figure IA-I shows generally the principle of address key selection based on memory access control signals which identify the type of access;

Fig. 1A-2 shows the principle of address translation in general for memory access, the logical input address from a specially generated address key and the address appearing in the program;

Fig. IB an overview of the various possible Memory access types;

Fig. IC in block form an overview of a data processing system with an expandable Main memory, which is described as an exemplary embodiment;

F i g. 1D combines a special embodiment of the in F i g. 1A;

FIG. 2A shows an overview of those occurring in the processor operations and I / O operations Memory accesses, as well as the various address areas;

F i g. 2 B shows an overview of the memory access processes during I / O operations;

3A shows details of an I / O subchannel which receives an address key with each subchannel command and issues this for each data access for executing the command;

Fig. 3B shows the relevant parts of an I / O channel comprising a plurality of sub-channels with a memory priority select circuit connects;

F i g. 3C shows, in block form, a memory priority selection circuit with a channel selection circuit through which I / O channels and processor over the main memory bus are connected to memory and translator, and each have a selected address key as well submit an address for memory access;

F i g. 3D details of an active address key selection circuit, with which an operand range comparison can also be achieved;

F i g. 4 Details of a processor which are relevant for memory access control with address keys are;

F i g. Figure 5 shows the partition format of the address key register in a preferred embodiment;

6 shows the content format in the exemplary embodiment provided segment register;

F i g. 7 details of the input and output control of a single bit position in the address key register;

F i g. 8A schematically shows the operations of a command for loading or storing a segment memory;

8B schematically shows the processes during execution a command for loading or storing the address key register from or into a Storage;

F i g. 8C schematically shows the processes when executing a command for loading or saving the Address key register from or into a general register;

F i g. 9A and 9B show a block diagram of a preferred embodiment of the translator according to FIG a 19-bit long logical machine address into a 24

Converts bit long physical address for memory access;

Figures 9C, 9D-1, 9D-2, 9E, 9F-1 and 9F-2 details the translator shown in block form in Figs. 9A / 9B;

F i g. 9G illustrates the operation of that shown in Fig. 9C Look-ahead circuits for the respective selection of the internal storage (ilasis storage), external storage (additional storage) or asynchronous storage, as well as the interpretation of the 24-bit long physical address by the selected storage unit upon access;

10 shows a circuit arrangement in the processor for selecting between the operating modes »memory protection without translation "and" memory protection with translation ";

F i g. 11 memory protection control circuits for use in translation-free operating mode;

Fig. 12 shows the format of a store-store command;

Figure 13A shows relevant parts of the format of an enable / disable command to define the operating modes with special address range selection (e.g. translation-free Addressing with memory protection, memory protection with translation, operand area comparison);

13B shows successive states of an address key register, if, in the event of an interruption, the operand area is synchronized;

14 shows a circuit arrangement for an alternative Memory protection mode with translation, which is an alternative to the memory protection mode with Represents address key translation;

15 schematically shows an alternative method for address key translation which is implemented in a processor as Can serve as an alternative to the translator arrangement with several register stacks;

16 Access to parallel basic memory modules by means of several active address keys in one Multiprocessor system;

17 control circuit units from the processor, to carry out the in F i g. Segment register load / store instruction shown in Figure 8A;

18 schematically shows the processes for loading and storing in the event of class interruptions.

1. Description of an embodiment

FIGS. 1A and 1B show the essentials Features of an embodiment of the invention. Fig. 1A shows an address key selection circuit

20. Which, depending on the type of memory access request (which are indicated by signals on lines 21, 22, 23, 24 or 25), selects one of the key register sections 31, 32, 33, 34 or 35 which contain the following keys: CS keys. / S key. OPl closing !, OP2-shots! and OP 3 key. The one of these keys which corresponds to the present memory access request is output by the AAS selection circuit 20 as an active address key (AAS). This active address key controls the addressing of the main memory of the system during the next memory access, ie retrieval or storage of data in the main memory. In this addressing operation, the active address key AAS determines the upper part (higher-order digits) of the logical address that is used by the system for memory access

The signals on the access request lines

21, 22, 23, 24 and 25 each represent a different type of access request which can be made by the channels and processors having access to the same main memory. These request lines are designated in Figure IA as follows:. I / O access, instruction access, OPL access, OP2 and OP3 access access. If only one of these access request signals occurs, then the content of the relevant address key register section is immediately output as AAS . If several request signals occur simultaneously, it is determined by priority circuits in the / 4-4S selection circuit 20 in which order the relevant address keys are output as AAS . A certain priority order is given, so that, for. For example, an I / O access request for a cycle steal operation has priority to issue the CS key first. The command fetch request is serviced second to output the / S key as AAS. Third, the OP 1 access request is served in order to issue the OP ! Key as AAS; finally, the OP2 and OP3 access requests are served as fourth and fifth in order to output the OP2 key and OP3 key as / MS, respectively.

So there is a certain relationship between the different types of access requests and the special key register sections.

In a processor, an address key register (ASR) contains the following sections: the / S key section (ISS), which is assigned to the command retrieval requests for access to each instruction, and the key register sections for the keys OP1 (OP iS) to OP3 (OPiS), which belong to the different types of operand accesses required to execute the instructions.

In addition, each I / O subchannel has a corresponding CS Key Register Section (CSS). It can also happen that several I / O subchannels request access to the main memory at the same time. Therefore, CSS priority selection circuits are provided in order to output the CS keys in a predetermined order in the event of simultaneous requests.

In addition, if several processors have access to the same main memory, further priority circuits are provided to meet the requirements of these To operate processors in a predetermined specific order.

Figure IA illustrates the invention in one System with processor and channel unit in which active address keys are used and in which only a part which is used in a data processing system in and of itself possible memory access types. Fig. IB shows a large number of different types of memory access. Those in a particular system usable spoke handle types are based on such which can be identified by the circuitry of the system. That is, it will be in the system Needs circuits that can detect different types of memory access requests, and although in each case at the time when the relevant access request occurs F i g. 1B shows more types of access than the arrangement shown in FIG. 1A is shown in FIG. 1B are eight memory access modes in three Divided into access categories:

(1) command access,

(2) operand access and

(3) an access category representing the processor events assigned

each channel contains K subchannels, and each subchannel has three memory access categories:

(1) channel command access,

(2) I / O data access and

(3) an access category for I / O events.

Each access category has at least one memory access type.

For any particular system, only those memory access modes can be used that are specified in the Machine design by an identifying signal, d. H. a memory request signal is provided are.

So is z. B. denotes the command access category in the system by a command fetch request signal. The operand access category can be defined in the system by six different types of operand access can be identified (Fig. IB). These are divided into direct and indirect operand access types, with the sub-category of direct Accesses those accesses belong to which use addresses which are derived directly from the command, while the subcategory of indirect access concerns operands for which the addresses are derived indirectly from the operand address of an instruction. Each sub-category has three different operand access types, which can be identified by the circuitry of the system as request signals for source retrieval, sink storage and sink retrieval. Each of these six Operand access types can be provided in the construction of a system, and the relevant Signals that can be identified by the system can be derived from any command, namely from the Opcode and from the operand fields. The Get Source Operand Type applies to data saved as Source of an instruction execution: it is not changed, but only used to create the To create the results of a command execution. On the other hand, the sink store refers to the operand type to accesses in which the results of a command execution are saved. the The sink call operand type is the result of an earlier command execution which is used as the source for the Execution of a subsequent command is used. For many data processing systems, however, it was found to be useful in designing the sink dump operand type and the sink fetch operand type group into a single sink dump / fetch operand type.

Processor event accesses are caused by the occurrence of internal processor events such as z. B. Data error. Machine failure. Addressing exception etc .. which make a long list of known ones Events that include the usual processor interrupts, i. H. internal interruptions. The category of processor event accesses can e.g. B. access to an area of the main memory include an interrupt handler and other programs for processing signals associated with the interruption in the Are related, and in which data is still stored that was related to the interruption in Related, so z. B. Closing Records.

Each channel has a plurality of subchannels that perform a variety of different types of access. For example, each sub-channel has an I / O data access category with the types of access I / O retrieval and I / O storage. In some systems, these two are closed by the design combined into a single type of access called I / O polling / storing access. The ones with sub-channel events Related accesses are ■> signaled by interruptions that are necessary for the Processor are external, d. H. external interruptions. There will usually be many different external Used interruptions, e.g. B. the device end interruption, device error interruption, I / O data

error interrupts, etc.

In summary, it can be said that the invention creates the possibility of addressing in main memory for each of the various types of memory access shown in FIG. 1B are shown,

ι ■> to be influenced separately. The in F i g. 1B shown Access types include the eight different memory access types, which are available to each processor, and the four different memory access types, which are available to each sub-channel.

.μ This possibility of separate influencing is given by having one for each of the types of access that are provided in a system provides a separate key register section. The embodiment shown in FIG. 1A is used

r> only four different types of processor access, which in the example chosen are represented by an address key register that has four different register sections. The number of register sections in the address key register ASR can, however, be selected as desired

in are according to the number of different types of access, which are provided in the construction of the system.

In any case, a .45 /? - Regi-

n ster section or a CS register section is provided with corresponding devices in the /4.4S-AuS- selector circuit. by a selected register section read out when the corresponding access request is served, with the content of the

απ selected register section becomes the active address key, which the system uses as an address component in order to influence the addressing process for the relevant memory access. For the given by the active address key AAS Adreßkompo-

>', nente can be:

(1) It can have a direct relationship to the physical address by connecting the AAS with the program

. ₍₎ address is concatenated so that both together result in a physical address in main memory;

(2) It can enable a permanently specified memory access in the main memory, as in the exemplary embodiment shown in Fig. 11;

._ (3) it can be used to determine a relocatable address for memory areas identified by keys serve, whereby sequential program addresses are required within each area, as shown in FIG. 15 is shown;

_(| (4) it can be used in an even more flexible manner for the determination of shiftable addresses, with address shifting also still possible within the areas identified by the key, as shown in the exemplary embodiment in FIG. 1A.

The main memory entry address identified by the in Fig. 1A is provided

the combination of an active address key AAS with an address appearing in the program. The latter is an address which the system sees in a program being executed, such as e.g. B. the instruction fetch address in the instruction address register, and the operand addresses in the instructions of the program. When a program is written, only addresses appearing in the program are known. The application programmer only cares about the / 4y4S operations to the extent that he combines his operand data separately from the program. The system programmer generally specifies the processor event access areas and their contents, and the I / O programmer generally specifies the I / O channel command and event access areas and their contents. In FIG. 1A, the 44S component occupies K bit positions in the higher-order part of the combined input address, and the address appearing in the program has 16 bit positions, so that in total it results in an input address for the system with 16 + K bit positions.

In the arrangement shown in FIG. 1A, the input address including the / I / AS field is a logical machine address for which a translation is still required in order to reach a desired storage location in the data processing system. On the other hand, in the in FIG. 11, the active address key AAS is used as directly used restrictions on the physical address which is not translated.

A. Translator with stacks of tabs

The translator shown in FIG. 1A contains a plurality of segment register stacks with the numbers 0 to ^2K . Each key register section in the processor or in a subchannel contains at least one key with K bits which can be used to address each of the stacks.

The active address key AAS is entered into a batch addressing device 40 and decoded in order to select the desired batch. Then a segment register (SR) within the addressed stack is selected with the higher-order bit positions 0— P of the component of the input address that appears in the program. Bit positions 0 to 12 of the selected segment register contain an assigned block number which represents bit positions 0 to 12 of the physical address of a particular physical block in main memory which is then accessed.

The remaining bit positions 13-23 of the physical address, which comprise 24 bits, indicate the relative byte address (D) within the selected physical block; they are identical to the relative byte address D in the input address, where they are in the lower-value bit positions (P + 1) to 15. Access to a particular physical block is also controlled by identifier bits in the remaining bit positions 13-15 in the selected segment register SR. The division of the segment registers SR is shown in FIG. 6 shown; the content of the validity bit position 13 (V) indicates whether the content of the block number field is valid. If it is invalid (ie V = O), the content of the selected segment register cannot be used to generate a physical address, and it an addressing exception interrupt then occurs. The identifier bit position 14 indicates whether the addressed block may only be read. If bit 14 is set to one, the block in question may not be written to, and only polling accesses are then permitted. Bit 15 is not used. The second word with the bit positions 16 to 31 is reserved and is also not used for the present exemplary embodiment.

B. Expandable main memory

F i g. IC shows the configuration of a data processing system, the one new expandable

ίο Has main memory for processing translated addresses. The main memory consists of at least one internal memory section 51, hereinafter referred to as internal memory for short, which has a storage capacity of up to 64 K bytes. The first possible extension is addition

i> an external memory part 52, hereinafter referred to as external memory for short, by means of which the memory can be expanded by 64 K bytes so that the main memory then comprises 128 K bytes. Then an expandable asynchronous memory 53, in the following

2 (i also called asynchronous memory for short) can be added, with which the capacity of the main memory can be expanded to a maximum of 16 777 216 bytes (ie 2 ²⁴ ).

A translator 59 is provided for address translation.

2i hen, which also contains interface facilities for the Connection of external storage 52 and asynchronous storage 53 to the main storage configuration.

A main memory bus 56.4 (with bus are below Collectors designated) connect; a process

Jd sor 54 and an I / O channel 55 through a memory priority selection circuit 56 with the main memory configuration. The main memory bus 56A is also connected to the translator 59 and to the internal memory 51.

Internal memory cycle signal lines 54Λ connect internal memory 51 directly to memory priority selection circuit 56. They carry internal memory cycle signals (7SZ signals) which represent 16-bit untranslated physical addresses generated by the processor when it is in non-translation mode. When the processor is working in translation mode, the five most significant bits for ISZ are provided by the translator; they contain a card selection signal (which

4> select the correct card from up to four cards that make up the internal memory) as well as the CSY and CSX fields (which select a specific memory area on the selected card, these areas being 4096 bits). The five most significant bits on the

V) Address bus lines 00-04 are transferred from the translator to the processor in order to be used by the latter during an internal memory cycle / SZ. Bit 13 to 22 are output from the memory address register of the processor in order to select a specific word location in the memory area, and the last bit 23 selects a specific byte in this word if it is a write operation Used for write operations, since read operations only address whole words (1 word contains 2 bytes). For a write operation, the last address bit 23 is set either to 0 or to 1 in order to address either the left or the right byte in a word.

If the processor only works with the internal memory (i.e., if there is no external memory in the system and no asynchronous memory is provided), then the processor only addresses the internal memory with physical, 16 Bit long addresses from the memory address register

can be handed over directly to bus 54/4. The 16-bit addresses provided by the processor are sufficient just about to address the maximum capacity of the internal memory (i.e. 64K). With this minimal configuration are used with the 16-bit long physical addresses memory protection keys according to the Non-translation memory protection circuits shown in FIG. 11 are shown.

The memory protection keys use the option of determining which address areas are separately is given by the address key register sections for different types of memory access. The combination of the active address key selection circuits with the memory protection keys also belongs to the in invention illustrated in this specification. The feature of the active address key circuits shown here, by which separate address area determinations are possible depending on the type of memory access can be combined separately, either with the use of storage keys when using not relocatable addresses or with the use of address keys when using relocatable Addresses.

If one desires the possibility of address shifting, which allows the main memory to be expanded beyond the capacity limit of the internal memory of 64K, a translator must be provided as shown in FIG. IC. An external memory can then be added which is connected to the translator by external memory cycle signal lines 58 which enable the external memory cycle control (OSC) shown in FIG. 9G is shown.

The translator also enables the main memory to be expanded beyond the capacity limit of 128K, which applies to the internal and external memories, by adding an asynchronous memory unit. The asynchronous memory unit uses the translated, 24-bit addresses in a different way than the external memory, as shown in FIG. 9G for the asynchronous storage cycle (ASZ) is shown. The bit positions 0 to 6 are used in the asynchronous memory cycle .45Z, and at least one 1 bit is in these bit positions because more than 16 bits are needed to represent a number that is greater than 128K. By using bit positions 0 to 6, the asynchronous memory cycle differs from the external memory cycle, in which these bit positions are not used; only bits 7 through 23 are used in the out-of-memory cycle. These special conditions for bit positions 0 through 6 are used to set a pair of look-ahead bits which are shown in FIG. 9G, with the associated one being expandable from 64K, a translator must be provided as shown in FIG (OSZ) allow the in F i g. 9G_ is shown

The translator also enables an additional expansion of the main memory beyond the capacity limit of 128K, which applies to the internal memory and external memory, by adding an asynchronous memory unit G. 9C for the asynchronous storage cycle (ASZ) is shown in the asynchronous storage cycle ASZ , the Bif positions 0 to 6 are used, and in these bit positions there is at least one 1-bit, because you need more than 16 bits to represent a number that is larger than 128K -, is. By using bit positions 0 to 6, the asynchronous memory cycle differs from the external memory cycle, in which these bit positions are not used; Only bits 7 to 23 are used in the external storage cycle. This particular one

ίο Conditions for the bit positions 0 to 6 are added is used to set a pair of look ahead bits shown in Figure 9G, with the associated Circuits and processes are described in more detail in connection with FIGS. 9A and 9B

i) be.

The translator has a connection to the main memory bus interface, over which he logical addresses including the active address key from the processor for the translation. The translator contains

2 (i also interfaces for the external storage tank and the Asynchronous storage.

C. Address Range Distribution

2A shows the relationships between the 2 ") different types of memory access which are caused by different types of processor commands and channel commands, and the corresponding data address areas used in the exemplary embodiment. In FIG. 2A, only a κι subset of the types of access is used As shown in Fig. 2A, an instruction fetch is carried out in the instruction address area 60 using the / SS and 62 are executed using the contents of the key register sections OPIS and OP2S.

Cl processor address range distribution

4 (i FIG. 2A illustrates the memory accesses which are carried out on the basis of different types of processor commands. A memory memory command calls up data in the OP IS data area 61 or in the OP2S data area 62 and stores the

<r> Results in the OP2S data address area 62. An instruction for direct memory operations fetches its data from the ISS address area 60 and stores its results in the OP 2S data address area 62 or in a general register (AR). A register-store instruction moves data from general register 63 to OP2S data address area 62; a store register instruction fetches data from the OP 2S data address area 62 and stores it in a general register 63. A branch instruction fetches a branch target instruction from the ISS address area 60 as well.

C2 I / O subchannel address range distribution

Two different types of I / O subchannel commands are shown in Figure 2A Called a direct program control I / O instruction

(DPS I / O) and causes an I / O operation that runs synchronously with the main program, i. That is, the main program does not continue until the I / O operation is complete, and both the I / O command and the data are taken from the OP2S address area 62.

The other I / O command type has the normal effect of asynchronous I / O operations, which in general

known as cycle steal I / O (CS) operations. For this second command, the I / O program itself (ie the channel commands) must be stored in the "key = 0-Kanalprogrammadreßh sreich" 64 (see FIG. 2A), while the data accesses, which ■> for the channel program are carried out, are controlled by keys which are specified in the relevant channel commands, so that each channel command (z. B. GSB) can select a different one of the address areas 65 to 66. This means that each I / O device has its own sub-channel program in which the commands have the option of entering a different key value in the address key register section of each sub-channel, so that it is possible for each sub-channel to assign each channel command with ι ί to access another address range. This means that each channel has the option of moving the data address area to which it is accessing as required.

F i g. Figure 2B shows in somewhat greater detail the manner in which the I / O operations determine their address keys to select different data address areas in main memory.

As shown in Fig. 2B, the main program contains an I / O operation command which initiates an I / O operation 2ϊ, and therefore the I / O operation command is in the / SS address area. The OP code portion of the instruction indicates that it is an I / O operation instruction, and the /? 2 field designates a register, the contents of which must be combined with the address field «1 in order to generate an address which directly or indirectly denotes an »indirect device control block« (IGSB) in the OP2S address area. If indirect addressing is used, the indirect address itself is in the OP2S address area. The IGSB- r> address is either a direct or an indirect address, depending on the value of the / bit in the I / O operating command. This means that the I / O operation command is in the / SS address area and the IGSB is in the OP2S address area. ■ »»

There are two types of indirect device control blocks IGSB:

(1) A CS type or

(2) a type of DPS. -r>

The channel command field CMD in the IGSB indicates whether a CS operation or a DPS operation is being initiated. If the IGSB is a DPS type, its second word contains direct data that is either transmitted to or received by the device addressed ίο, depending on whether the channel command field CMD indicates whether there is an I / O read or Write operation is.

If the CMD field indicates that the IGSB is of the v> CS type, the second word in the IGSB contains the address of the sub-channel program for the device which is addressed by the CA field in the IGSB. The first channel command (ie channel control word), which is called device control block 0 (GSB-O) , is located in the address part of the IGSB. A field in the CSS-O. which is called the concatenation address indicates the location of the next subchannel control word which is called GSB- \ and which also contains a concatenation address which locates the next GSB · "and so on until the last CSß is found.

In this embodiment there is therefore that entire channel program in the »key = 0 address area«.

However, each device control block GSB holds a key field in its first EA , which is the address key for data accessed by the GSB concerned. GSB-O contains z. B. a key field, which is referred to as the key for GSB-O and which specifies the address range for a contiguous block of logical addresses, which begins at the data address contained in the field of GSB-O that is at the position £ 4 + 14 is located. The key for GSB-O can have any key value. Similarly, the next control word GSB-X contains a key for GSB-X, which can have any key value, to define the address area for the data which are addressed within GSB-X. The key value in GSB-X can therefore be different from the key value in GSB-O etc.

It can be seen from this that the invention results in a very high degree of flexibility in the selection of the address range during the operation of I / O devices in the system. When using memory protection keys without translation, different key values can be used in the device control blocks GSB in order to obtain special, selective memory protection for the I / O data accesses.

If, moreover, the system is working in translation mode, all I / O data addresses are used for each access translated by the translator (see Fig. 1 D) in the same way as the processor addresses to be translated.

Figure 3A shows circuit details for controlling the GSβ key operations. Each I / O subchannel contains a small processor-like control unit for controlling the operation of an attached I / O device, which can be of any type. This processor-like control unit controls the processing of the GSß keys through the relevant I / O subchannel. The GSß key is entered in a GSß key register 301 in the sub-channel control unit from the I / O data bus of the channel when a device control block GSB in the key = 0 address area is taken.

A plurality of subchannels are connected to a single channel in the usual manner. Each subchannel can communicate with its channel using protocol signals specially provided for this purpose. A subchannel requesting service by the channel is selected by a calling process. After the selection by the calling process, the channel data bus transfers control signals and data between the subchannel and the main memory. A signal which is passed from the call selection controller 310 to the subchannel / OS controller 311 causes a word from the read only memory ROS 312 to be entered into a ROS data register 313 in order to control the necessary subchannel operations. One of the subchannel operations is a GSß retrieval of the next address field in the current GSB from the address area with key = 0. The GSβ request field in a /? OS word is decrypted by a ROS decoder 314 , which then outputs a GSβ request control signal which activates AND gates 315 (0), 315 (1) and 315 (2), which cause an entry in the GSB key register 301 , which is part of the register stack which receives the entire device control block GSB. After the GSß poll is executed. if the GSB is stored in the subchannel, the GSß polling signal

terminated and a "no GSß-Abruf" control signal is activated which enables the AND gates 316 (O), 316 (1) and 316 (2) to output the GSß key from the GSß key register so that it can be used as CS Key is available for GSß data access operations. The CS key is transmitted to the channel in Figure 3B via the condition code bus. The channel then transmits the CS key to the CS key bus associated with the memory priority selection circuit in FIG. 3C is connected.

CSS storage priority selection policy

In Fig. 3C, the CS key is shown from the channel bus to a channel selection circuit 331 which is connected to the channel buses of all channels connected to the processor and which gives priority to a CS key from one of the channels.

A plurality of control lines are also connected to each subchannel control unit, including a : u control bus and an I / O address bus. The I / O address bus transmits the data address which was derived from the GSB. The I / O control bus includes a CS request line which indicates whether an address is on the I / O address bus (Fig. 3B).

The memory priority selection circuit 56 is connected to CS cycle request lines of each of the channels 1 ... P which are connected to a processor. A specific CS key is selected by the circuit 332 and sent to the channel selection circuit 331, which transmits the CS key of the selected sub-channel to the A4S selection circuit 333, which also transmits the processor address key from the processor / \ S /? Buses obtain. Under the control of the memory priority cycle circuit 332, the ^ / tS selection circuits 333 each select one of the received address keys as the active address key AAS of the system. 3D shows details of the AAS selection circuit 333.

D. Processor

FIG. 4 shows details of the parts of the system processor which are essential for the description and which, if necessary, tries to access the memory at the same time as the CS keys. The processor 4S / i buses (bus lines) are connected to the outputs of the address key register ASR . The memory priority cycle circuit 332 (FIG. 3C), which can be of a known type, determines the order in which the competing requests are granted access, that is to say the order in which the corresponding address keys are used as active address keys AAS at the outputs of FIG / 4S select circuits (Fig. 3D) appear.

4 shows those control devices in the processor which cooperate with the address key ASR . The ASR is loaded from the processor data bus (data bus) by means of the input control (EG). and the various address keys are output from the address key register onto the processor data bus with the aid of the output control (AC). The EG and 4G control signals are issued by the processor ROS decoder. The content of the address key register ASR is continuously transferred to the processor ASR buses, namely the / SS bus, the OP2S bus and the OBA bus. which are connected to inputs of the SS selection circuit 333 (Fig. 3C), details of which are shown in Fig. 3D. The / 4AS selection circuits make the selection between these three processor keys and CS keys which are present approximately at the same time and thus determine which of these keys becomes the active address key AAS. F i g. 7 shows in detail the / 4S7? Control circuit based on the input and output circuits for a single bit position of the ASR. All other bit positions of the ASR have corresponding control circuits.

From Fig. 4 it can be seen that the processor ROS decoder 405 (read-only memory decoder) has output lines, each of which is activated by a particular ROS word when this is entered in the KOS data register 406 , in order to enable input and output at the 4SÄ- To control register sections ISS, OPiS and OP2S or to initiate other processor operations.

Dl register for last active
Address key AAS

The processor shown in FIG. 4 also contains a register for the last active address key, to the input side of which a / 4 / 4S gate circuit 407 is connected which, on the one hand, is connected to the v4 / 4S bus of FIG. 3D is connected and on the other hand to an inverter which is connected to a processor error flip-flop 401 . The output of the AAS gate circuit 407 is entered into the last active address key AAS register 408 when a processor memory cycle signal (of Fig. 17) is present. Register 408 stores each active address key present on the AAS bus from the processor address key register ASR. provided that the fault toggle circuit 401 does not indicate a fault on a fault blocking line.

If, however, a machine error (MCK) or a program error (PCK) occurs in the processor, the error flip alarm 401 is set. As a result, the / 4 / tS gatekeeping 407 is locked because the error lock signal a! falls to thereby have back the last active address key of the processor (LKSA). which was at the time the error toggle 401 was set. The machine error signal (MCK) and the program error signal (PCK) are input to a forced address decoder 402 (except during a segment register cycle) to force a read-only memory address into the ROS control circuit 403 , which causes a diagnostic program to be called, which either removes the error condition by repeating the faulty function until it is performed correctly, or by performing a logout operation if the fault is determined to be a persistent problem. The 44S register 408 now holds the LKSA to maintain the last valid address range setting while the processor is performing error recovery operations so that once the error condition has been corrected, the system can resume work while retaining the last used address range setting.

One of the last diagnostic operations that are carried out before the status of a processor can be changed is the storage of the overall status of the processor in a level status block (NBS) in main memory, including the content

belonging to the address key register ASR . A signal AGAASR (output from the register for the last active address key) outputs the content of register 408 (LKSA) to the processor data bus; a simultaneously occurring signal EG OP 1 S causes the LKSA to be entered in the OfI K register section of the ASR for the diagnostic or error correction operations (see section H3). When the debug operations are complete, the last normal ASÄ value is reloaded from the NSB in memory to resume normal operation.

D.2 Commands for loading / saving the ASR

Fig. 8B and 8C show the commands for controlling the following two operations:

(1) Loading the address key into the ASR either from a word location in main memory or from a designated general register AR;

(2) the storage of address keys by the ASR either in a word position in the main memory or in a designated general register A R.

F i g. BB shows the processes when executing the command »AS7? / Load / Save memory«. This single command can be used to control either the loading of the ASR from the main memory or the saving of the contents of the ASR in the main memory.

F i g. 8B shows the division of the 16-bit long command »ASÄ / Load / Save memory«. It is characterized by the 5-bit OP code and the 3-bit modifier field in bit positions 13 to 15. The / C field in bit positions 5 to 7 addresses the part of the ASR (or the whole ASR) ₁ to be entered or output. The K values O, 1, 2 or 3 designate the register sections ISS, OP2S, OPiS or the entire ASR for use by this command. A logical main memory address is generated with the aid of the /? Ss field in bit positions 8 and 9, which designates a base register, and access mode bits 10 and 11 (AM), which indicate whether a word is an appended field to an instruction which contains an address field, the contents of the AM field and the RB register being combined in order to generate the effective address of that word position in the main memory which is either loaded or stored by the execution of this instruction. Bit X in bit position 12 indicates whether it is a load command or a save command. If Λ "= 0, then the content of the addressed word position is stored in that ASR-TeW which is identified by the AC field. If X-Bh = 1, then the specified AKR-TeW is in the addressed word position saved.

In a similar way, FIG. 8C shows the operations carried out when executing the command "AS /? / Register Load / Save"; the only difference from FIG. 8B is that a general register AR is used instead of a main memory word location when this instruction is executed. Accordingly, in FIG. 8C, the /? Field in bit positions 8 to 10 designates a specific general register AR which is used for loading or storing one or more keys in or from the designated part (or designated parts) of the ASR is used.

The corresponding operations are carried out in the processor on the basis of signals on the output lines labeled EG or AG of the processor AOS decoder 405 (FIG. 4), which with the signals occurring on the data path of the processor are those described in connection with FIG Initiate operations.

E. Translator

9A and 9B contain details of the in FIG. IC shown translator 59, wherein the translation operations described with FIG. IA for Adreßverschiebungen making the Adreßverschiebungs translation circuitry may the physical address range of 64K (2 ¹⁶⁾ bytes to 16 million (2 ²⁴⁾ bytes larger, which thus an extension of the internal memory of 64 K Bytes

The address range of the main memory is enlarged by the translator as it takes the active address key AAS and the 16-bit long address appearing in the program from the processor or from a subchannel as a logical input address and converts this input address into a 24 Bk long physical address. the

2ϊ Access to internal storage, external storage or Has asynchronous storage.

This translation process enables the dynamic allocation of physical storage capacity to become logical Address ranges and sharing

ίο physical storage capacity of several logical address areas. 8 sets (stacks) of 32 segment registers (SR) each are provided for the 8 different possible values of the address key, which results in a total of 256 segment registers. Each loaded stf stack

ii can be a complete mapping of a memory area containing up to 64K bytes, which are distributed in blocks of 2K bytes each can. A stack can also be used to address an address range that has fewer than 64K bytes by

-to just put the validity bit position in an or sets several of the segment registers to one, so that only those segment registers for which the validity bit = 0, which denote blocks with a capacity of 2K bytes each, which become an addressable area

<n belong to that by an assigned address key is identified.

A separate segment register stack is provided for each address key to enable rapid switching of the logical address areas without the

"> <> Necessity of path storage and re-storage the system's address space mappings.

The address shift translator shown in Figs. 9A and 9B allows expansion

^r i ^r ) of the main memory by an external memory of up to 64K bytes in increments of 16K bytes on one card each, which are designated as the fifth to eighth cards for the external memory. The internal memory consists of the first to fourth cards, whichever one

w) have a capacity of 16K bytes. Extensions to the Storage capacity beyond the 128K bytes of the internal memory and external memory require one additional asynchronous storage unit (Fi g. IC) which the physical memory of 128K bytes up to

<"enlarged to a maximum of 16 million bytes can verden.

The largest address area that can be statically addressed by the machine, which is all simultaneously running

Programs available when all segment registers are loaded with different physical block addresses is 2 ¹⁹ bytes. This limit is determined by the 19-bit long input address, which is shown in FIG. 1A and which occurs when a 3-bit long active address key is appended to the 16-bit long address appearing in the program in order to generate a 19-bit long logical machine input address for the translator. For a single program there is the option of addressing up to three different address areas, which are defined by the three sections of the ASR , namely ISS, OPiS and OP2S. which means an addressability of an address range of max. 64K. results in up to max. 192 K bytes.

That is, for a physical main memory with a capacity between 512K bytes and 16 million Bytes results in an addressing option of only up to 512K. Bytes at a particular loaded Content of the segment register; this is called the greatest static machine addressability. if addressing via the 512K bytes of the If you want to make a static maximum, you have to reload the segment registers by programs, in order to obtain addressability of other areas in the main memory.

The static addressability can easily be increased by adding more bits to the address key in the ASR and by increasing the size of the associated circuitry in order to support a correspondingly larger number of segment register stacks.

If a translator is built into the system as shown in FIG. 1A, its use is controlled by bit number 14 in the processor status word (PSW) through output lines of the processor FLOS decoder in FIG. 4 when the enable / disable command shown in FIG. 13A is present. Bit 14 in the enable / disable command indicates whether a translator is provided in the system or not, and bit 7 indicates whether it should be enabled or disabled. The in F i g. The circuit shown in FIG. 10 determines whether or not the translator is enabled. When the translator is not enabled and when the 5P bit in the instruction shown in Fig. 13A is set to 1, the non-translation memory protection circuit shown in Fig. 11 is used. If addressability is only required in a small address area and if very fast processing is required, the translator can be blocked.

Fi g. 9A and 9B show in detail the circuits, Bus lines and interface lines for the translator 59 of the system of Fig. IC according to the following list:

E.1 Processor / translator interface

(1) Memory address bus 901. It has 15 lines which carry the logical program address from the processor's memory address register (SAR) to the translator. After the address translation, the five most significant bits of the translator address are sent back to the processor in order to be used for addressing the internal memory 51, if necessary. The 10 low-order bits (D-field) do not need to be translated.

(2) Memory data bus 902 to memory. It contains 16 data lines and two parity lines. It transfers memory data and segment register contents from the processor to the translator.

(3) Memory data bus 903 from memory. It contains 16 data lines and two parity lines. It transfers memory data from the translator and the content of the segment register (SR) to the processor.

(4) 3us for active address key (/ MS-Bus). These three lines transmit the active address key AAS from the memory priority selection circuit (FIG. 3C) to the translator in order to select a particular stack of segment registers in the translator.

(5) Memory writing OPO. Single line from the processor that signals to the translator that a

η write operation in memory is to be carried out with the left byte of the word currently on the memory data bus to memory. This line is activated when the lowest bit number 23 of the 24-bit physical address equals 0.

(6) Memory writing OPl. Single line from the processor, which signals to the translator that a write operation is to be carried out in the memory with the right byte of the word that is on the memory data bus to the memory. This line is activated when the lowest bit number 23 of the 24-bit physical address equals 1.

(7) Translator approval. Single line that sends a processor signal to the translator that the

Approves the translator for his function. This signal is activated by the enable / disable command.

(8) Memory requirements for translators. This single) ■) line transmits a processor signal which asks the translator for the logical address of the To translate memory address bus. A micro cycle (220 nanoseconds) is automatically skipped, to give the translator access to the

mi relevant segment register to enable to determine the physical address and to determine whether access to the internal storage, External storage or asynchronous storage is required.

■ ij (9) timer pulses A, B, C, D. These four lines carry processor timer pulses of 55 nanoseconds in duration, which establish synchronism between the processor and the translator.

ίο (10) pass on translator / SAR . The signal on this line indicates that the translator has placed the five most significant bits of the translated physical memory address on the memory address bus 55 nanoseconds after the start of this signal. It causes the processor to pass bits 00-04 of the translated address from the address bus to the internal memory.

(11) Internal storage cycle (ISZ). This line transmits a signal generated by the translator, which the

to the processor to provide the internal memory 51 with a storage time signal with each new physical address. If an external storage or asynchronous storage cycle (OSZ or ASZ) is to be executed, this will be

b5 line deactivated, so that the inner memory is not selected.

(12) Translator memory occupied. This line transmits a signal generated by the translator,

Should stop clock signals. This line is only activated when the asynchronous storage unit is accessed 53. When the translator receives the appropriate response from the asynchronous storage unit 53 this line is deactivated and the clock signals are started again at the End memory cycle. This shutdown of the memory clock signals by an asynchronous memory unit is the reason for their asynchronous operation and the reason that their access cycle is longer than the access cycle for Internal storage 51 or external storage 52.

(13) Translator built in. This line transmits a signal generated by the translator, which the Processor indicates that a translator 59 is built into the system.

(14) Translator invalid memory address. This line carries a signal generated by the translator which indicates to the processor that the logical address just transmitted to the translator is invalid; a program error display (PCK) then appears.

(15) Translator memory protection indicator. This line transmits a signal generated by the translator, which indicates to the processor that an attempt has been made to enter a block in memory write, in whose segment register bit 14 is set to 1, which indicates that for only read operations are allowed in this block.

(16) Monitoring program status or cycle steal cycle. This line transmits a signal generated by the processor to the translator, which indicates that this should ignore the read-only bit 14 in the addressed segment register, because the present memory access request either from the monitoring program or from comes from an I / O subchannel.

(17) End of cycle. This line transmits a signal generated by the processor, which is sent to the translator indicates that the memory cycle is now ended.

(18) Segment register cycle. This line transmits a signal generated by the processor which indicates to the translator that the segment registers are being activated. At the same time, the lines Write Memory OPO or Write Memory OPX are used to indicate whether the cycle is a read or write cycle as part of a “save segment register” or “load segment register” command.

E.2 Translator / external storage interface

The interface from the translator to the external memory is shown in FIG. 9B. It includes the following Cables:

(1) Card select lines. These four lines which are labeled with card selection 8OK, 96K. 112K and 128K, choose one memory card each of 16K bytes in the external memory.

(2) TCSX and TCSY lines. These six lines carry X coordinates and V coordinates for the selected map in order to select a specific area on that map.

(3) "Write byte O" and "Write byte 1" lines. These four lines transmit

Timer signals to the four external memory cards to write a byte.

When the translator receives the physical memory address from the corresponding segment register, it is determined whether access is made to the internal memory, the external memory or the asynchronous memory got to; it only activates the interface lines to the external storage when an external storage cycle is in progress is required. The cable bridges that are built into the external storage tank control (Fig. 9B) indicate which of the four cards of the external storage unit are installed.

E.3 Translator / asynchronous memory interface

The interface from the translator to the asynchronous memory (Figs. 9A and 9B) comprises the following lines:

(1) Asynchronous storage output data / parity. These 16 data lines and two parity lines form the memory data bus to the asynchronous memory unit.

(2) Asynchronous storage input data / parity. These form 16 data lines and two parity lines the memory data bus from the asynchronous memory unit to the processor and to the channel.

(3) Asynchronous storage lower SAR off. These 13 lines carry the 13 most significant bits of the physical address, which form the block address in the asynchronous storage unit. They form the upper SÄft bits 0-12, which in the asynchronous memory cycle in FIG. 9G.

(4) Asynchronous storage upper SAR off. These ten lines carry the 10 low order bits 13-22 in the asynchronous storage cycle, but not picture 23 of the asynchronous storage cycle (FIG. 9G). Figures 13 to 22 address a word in the selected block.

(5) Byte 0 write. This line transfers the lowest bit # 23 of the physical address indicate whether the left byte of the addressed word during the asynchronous memory cycle for a memory operation is used.

(6) Byte 1 write. This line informs the asynchronous memory that the right byte of the addressed word is subject to a memory operation during the asynchronous memory cycle.

(7) Asynchronous memory selection. This line indicates to the addressed memory module that eir Storage cycle is to be started. This election line is only activated during a Asynchronous memory cycle and if there is no logical command address and no memory protection display detected by the translator.

(8) Interface cycle and interface cycle 90 °. These two clock signals have a period of 44C Nanoseconds with a pulse duration of 50% prc period. The two clock signals have one Phase shift of 90 ° to each other; they are only active when the asynchronous memory is off dial signal is also active. These clock signals can be stored in the asynchronous storage unit for the following: can be used: synchronization within the storage unit to avoid problems Rewriting, storing of data in flip-flops and for generating responses Signals at the specified times.

(9) Reply. An S appears on this line ^; gnal from the asynchronous storage unit if the addressed storage space is installed.

(10) Write timing signal. This line to the selected asynchronous storage module is during activated in the second half of the write cycle after the translator received a reply would have. The write timing signal is only activated if the select line is also activated is.

(11) Normal asynchronous storage cycle end. On this Line is given a timing pulse when the response line receives a signal from Synchronous memory receives. It is used as a confirmation signal by the selected asynchronous storage unit used to reset the trigger circuits set during the cycle and to re-select to prevent during the same cycle when the asynchronous memory selection signal falls.

E.4 Segment register selection

Details of the segment register control circuits are shown in FIG. 9C shown. A segment register is selected by a concentration method. First, the desired memory location is selected in all register stacks by addressing all registers with the higher-order bit positions 0-4 of the logical address appearing in the program, so that the content of the selected register is output from each stack. A selection is then made among the stacks with the aid of the / tAS bits, one of the eight preselected registers being finally selected by this selection. This is achieved by first using the value of A / 45 bit 2 to first select four of the preselected segment registers for restriction, either from the even or the odd stacks. The lines applied by the AAS-Bn 1 with the signal real (T) and complement (C) are then used to select only one of the two groups of stack output signals, namely either the stacks 0, 1 and 4, 5 or the Stack 2, 3 and 6.7 (here the comma between the stack numbers means "or"). The output signals from a pair of registers are used, either from stacks 0.1 and 4.5. when -4 / 4, S-Bh 1 is in state 0. or from stacks 2,3 and 6.7. when the AAS-Bh 1 is in state 1. From the selected pair, a single register is finally selected based on the state of the S /? - high-low selection bit (AAS-Bh 0) which the concentrator 921 in FIG. 9A is supplied, which makes a selection from the preselected pair of stacks and finally only outputs the output values from a single register from a selected stack.

E-5 control for loading / saving
the segment register

F i g. 8A shows the operations of the instructions for loading and storing the segment registers (SR). F i g. 17 shows the processor memory control and FIG. Figures 9A and 9B show the associated translator controls needed to execute these commands.

In Fig. Figure 8A shows how the "S /? Load «controls the entry of a physical block address into a selected segment register from an addressed word storage location in main memory. The command »SR Save« causes the contents of a selected segment register to be copied into an addressed word memory location in the main memory.

The format of the 16-bit long commands for loading and saving the segment registers is determined by a 5-bit long OP-Codc and a 3-bit long modifying field, which are in the bit positions 0 to 4 and 13 to 15.

Bit X in bit position 12 of the S /? Command indicates whether it is a load or a save operation. When X is set to 0, the contents of the addressed word storage location in main memory are loaded into the selected segment register. If the A "bit is set to 1, then the content of the selected segment register is stored in the addressed word memory location.

The /? - Fe! D in bit positions 5 to 7 addresses a general register (AR) which contains the address of the selected segment register which is to be loaded or whose content is to be saved. In the general register, the key field in bit positions 5 to 7 is a batch number which identifies the selected batch, and ΛΛ-bit positions 0 to 4 contain a segment register number which identifies the selected segment register, which is loaded or saved from the shall be.

The desired word storage location in the main memory is addressed with the aid of a logical address which is generated using the /? Ss field in bit positions 8 and 9, which specify a base register: the / 4M field in bit positions 10 and 11 (type of access) indicates. whether an access type word follows the instruction. The content of the access type word (AM word) and the /? Ss register are combined in order to generate the effective (ie appearing in the program) address of the main memory word position which is to be loaded by executing the instructions or to be saved from. If the system is operating in the translator mode, the generated effective address is entered into the translator (FIGS. 9A and 9B) together with the active address key AAS. to form a logical machine input address. The translator provides a 24-bit physical address. with which access to the addressed word memory location is possible. It is thus possible that the previous content of the segment register which is to be loaded is used in a translation operation before this content is changed to a different physical block address by the segment register load command.

When the processor is not operating in translator mode, the effective address generated is the physical address in main memory.

Bits 13 and 14 of the addressed word memory location in the main memory contain the values for the validity bit V and the read-only bit R. which are to be loaded into the segment register in order to control its effect when it is used for a requested translation.

F i g. 17 shows the control devices of the processor which are used when the instructions for loading and unloading are executed. Saving the segment register can be used. These control circuits in the processor generate a Segment register cycle signal. which is used by the translator (Fig. 9A and 9B) to load or To effect storage of a segment register.

A command to load or save a segment register calls up microinstructions in the processor which generate a signal “Request for loading / saving a segment register” and then a signal for a processor request for a memory cycle. The first signal sets a multivibrator 481 "SR request follows" (FIG. 17), and the second signal arrives at an AND element 482, which is enabled by the Γ output signal of the multivibrator 481. When the output signal of the AND element 482 is active, an Sfl phase toggle circuit (PH) is set for one cycle; the output of which activates the AND gate 484 when the translator is installed. The output of AND gate 484 sets a toggle 486 "S / f request" to indicate that access to a segment register is required. The Γ output signal of the flip-flop 486 enables the AND gate 488 in order to generate an S /? Cycle signal, provided that there is no CS cycle request, since CS cycles have the highest priority. The 5 /? Cycle has the second highest priority and a normal processor memory cycle has the lowest priority; this is effected by an AND gate 493 which generates a processor memory cycle signal on line 494 only when there is no 5>? request signal from the C output of the flip-flop 486 at its input. The other input of the AND gate 493 is connected to the Γ output of the processor cycle flip-flop. (The 7 output of a multivibrator gives the real or true output signal, while the C output gives the complementary signal.)

If the AND gate 488 is enabled by the T output signal of the flip-flop 486 during the execution of an instruction to load or save a segment register, its other input receives the Γ output signal from the processor cycle toggle circuit 490, which is activated whenever a memory cycle request is made from the processor. The flip-flop 490 is set by an output of the AND gate 491; one of its inputs receives the signal »no CS cycle« for release (which occurs when there is no I / O memory access request). The other input of the AND gate 491 receives the release of the Γ output signal (true output signal) of the processor memory request toggle circuit 492, which is always set when there is a processor request for a memory cycle.

While a segment register cycle signal is present on line 923, the segment register to be selected is addressed by the current address in the processor memory address register SAR. A selection operation for the segment register is then carried out in the same way as was explained in the description of the translator in the section »Segment register selection«.

As already mentioned, the binary value of the X bit in the instruction determines whether a load or store operation is being carried out; for this purpose the X bit selects a load or store micro-routine from the processor fixed memory ROS. For a segment register load operation, the microroutine first generates a processor memory request, during which the word addressed by the SÄ instruction is fetched from the main memory and entered into the processor memory data register SDR

Segment register, followed by a further processor request for a memory cycle. This causes the circuit in FIG. 17, in order to generate an S /? Cycle in the manner described above which selects the segment register and causes the content of the memory data register SDR to be transferred into the selected segment register.

The "save segment register" command is similar, but with the reverse sequence of the micro-routine, so that the circuit in FIG. 17 is first caused to generate a 5 /? Cycle while the segment register is selected and its contents are transferred to the memory data register SDR will. The micro-routine then causes a normal processor memory request which causes the contents of the SDR to be transferred to the addressed memory location in main memory.

E.6 Control for look ahead translator unit

If the block address part of the physical address is generated from bits 0-4 of the logical address during the address translation, a processor clock cycle is required for access to select and read out a segment register SR . Another processor clock cycle would be required to access (if the look-ahead circuits were not provided) to decode the read block address in order to select the interface bus to the required memory unit, i.e. to the internal memory, to the external memory or to the asynchronous memory to which the physical block address must be transferred . If a look-ahead circuit is provided, there is no need for additional time to select the required interface bus, and there is no need to decode the read block address in order to determine the required memory unit. This means that the look-ahead circuit shortens the access time during translation by one processor clock cycle. During the translation process, the D bits in positions 5 to 15 of the logical address are always available on the main memory bus from the processor memory address register SAR . No additional translation time is therefore required for the D bits; they are delivered to all three storage units at the same time.

For the look-ahead circuits, two bit positions, which are referred to as look-ahead bits, are provided in each segment register (SR) in each of the eight stacks (FIG. 9A). The division of the segment registers is shown in Fig. 6. The two look-ahead bits are generated and inserted into the segment register when the block number is inserted into the segment register by the processor memory controller; this control, soft the in Fig. SA performs operations shown in FIG. Shown 17 Vorgriffsbits indicate whether the internal memory, external memory or the Asynchronspeicher containing the block which the block number in the SR corresponds When the Vorgriffbits are set and the segment registers are loaded, the Vorgriffbits be with each memory access with translation used to set the determination and selection the required memory unit in parallel with the circuit translation of the logical input address. The block number, but not the look-ahead bits, can be read by a program using a SÄ memory instruction

The look-ahead bits are in the form shown in FIG. 9G shown Type coded The left look-ahead bit is set to 1,

if the associated block is in the internal memory. If the left bit is set to 0, the associated bit is available Block either in external storage or in asynchronous storage. The value of the right look ahead bit indicates whether the external storage or the asynchronous storage holds the block. If the right bit is equal to 0, the is Block in the asynchronous storage unit.

The look-ahead bits are only used by the circuits and are for the programmer or the System user not visible. They only serve to accelerate memory access and are not Part of the translation operation.

The circuitry for setting the look ahead bits is shown in Figure 9C. These include the decoders 9OM and 902 / t, both of which are supplied with the higher-order part of the assigned block number, which is loaded into a segment register when a Scgrncnircgästerbefehls is executed, as described in connection with FIG. 8A has been described. The selected segment register is in one of the stacks 0 to 7 (Fig. 9C). The block number is issued by the "Load segment register" command, which retrieves the program-assigned block number from the memory location in the main memory addressed by the command, after which the block number is inserted in the memory data register SDR (FIG. 4). Then the processor gives the allocated block number from the SDR to the processor data bus (FIG. 3C) ₁ which is connected to the memory data bus to the memory (FIG batches 0 to 7 are to be loaded. The segment register load path is shown in detail in FIG. 9C; the signals on the S /? input lines 00-07 are used to generate the look-ahead bits. The conduits 00-06 are connected to the input of the decoder 0 902/4, and the lines 00 to 07 are connected to the input of the decoder 901 0 A. Each of the 0 decoders outputs a 1 as a look-ahead signal if there are all zeros at its inputs, and outputs a 0 signal at the output if any of the inputs is equal to 1. If the decoder 901/4 detects all zeros in the bit positions 00 to 07, it transfers a 1 bit into the left look-ahead bit position of the addressed segment register in the stacks; but if any of the input bits 0 through 7 is a 1, then the left look-ahead bit is set to zero. The decoder 901/4 indicates whether the physical block whose address is being loaded is in internal memory or not; it depends on this whether a / SZ signal must be generated.

If decoder 902y4 detects all zeros in SÄ input bit positions 0 through 6, then will the right bit of the addressed segment register is set to 0. The reason for this is that when the left Look ahead bit indicates that the internal storage unit is not the affected storage unit and if bit 0 to 6 are all zero, then the decoder 902Λ indicates whether a 1-bit is or is not present in bit position 7 of the physical address being loaded; this finally shows whether the block in question is in the external memory or in the asynchronous memory.

So for every segment register that is loaded, the look-ahead bits are set to be the one Specify the storage unit that contains the allocated block. The S /? Load operation occurs during of a SÄ cycle on line 923 in the concentrator 922 (Fig. 9A) is displayed by the basic control, the details in F i g. 9D-2 is shown.

The stack address is input to concentrator 922 through lines 05-07 of memory address bus 901 (Fig. 9A). The segment register address is transferred from lines OO through 04 of memory address bus 901 via the PH register to segment register stacks 0-7 (FIG. 9A). These address signals arrive on lines 00 bit 07 of memory address bus 901 (see FIG. 3C) from memory address register SAR (FIG. 4) via the processor address bus. The content of the SAR comes from the general register, which was selected by the "Load segment register" command (FIG. 8A), from which general register bits 0-7 are the S /? Address bits on the lines 00 to 07 of bus 901 are. (The general register AR is selected in the level stack 431 [Fig. 4] by a level stack address that was derived from the 4S field in the "Load segment register" command.)

The concentrator 922 then outputs the stack address of the selected segment register on its following output lines: AAS-Bn 2, / 4 / 4S-bit 1 and "SR high-low selection" (line 935). Line 935 provides an input signal to the basic controller in FIG. 9B. These circuits are shown in detail in Figures 9D-2; they generate the signals for lines 932 and 933, which are connected to the segment register stacks 0 - 7 to indicate the lower-order stack address bit and according to the true and complementary form of the signal on line 07 ι of memory address bus 901. The signals on line 4 / 45-bit 1 correspond to the true and the complementary form of the signals on bus line 06; and the signal on line AAS bit 2 corresponds to the signal on bus line 05.

• When memory is accessed in compile mode, a stack register is selected using the same type of concentration operation as described in the section »Segment Register Selection«. From the segment registers selected by the concentrator

• Both look ahead bits are read out at the same time as the other 16 bits. For the look ahead bits uses a separate concentrator 931 because it works faster than the other concentrator 921, the the block address bits for the same segment register

> selects. At the output of the concentrator 931, one of three output lines is activated in each case in order to indicate the selected memory cycle, namely either ISZ, OSZ or ASZ . The / SZ signal lines 54/4 are used by the processor for the processor

'used by the memory priority selection circuit 56 to the internal memory unit 51 (Fig. IC). Since the lines 54/4 exist in any case, whether the oystein is a uu £ i aetzer nSi Oucr PtCut, * A "r * 4« ic internal memory cycle control line from the concentrator

5,931 connected to the processor for a / SZ addressing operation to cause. The lines for the external storage cycle and the asynchronous storage cycle lead to the F i g. 9E or 9F-1 to select the address in the units concerned.

F. Operand range comparison

A specially provided facility is the operand area alignment (OBA). If this condition is set in the address key register ASR , ί> 5 results in a special addressing state in which all operand calls are forced to take place in the CV2.S address area, while the address area specified by the O / MS address key, although the

Key in the OP 1S register section of the address key register ASR is not changed.

The OBA state of the system is brought about by the release command shown in FIG. 13A if its OBA Bh 13 is set to 1. When this command is executed, the set OBA-Bh causes the OßA register section in the relevant ASR to be loaded accordingly by input from the processor ROS decoder ( FIG. 4). None of the keys in the ASR are changed when the OfiA state is activated. However, the address area that is defined in the OP IS section is not accessed as long as the OS / 4 status is active in the ASR . The OßA device is implemented by the circuit shown in Fig.3D, in which an activation of the OßA line from the ASR forcibly requires that the Λ AS output emits the OP 2S key every time an instruction is executed in the processor There is an access request for either an OP1 operand or an OP2 operand.

If the OßA state is ended by executing a lock command, the OßA bit 13 of which is set to zero, the key value in the OP 1 S register section is used again and is output with every OP 1 operand request.

G. Determination of the address range
Key entry into the ASR

If the OB / 4 facility is locked, the three address keys in the address key register ASR have the following function:

Each address key loaded into the ASR defines an address area that can be accessed, the address area is a logically contiguous memory area that can be accessed by the effective logical address without the aid of any programmed management function for the distribution of the available resources. Each logical address area contains up to 64K bytes. All command calls are made in the address area defined by the ISS. All read operations that relate to a data operand 1 (as defined in the memory command) take place in the address area which is defined by the OPIS. (Due to the design, no write operations are provided for operand 1.) Similarly, all write and read operations involving a data operand 2 (as provided for when designing the instruction structure) take place in the address area defined by the OP2S.

If, for example, ISS = OP \ S = OP2S, all memory accesses are made to the same logical address area with a capacity of 64K bytes. If ISS is not the same as OP1, but if OP \ S = OP2S. The instruction calls then take place in the ISS address area, and the data access takes place in the OP2 address area. If ISS * OP \ S * OP2S, then the command is called in the / SS address area, every call of an operand 1 in the OP IS address area and every call or every saving of an operand 2 in the OP2S address area, whereby the 3 address areas are different from each other are. The flow of data for a class of instructions using three different address ranges is shown in FIG. 2A shown. The key values in the ASR can only be set if the processor is working in the monitoring program mode, ie if the commands for loading the ASW are privileged.

H. Loading the ASR in the event of an interruption

If an interrupt occurs in the processor, address keys for address areas that might be required by the programs handling the interrupt are entered into the ASR in preparation. There are a number of different types of interrupts in the system, each of which has its own special programming support, which in turn requires the loading of certain address keys. Interruptions, control panel interruptions and interruptions in the event of thermal overload. These processor interrupts are sometimes called class interrupts.

It is assumed that all interrupt routines are accommodated in the address area with the key / = O. Therefore, an O must be loaded into the / SS section when an interrupt occurs. Since the operand data which are required for handling a specific interruption can be accommodated in a different address at; I, the address closure belonging to the special interruption data! loaded into the OP IS register section. An OP ! Key is entered when a class interrupt occurs (ie, inputting an input to the forced address circuit 402 in FIG. 4) in preparation for performing a memory-to-memory transfer operation from the interrupting address area (ie, OP IS area) to the OP 2S address area with a key! = 0. When a class break occurs, e.g. B. a level status block NSB is stored in the OP2S area, which has the key = O (ie OP2S = 0), with data being retrieved from the OP IS area. The content of the ASR is also entered in the NSB with a command to save the ASR .

Other states in which all key values in ASR = O are set: System reset and initial program loader, during which the OP / 4 device, the translator and the memory protection device are all blocked.

H.l Interruption with monitoring program call (SVC interruption)

For the SVC interruption operations discussed below, it is assumed that the monitoring programs are accommodated in the address area with key = 0 and that the user program is in a different address area, ie with key Φ 0. It is also assumed that an exchange of data between the user and the monitoring program is necessary. The data must be fetched from the address area of the user into the address area of the monitoring program and must later be returned to the address area of the user.

Figure 13B shows the load operations for the ASR in the event of an SVC interrupt. It is assumed that initially in the user state each of the three user keys has the value 2 and that the OS ^ -FeId = C> is set. If in the processor of FIG. 4 a monitoring program call command (SVC command) is executed, the forced address circuit causes a sequence of ROS words to be called up and executed

whereby the processor is brought into the monitoring state. A level status block NSB is also stored, the content of OP2S is output to the content of OPiS , so that the address area which contains the data that were involved in generating the interruption can be addressed. The zero output line (ACQ) from the processor ROS decoder is activated and values are entered into the OP2S and / SS positions of the ASR via the processor data path. κι

Data is transferred from the user area to the supervisor area is transmitted, and then the release command (Fig. 13A) with a 1 in bit position 13 is transmitted carried out to the OÄ4 state 4 shown in Fig. 13B is shown to bring about. This has the effect that all memory accesses in the address area with key = 0 take place while the monitoring program is being executed in the Oß-4 state, with the possibility of access / to OP 1 address area is not lost.

If the monitoring program wants to transfer information to the OP 15 area, the processor issues a lock command which resets the content of the Ofl ^ section in the ASR ; this causes a return to the OPI address area. Then state 6 of FIG. 13B is brought about by exchanging the fields OPIS and OP 25 so that the monitoring program is given an addressing option for storage in the OPIS area. The monitoring program can then transfer the data from the monitoring program area to the user area v \ . Then the ASR is returned to user state 7 (Fig. 13B) by loading the original contents of the ASR from the level status block NSB.

Fig. 18 shows the operations performed when an SVC command is issued. These operations include saving the old content of the ASR and loading new content into the ASR according to the overview below, the section numbers of the overview and the numbers circled on the data paths in FIG. 18 corresponding to one another. The execution of the SVC-Belehls in the processor takes place in the following way:

Area by definition contains an address (ie a pointer) to a level memory block (ie NSB), which in turn is also located in the address area with key = 0.

(8) The NSB pointer in position 0010 is transferred to the memory address register SAR ( FIG. 4).

(9) at the addressed by the SAR, then for the NSB provided for storage of the contents of BAR. TEMPA, TEMPB and the general registers 0-7 are saved (NSB).

(10) The SVC number (which identifies the relevant type of SVC command) is copied from the SVC command in address area 1 into register R 1.

(11) The content of memory location 0012 is transferred to the BA R.

(12) The execution of the monitoring program routine now begins, which starts at the memory location with address 0012. This is the routine which is called by SVC number 2.

At the beginning of the SVC routine, the ASR has the following content:

0! '\ S OPZS

ISS

(1) At the beginning of the execution of the SVC command, the content of the ASR is output to the working area register (ABR) via the processor data path by activating the AG ASR signal and the EC ABR signal from the flOS-üecoder. This operation is indicated by the transfer of the ASR contents to the TEMPA register in Fig. 18; it is believed that OPIS. OP2S and ISS have been set to the value 3.

(2) Output OP25 and input OPlS.

(3) Set OP 2S = ISS = O.

(4) The content of the level status register (/ VS /? / ¹ is stored in the "'' temporary register (JI MPB ').

(5) The Ru for the monitoring status is set in the NSR ' register, the item for the summation mask is reset and the protocol is also reset. '■>'>

(6) The content of the BAR (instruction address register) is then (1) increased by two units so that the next memory location is now addressed, in which the beginning of the data or a pointer to the data is located. >"(2)

(7) When the processor detects the SVC state, (3) the content of memory location 0010 in (4) Address book retrieved with key = 0. This

OPlS ' 0 0

(Note: OPIS ' is the
\ previous content with OPlS).

In the case of other class interruptions, similar types of operations are performed in order to achieve a certain state of charge of the ASR , as shown below:

H.2 Device-related interruption

| 1) Reset protocol. Block ORA and set monitoring status.

(2) Set ISS = OP IS = OP 2S = O.

(3) Insert the address of a device data block in register 1.

(4) The interruption identification (ID). which was received by the interrupting I / O device in register 7.

The resulting content of the -4S /? Is:

O / MV () / »2.V ISS

0 0 0

11.3 Interruption in the event of a machine failure and
Bug

Reset protocol, block total mask,

Block OBA and set monitoring states.

Save the NSB in the address area with key = 0.

Set / SS = OP2S = 0.

LKSA in the oil ' ISspeichcm.

Save the content of the SAR in register 7 (except for the protocol bit).

The following content of the ASR results:

OP \ S

OPlS

ISS

LKSA 0 0

(Note: LKSA is the
last in register 408 Fig. 4
stored keys at
Occurrence of the interruption).

H.4 Interruption from the control panel /
Interruption in the event of thermal overload

(1) Reset protocol, block total mask, block OBA and set monitoring states.

(2) Save NSB using the address key O.

Set (3) / 5S = OP IS = OP 2S = O.

The ASR is in the following state:

OPlS

ons

ISS

H.5 Log recording interruption

(1) Reset protocol, block total mask, block OBA and set monitoring states. Save NSB in the address area with key = 0.

(2) / SS transferred to OP IS.

(3) Set OP 2S = / SS = O.

This results in the following content of the ASR:

OPlS

ISS

ISS ' 0 0

(Note: ISS ' corresponds to
the ISS present at the time of the interruption ).

2. Circuits for memory protection without translator

The memory protection circuits shown in FIG for translation-free addressing (ÜFA memory protection circuits) are used if the in The address shift translator shown in Figures 9A and 9B is either not enabled or is not in the system installed. The invention enables backward compatibility between a system with translator and address key memory protection on the one hand and one On the other hand, system without translator with memory protection. That means: programs and data in one System that works with the ÜFA memory protection device can be used without changing in a facility that has an address shift translator. This option to switch between two types of memory protection circuitry is very important for system users who are familiar with a relative want to start small storage system that is inexpensive and move their storage for a larger one later Want to expand the system.

When the address shift translator is enabled and so is the ÜFA memory protection circuit is enabled, the address shift translator is disabled. The condition of the ÜFA storage protection devices is controlled by the enable / disable command, "" shown in Figure 13A.

The ÜFA spoke protection circuits enable the prevention of unwanted access to a Main memory location, be it by a processor command or an I / O command that does not translate one

in address used with the ÜFA storage facilities the main memory is divided into blocks of 2048 bytes each. For each block of main memory For example, a storage key register is provided in register stack 501 (Fig. 11). Every register

π is assigned to a certain block in the internal memory, which is selected by the five most significant bits in a 16-bit physical address, where this is the address appearing in the program, which is generated directly by a program that

2i'- runs in the system. When using the ÜFA memory protection device, the addresses appearing in the program are the physical addresses; but if the translator is released, the address appearing in the program is part of the logical input

2 ~ < address. Each register has at least three bit positions for an associated storage key and a read-only bit R; it can also have an additional validity bit V (not shown). For the three-bit storage keys, the bit positions are 0, 1 and 2

in provided which by one of the usual commands can be loaded to load storage keys (such as in the IBM system 360).

A comparison part belonging to the ÜFA memory protection operation roughly corresponds to the mode of operation of

r> Storage key protectors that are known in Systems such as B. IBM systems / 360 or IBM systems / 370 occurrence. The remaining parts of the ÜFA storage protection facilities that work together but belong to the new solution, which in this one

4 »Description is shown, as well as their combination with the special / MS selection circuits 333 (Fig. 3D).

The most significant bits 0-4 of the 16-bit physical address are used for the comparison operation

• r> used to select the register in the stack that which is assigned to the internal storage block.

The storage key in the selected register is obtained. The active address key AAS is then used with the storage key selected from the stack

vi in comparison circuit 502 (Fig. 11). If the comparator indicates that the two keys are the same, access is permitted, provided that that the ÜFA memory protection device is enabled and that the access is either a

> ") Is a retrieval operation or a write operation, where the read-only bit is set to 0. The ÜFA storage protection device thus enables one selective protection depending on the type of access; with it, with addressing without translation, a separate

Wi memory protection for addresses in the areas OPiS, OP2S and / SS can be achieved.

Another special feature of the ÜFA storage protection devices is the access control for shared memory areas, which

fei is indicated by a special key value, and i Access through I / O sub-channels. Every user has access to the special ones identified by keys Storage areas that are available for the

Users are defined in the ASR in the processor; All users can use the key = 7 in each register section of the ASR to define a memory area shared by the users. The circuit 505 controls the accesses to the shared memory areas.

A special access control for I / O operations when using the ÜFA memory protection devices is given by the circuits 504 and 505 , which enable an I / O cycle steal Zugnffs- κι request both to the memory area for the relevant User is defined in his ASR , as well as can be made to the shared memory area with key = 7, whereby no I / O cycle steal access is prevented by the r, read-only bit in the memory key register used. That is, I / O write access is always permitted regardless of the value of the read-only bit in the selected register in stack 501.

If the processor is in the supervisory program state, i. If bit 8 is set in the NSR (Fig. 4) , the memory key protection circuits are bypassed and all access to any block in the main memory is permitted.

In summary, it can be said that the address area selection control, which is given by the address key register ASR , is always used, both when the ÜFA memory protection device is enabled and when an additionally provided translator device is used. The active address key is ju AAS either a CS key or a key that was selected from the ASR when executing a processor command, depending on which type of information is called up by the access (type of operand or command). r>

When the ÜFA memory protection device is enabled, at least one of the following conditions must be met must be fulfilled so that an attempted memory access is permitted:

41)

(1) The system is in the monitoring program state.

(2) The memory key of the addressed block is 7. When an attempt is made to write to memory the read-only bit must be = 0. -n

(3) The storage key of the addressed block must be the active address key AASg \ e \ ch . The read-only bit must be 0 when a memory write operation is attempted.

ίο

If none of the above conditions (1), (2) or (3) is met, the inverter 507 (Fig. 11) outputs a memory access inhibit signal, which causes a program error interrupt (PCK) which is the corresponding bit in the processor -Zu vi status word register fPSIV register) sets.

In the monitoring program status, there is free access to all parts of the main memory. Access to a memory area that has a memory protection key 7 is permitted, regardless of the value of the active address key AAS or the values in the address key register ASR, provided that the system is not in the monitoring program state, provided that the Value of the read-only bit for the addressed block given μ condition is not violated.

This means that within a single addressable address defined by an address key Storage area some blocks can be kept read-only while other blocks write access is possible; this depends on the binary value of the read-only bit of the relevant blocks in the addressable memory area. The read-only bit can be set by the monitoring program loading the stack registers

During the initial program loading (IPL) , both the ÜFA memory protection devices and the translator devices are both blocked, so that writing can be carried out in any location in the main memory during the initial loading. After the initial program loading (IPL) has been carried out successfully, each of the two memory protection devices can be released and if address keys that are set to 0 occur in the ASR, the system switches to the monitoring program status.

The ÜFA memory protection device and the translator device share the establishment of the active address key AAS, but they also have a number of features that are different, such as. B .:

(1) In the monitoring program status, access to the ÜFA memory protection device is granted all parts of the main memory are permitted, regardless of the memory key. In one System with translator can only access the memory area in the monitoring program state which is defined by the active address key / 4 / 4S.

(2) The total storage capacity in one
ÜFA memory protection system is defined by an address key, is a maximum of 64K bytes. The entire static memory, which can be defined by the address key in a translation system, can have a capacity of up to 512K bytes at any time.

(3) In a translator system, the address area defined by the address key begins at logical address 0. In a ÜFA memory protection system, it begins with the address key Defined address area with different possible limits of blocks of 2K bytes each Capacity, but the address key always provides access control depending on the type.

(4) The commands that are used to execute the
Loading memory key registers in the processor or saving from them are different from the commands used to load or save segment registers in a system with a translator.

(5) A memory protection failure operation cannot be performed for an I / O device in a system where a translator is enabled There may be an I / O device in a system with a ÜFA memory protection device but memory protection error operations can occur accept for access to an address which is not assigned to that by a CS key or belongs to the area defined by a key = 7.

(6) Because of the flexibility for address translations in a system with a translator If the ÜFA storage protection devices are available, certain conversions from logical to physical address ranges difficult to implement, e.g. B. Use of a common area for only two address keys.

3. Alternative memory protection mode (ASB)
for systems with address translation

F i g. Figure 14 shows the control circuitry for an alternate memory protection mode (ASB) that may be used in a data processing system. This mode of operation is an alternative to the translation mode described above, in which a multiply subdivided address key register .457C (FIG. 1 D) is used. In this alternative operating mode, there is no addressability by the processor which is dependent on the type of memory access and which can be achieved with the arrangement according to FIG. ID; however, it enables separate addressing areas for I / O memory access. The alternative operating mode enables the processor to have different addressability, depending on an active address group, for its various programs and data with different user address keys; however, it also allows an interactive relationship between the user and the monitoring program, if necessary, without the content of a user key register (BSR) 460 having to be changed.

In the arrangement according to FIG. 14, only a single address key can be loaded into the ßS /? Register 460 of the processor, so that all memory accesses for executing a user program and for corresponding data access must take place within a single address area which is defined by the user key in the BSR 460 is defined; this user address key cannot have the value zero, since this value is reserved for the memory area in which the system monitoring programs and system data are located. I / O accesses are controlled by the CS key, which can be loaded into the CS key register 465 from a subchannel.

The / 4Sß mode is controlled for a processor by a bis position A in the level status register (NSR) 470. When the monitoring state is switched on. bit position S contains a one; when the 4Sß mode is on, bit position A contains a one.

If both bit positions S and A contain a one, a first type of processor operation is provided in which the monitoring program (which is contained in the address area with key = 0) can work with the address area of the current user address key (which is contained in the BSR 460). This means that the monitoring program works from the area with key = 0 and uses operands from the address area identified by the user key. The monitoring program cannot access other address areas in the main memory that belong to other address keys. This mode of operation of the monitoring program with limited addressability enables the programs for break handling. access to a presently suspended user program and its data without there is a risk that the monitoring program in a separate fault the integrity not involved areas of the main memory disturbs Incidentally, a Benutzerprograrnm never access when executed to the storage area of the monitoring program because _E very user agent only has access to the memory area defined by its own user address key.

A second type of processor operation occurs.

if the monitoring program bit 5 is one and ASB-Bh A is equal to zero. The monitoring program from the area with key =! work out without disturbing the running user connections in the BSR 460. In this case, commands and operands are only accessed in the area with key = 0, and the monitoring program must not access any user area. That is, in this state the monitoring program has no access to either the user area identified by the current content of the BSR 460 or any other area defined by any other key. This type of system operation avoids the need to enter each key = 0 into the BSR 460.

A third type of processor operation is provided when the monitor program bit S equals NuI, the value of the ASB-Bhs A being irrelevant. In this case, all command calls and operand accesses only take place in the area defined by the user keys; Access to the main memory area with the key = 0 is then not permitted.

The / 455 operating mode is controlled in the processor by the circuit arrangement shown in FIG. 14. AND gate 462 is enabled when both S-bit and A-Bh are set in NSR 47 ( Thereupon, a signal via AND element 462, OR element 466 and inverter 467 ai AND element 461 is given by the processor (FIG. 4) for each command request request, in order to block this during the command request process Member 461 is blocked, there is a zero signal, which represents the key = 0, to the / 14S-BuS. A command call is therefore only permitted in the memory area of the monitoring program with the key = 0.

If there is no command call request (as <in the times between the command call requests), the AND gate 462 is not enabled, so that the inverter 467 sends an active signal to the AND gate 46: to retrieve the user address key from the BSf 460 to the / MS bus so that a command called up from the monitoring program can access operands that are in the area that belongs to the key in the BSR 460.

If the ASB-Bh A is reset in the NSR (equal zero) while the monitoring program bit.! is set (equal to one), the AND gate 4 # remains constantly enabled and blocks the AND gate 461 via the inverter 46i, so that it continuously outputs the key = 0 to the AAS bus. From this it results

tion where the monitoring program for aiii Command calls and operand access to the area of the key = 0 is restricted, regardless of Value of the user key in the SS /? 460

If the S bit in the NSR 470 is reset (equal to zero), AND gates 462 and 464 remain locked, so that inverter 467 constantly supplies an enable signal to AND element 461, which consequently forwards the user address key to the AAS bus without interruption The result is the third type of processor operation described above, in which all memory accesses, both for the processor and also for I / _{O, take place in the main 1} .. memory area, the addressing of which is provided by the user key in the BSR 461. The monitoring program can only work when bit S is set (equal to one)

llicr / u 2 <> \ V:; \\

Claims (8)

Patent claims: 1. Memory protection arrangement for the main memory of a data processing system, which by Address keys that are dependent on the type of memory access and a block address from a Select block address register stack, preferably addressed without virtual address translation is indicated by - an access key register (31-35, Fig. IA-1) with sections for several Access key; - a selection means (20) for selecting and ι> passing each of an access key from the access key register as an active access key on the basis of selection control signals; - Detector devices (405; 22 ... 25) in the processor or processors of the data processing system to determine different memory access requirements according to the type of access or information, and control devices (56; FIG. 3C) for releasing one access arrangement each tion and for the delivery of a corresponding selection control signal to the selection devices; - A group of storage key registers (501, FIG. 11), each of which is assigned to a storage block in the main memory and has a field for receiving a storage key, as well as output devices for addressing one of the storage key registers based on the block address from higher-order r> Bits of an address present in the memory address register of the processor (SAR); as - A comparison device (502, Fig. 11), which with the selection device and the output devices for transmission per m an access key and a storage key is connected, and which is a first Emits an indicator signal that indicates whether the access key and the storage key matched each other, and that via a 1> first gate circuit (508) to output circuits (506, 507) for enabling or disabling of the memory access is passed on (Fig. 11). 2. Arrangement according to claim 1, characterized in '", - that in each memory key register (0 ... 31, 501, Fig. 11) a bit position (R) is also provided for a read-only control bit, as well as r> a coincidence circuit (503) which is connected to an output line of the /? Bit position of the group of memory key registers is connected in order to emit a write permission control signal at its output only when both lines indicate a predetermined bit value. 3. Arrangement according to claim 1, characterized in that - A second gate circuit (505) is provided, which upon receipt of a specific Storage key is released at its input to issue a second display signal at their exit; - a connection is provided between the output lines of the memory key register (501) for read memory keys and inputs of the second gate circuit; - the output of the second gate circuit with the Output circuits (506, 507) is connected, so that these in the presence of the specific Address key in the currently addressed memory key register a signal for release of memory access regardless of the value of an access key, i.e. independent of the respective program. 4. Arrangement according to claim 3, with switching devices (Fig. 10), which a switch from address translation operation to non-translation operation and vice versa, with input lines for signals, which indicate whether a translator is installed, whether the translator is enabled, and whether the memory protection is enabled by means of the memory key, characterized in that that the switching devices have an output for a release signal for translation-free Have memory protection, each with an additional control input of the first gate circuit (508) and the second gate circuit (505) is connected to this at least when ready for operation a built-in translator. 5. Arrangement according to one of the preceding claims, characterized in that additional Logic circuits and control lines as well as an input for a cycle steal control signal are provided to respond to a cycle steal request of an I / O unit depends on the storage key, but on the respective one State of the read-only bit in the affected memory key register independent memory access enable or to generate blocking signal at the output circuits (505, 507). 6. Arrangement according to claim 1, characterized in that switching devices (461, 462,463,464,466, Fig. 14) are provided to the Key selectors (469) optionally either one in a key register (460) of the Processor contained user key or a circuit-related, the monitoring program assigned special key. 7. Arrangement according to claim 6, characterized in that a status register (470) is provided with at least two bit positions for access control bits (S, A) and that the switching devices (461,466) have three control inputs, two of which with the outputs of the status register Bit positions and one is connected to a command fetch request line, depending on the binary value of the access control bits being fed to the key selection devices: a) alternately when the command call request signal is present the special key and in the absence of the command request signal the user key; or b) only the special key; or c) only the user key. 8. Arrangement according to claim 7, characterized in that when storing the loading user key in the access key register (32—35, UKR) the access control bits allow the following memory accesses of the monitoring program depending on the value: - to the memory area of the monitoring program to the area of the user whose The key is currently stored in the access key register (for operand access); - only to the memory area of the monitoring m programs; - only to the user's memory area.