DE2710502A1 - ARRANGEMENT FOR THE COAERENT MANAGEMENT OF A STORAGE HIERARCHY - Google Patents

Description

Dipl.-Ing. Dipl-Chem. Dipl.-Ing. * · ' ^Ww **

E. Prince - Dr. G. Hauser - G. Leiser

Ernsberger Strasse 19

8 Munich 60

⁵ 'March 10, 1977

COMPAGNIE INTERNATIONAL POUR L INFORMATIQUE CII - HONEYWELL BULL
94, avenue Gambetta
Paris (20) / France

Our sign; C 3129

Arrangement for the coherent management of a storage hierarchy

The invention relates to a system for the coherent management of the exchange of information between two contiguous Levels of a storage hierarchy, one level of which is faster than the other, and in particular between a data store of the slower level and several data stores of the faster level, which can be used individually by separate processors. To simplify the terminology, the data store is intended to be of the less fast level are called "main memory", and each of the data memories of the faster level shall be called "buffer storage".

Lei / Ma

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. ο.

The exchange of information between the main memory and the buffer memories, of course, is bilateral occurs relates to information or data, part of which can be modified. If a same modifiable Information originating from main memory may have been entered into multiple buffers it can happen that these "copies" have been modified independently of one another. There is therefore a certain Risk of inconsistency if no special measures are taken. However, there are three Differentiate between categories of information:

- Information concerning the programs and not modifiable are so that they cannot cause incoherence;

- Modifiable information, but only to a single task of the multitude of the complete Attachment to executable tasks so that they cannot cause inconsistencies as long as the task is in the same processor remains active;

- Information that is generally usable and can therefore be used by various tasks; such information can cause inconsistency at any time.

The aforementioned first modifiable information, that only belong to one task should be "local" information and the second modifiable information should be called "global" information. However, these categories of information are on the less

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fast level indistinguishable. You can be at the faster level in a more or less precise measures can be distinguished, because an instruction processor can use the instructions it has carried out recognize what information is global in order to access and use that information; because he can recognize the program information, he can thus, if he can distinguish the global information, also recognize the local information, at least when it is called up and when it is used.

There are already different systems for the coherent management of the exchange of information between contiguous Known storage levels of the type specified above, in which to varying degrees and in various combinations of systematic markings of information transmissions and immediate or Postponed systematic re-entry of the modified information with likewise systematic Look for the presence of data in the buffers where it was in the original or in modified form can be present. However, these systems are essentially concerned in order to ensure the coherence in data processing systems with strongly competing multiple programs and to maintain the highest possible overall efficiency for such data processing systems, i.e. the best possible utilization of the buffer memory, at least when reading, and the least possible delay when performing the tasks at this level. Such systems are very complex, and in in certain cases they result in a more complicated management.

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In contrast, the object of the invention is to create an arrangement for the coherent management of a memory hierarchy of the specified type, which is particularly useful for systems with low program competition and / or relatively low individual capacity of the buffer storage is economical and effective, as well even in systems in which a certain loss of time in accessing the data of the buffer memory as well when writing as well as when reading is permitted.

In the case of the arrangement according to the invention, use is made of certain measures and terms from customary practice made by which also the organization of the management of the information movements in the stores through autonomous control circuits of this memory is retained, this line in most cases also makes use of repertoires of state words which represent the states of the addressed in the memories Display memory locations and be controlled by the routing circuits.

For example, when a data store with multiple processors works together, they perform different tasks perform, as is the case with the aforementioned main memory, can be known to one these processors, if necessary, "lock" part of this memory so that it can use it this part of the memory during the time required to run its own program, or at least in a critical period of this time, reserved for yourself. If the logic of the plant is correct is designed, no other processor can access the information during the duration of this interlock of the locked memory part.

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It is also known that in the algorithms of the programs the tasks in critical phases, to which the Calling up information of a global nature, generally making use of a type of command, which is called "Test & Set" in Anglo-Saxon usage and should be called "TS command" here · This type of command causes the reading and modification of information in a manner that is not divisible per se. In a properly set up program, everyone has access to read or write global information such a TS command precedes in the main memory; if the addressed memory section is not locked, brings this command displays the interlock in the form of a character (• »byte") that defines the memory section to which In this way the processor reserves access to the exclusion of all other processors want.

It is also known that a "page" of information can be blocked in a high-speed store by that a suitable reference symbol is added to it, or more simply by the fact that it is blocked by the change the value of a bit of the status word corresponding to this "page" in the corresponding register of the status word repertoire is changed, which is usually assigned to the memory management circuits. In the following Description "Page" means any group of information that is the subject of such a status word even if the memory is not divided into pages (although the division into pages is the most common The form of representation of such memory is).

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40 '

Finally, it is also known that a processor that has finished performing a task will do so Confirmed facts and then can generate a confirmation signal. Such a signal is usually in data processing systems for performing various operations, in particular for transmission used by information.

According to the invention, the coherence is ensured that on the one hand each execution of a TS command by a processor has the blocking of at least all global information contained in this Processor allocated buffer memory are available, and that on the other hand, in addition to this, each confirmation the execution of a task the blocking of at least all local and existing in this memory global information.

If, when loading the buffer memory, the processor reads the various categories of information (commands, local modifiable information, global modifiable information) has determined and marked these blocks are preferably carried out selectively. If, on the other hand, there is no marking during loading is, these locks affect the entirety of the information, which can be acceptable if the capacity of the buffer memory is not so large.

In other respects, this method is directly applicable when any modification of information in the affected buffer storage of the faster level immediately in the section of the affected by the lock

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• 4η χ

Main memory is copied. That way, this section will be informed when the latch is on later canceled.

However, if so desired, this section of main memory can be corrected until it is canceled the locking and / or each confirmation of the execution of a task or each change of the To reset context in the processor's working registers, it is necessary to use a trick which has already been used to maintain consistency in various previous practices and consists in each piece of information that has been modified in the buffer memory having a flag bit which indicates the modified state of the information. This bit is preferably used in the status word of the repertoire assigned to the routing circuits of the buffer memory is introduced. Consequently the "keep-open" operation affects only the really modified data, from what there is a double advantage: on the one hand, a reduction in the number of rewriting cycles in the main memory, and on the other hand a protection against the risk of incoherence, because the Information that has not been modified by the processor in question can already be obtained from a modified by another processor that had taken it over before locking.

An embodiment of the invention is based on the Description of the drawing, the only figure of which is a section of a schematic block diagram

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shows a memory arrangement designed according to the invention.

The drawing shows an organization for the coherent management of information transfers between two abutting levels (i + 1) and (i) of a memory hierarchy in the event that level (i) is the faster level in this hierarchy. The example given is that the less fast level (i + 1) also provides information with an even slower level (i + 2) can exchange, which is not shown, since it is not important for the invention.

The level (i + 1) is only represented by a single memory unit Bj, here called the "main memory" shall be. It should be noted that several storage units can be present at level (i + 1), who can exchange their information with level (i + 2). Therefore, as part of an interface between the levels (i + 1) and (i + 2) three buses are shown, namely one address bus AB and one Data collecting line DB, to which a collecting line TSL is added for easier definition, which is used in the Execution of the TS command (Test & Set) is used, which has the effects already explained at the beginning. Each bus can be used in both directions of transmission.

In the present case, level (i) contains several storage units, which are called "buffers" here, since Each of them is used by an instruction processor. At the interface between levels (i + 1) and (i)

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there are again the three same collecting lines AD, BD and TSL.

The schematic circuit diagram shows in level (i) only a single buffer memory Bk, which is used by an instruction processor 01k is used and is passed through routing circuits CGBk to which a repertoire RPk of status words assigned. The address register of the buffer memory Bk is with RA and its read-write register shown at REL. The memory Bk is divided into pages P1 to Pm. Each page contains η information IF1 to IFn. The repertoire, the address register of which is shown at AD and its read / write register at EL, In its simplest form, it contains the same number of registers R1 to Rm as there are pages in memory Bk. Each status word register can be divided into as many separate locations as information, if desired are present in every page. Each status word contains an address ADR, which the training a correspondence between at least the content of the page P to which the status word relates, and its spatial address in the main memory BJ enables as well as status bits or status code groups defined later for the practical application of the invention will. In most cases, the ADR address also enables a correspondence to be established between the ones mentioned spatial address and a program data address AP, which is used in processor 01k, except when it the address AP is provided in the logic of the control circuits or in any other suitable place, for example to convert an interface into the address ADR.

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The organization of the control circuits CGBk can be summarized for the present explanation that it is said to consist of a micromachine which the four indicated in the scheme performs logical functions, namely:

L0G.EX. (i + 1): the management of the exchange of information with the adjoining slower level;

L0G.Bk: the control logic for the read-write operations in memory Bk;

L0G.RPk: the guiding logic for the repertoire;

L0G.EX.0Ik: the control logic for the exchange of information with the command processor 01k.

The "main memory" Bj is carried out in a similar way Control circuits, namely:

L0G.EX. (i): the control logic for the exchange of information with level (i);

L0G.EX. (i + 2): the control logic for the exchange of information with the level (i + 2), if this is available;

L0G.BJ: the guiding logic for the actual

Memory, which the write and read operations via the write-read register REL and controls the address register RA of the memory Bj;

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L0G.RPJ: the control logic for a status word repertoire RPj.

Ordinarily, the memory Bj does not need to be divided into pages, but it is such an organization often advantageous for information transfers in a coherent memory hierarchy. The scheme shows therefore only an indication that the memory Bj contains "sections" S1 to Sx (at most) as required can, the repertoire RPj then having a number of corresponding to this maximum subdivision of the memory Bj Contains registers R1 to Rx. If necessary, an address AS is then placed in a register of the repertoire RPj of the section generated in the memory Bj, and, if necessary, a buffer memory address ABi, which it enables the routing circuits to recognize where the section information is located in level (i); further status bits ET are entered into the register of the repertoire RPj, which are not explained in more detail here, since they are of no importance to the invention, and an index LK, which is brought into the state 1, with it Section S defined by the address AS is locked if the processor with the address ABi has a TS command executed. The lock is canceled and the index LK is reset to zero by an RSr command (RESET), which is issued by the command processor when such a command is in itself Program is present, and in the other case by a command for the rewriting of the for the interlock taken code group, as determined by the processor 01. This code group can be used at the point LK have been enrolled.

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When the processor 01k orders data to be entered into the buffer memory Bk, its logic unit L0G.K can assign references to the address AP, which it directs to the routing circuits CGBk via connection a, indicating the type of information in question in its register Define RAK i

P β program;
L - local;
G β global.

These notes are examined by the logic L0G.RPk, which then creates a corresponding code group in the relevant R register of the RPk repertoire reproduced. In the scheme are both in the register RAK as in each Status word register R of the repertoire three separate cells for the notes P, L and G are given, however it is obvious that a code group with two bits is sufficient for the distinction, for example:

P-OO.
L - 1 0
0-11.

The first bit indicates the property of whether the information cannot be modified (0) or modified (1) and the second bit indicates the property whether the modifiable information is local. (0) or global (1) is.

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If the processor does not distinguish the information of this type, these indices are of course missing in the state words of the repertoire.

In every memory in a hierarchy it must be possible to store an item of information, a section or a To block or invalidate "page". In the case of the invention is only the blocking of information to be considered in the buffers. For this reason it is in the registers of the repertoire RPk indicates a cell labeled V, the state of which is determined by the routing logic. For example, if the bit V has the value zero, the information is enabled or valid, and if the bit has the value 1, the information is blocked or invalid. In this example, the blocking is in each case marked for one page, but could also be for each Information IF be defined, in which case there would be as many cells V with addresses from 1 to η as Information IF is present per page.

The RPk registers also indicate the possibility of a cell beginning with M ("modified") is designated. This cell can indicate whether the information of the page has been modified (bit M at the value 1) or has not been modified (bit M at the value 0). For the evaluation of this index is it is necessary that there are as many cells M in each register R as there are information IF with the There are addresses from 1 to η per page. Such an index is then used in the event of a deferred re-entry used so that only the

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Information is transmitted back which has actually been modified in the memory Bk. He's against it superfluous in the method more familiar for practicing the invention, in which each modified information is re-entered into the memory Bk at the moment of modification.

In the processor 01k is in addition to the logic L0G.K and the associated address register RAK a main memory (MT) shown, which in conventional V / eise from a a certain number of registers is formed, which store the contexts of tasks on a case-by-case basis, which are taken from the buffer memory Bk, i.e. the information required to continue a task must be held. Between the instruction processor 01k and the control circuits CGBk are the the following connections:

a two-way connection d for the context transfers from the buffer memory Bk to the main memory (MT) and vice versa;

a connection a for the delivery of the address AP, which, as mentioned, possibly from the indexes PLG is accompanied by the code given above;

- Control lines k, which, apart from the general commands C, which are not explained in detail, as they are used for the Invention are insignificant, effect the following controls:

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a lock control v;

a possible control m for the index M;

a controller ts for the execution of the previously defined TS command.

The activation of the control line ts in turn triggers the activation of the connection TSL to the control circuits of the memory Bj so that it is sent to the address defined by AP, which is then output from the RAK register is read and then the addressed section is locked in the memory Bj, if this is not already was locked. At the same time, the logic L0G.K then triggers the connection ν for calling the blocking of the data present in the buffer memory Bk, the code of which is PLG Has value "11" if this index is present in the status words of the repertoire. The selection is made by

a systematic query of the registers of the repertoire RFk with decoding of the code PLG by the

Decoder DEC at each step of this query, which results in the setting of the index V to the value "1" results in those status words whose code PLG has the value "11". This organization is not in theirs Details shown, but can obviously consist of a microprogram in the logic L0G.K runs and the addresses of the pages one after the other in the buffer memory Bk can run, or addresses that by associative addressing in the register AD des Repertoires RPk the successive calling of the contents of the register R in the read / write register EL result to think with which the decoder DEC is connected

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is, while maintaining the activated state of the connection ν the input of a bit "1" in place V every time the output of the decoder DEC assures the presence of the code "11" in the register.

If the code PLG is not provided in the system, cell V is forced to state 1 in all registers during this interrogation.

In the case of a deferred re-entry, the re-entry must follow the previously described locking process all information marked with the code "11" in the memory Bj precede if the index PLG is used in the system, or it must at the same time with this re-entry. This re-entry is reduced to that of the information that also have an index M of the value 1 if this index is also used; then it is sufficient the output of the decoder DEC and the output of the cell M of the information in the course of the previous to link the query mentioned in conjunction (logical AND operation). If the code PLG is not used, but the index M is present, only this index causes the rewriting in the Speicher.Bj during the query of the RPk repertoire before or at the same time as the blocking.

It is obvious that after each TS command, each Calling up the program, which can then be issued by processor 01k and relates to blocked information, then the transmission of the addressed information

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and information entered again into the memory Bj caused in the buffer memory Bk. If this information has been modified beforehand, the receives Buffer memory Bk and thus the processor the last version of this information, which is in the complete System is in place. Each new writing in the memory Bk then suppresses the blocking, as usual in the register of the repertoire RPk corresponding to the address of the memory Bk at which this new one Information is inscribed.

Every change of the task that is realized either by an execution confirmation (activation of the connection acq from the logic L0G.K to the routing circuits CGBk) or by a change of the context in the main memory (HT) if the condition acq is not sent to the routing circuits CGBk causes the excitation of the compound v. The same procedure of querying the repertoire as before is repeated, but with a modification of the output signal of the decoder DEC (or the simultaneous excitation of two outputs of the decoder DEC): it is sufficient that in the code PLG, if it is present is, the first bit has the value "1 ^Μ , regardless of whether the second bit has the value" 0 "or the value» 1 ^W.

The above-mentioned microprogram for the locks executed by the logic L0G.K can be replaced in the logic L0G.RPk of the control circuits CGBk by an automaton which runs the successive addresses of the registers of the repertoire RPk as soon as the connection ν (i.e. the Request for blocking) has been activated by the logic L0G.K.

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When a new task is resumed by the processor or when a program is executed with a new context, as in the previous case, any blocked information is inevitably removed from the
Memory Bj recalled.

Such a simple system thus ensures the coherence sought without the need for a noticeable additional Circuit effort is required.

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Claims (8)

O * P »- lng. Dipl.-Chem. Dipl-Ing. E. Prince - Dr. G. Hauser - G. Leiser Ernsbergerstrasse 19 8 Munich 60 TO. March 1977 COMPAGNIE INTERNATIONAL POUR L'INFORMATIQUE CII - HONEYWELL BULL
94, avenue Gambetta
Paris (20) / France Our sign; C 3129 Claims Arrangement for the coherent management of a storage hierarchy with two contiguous levels, of which the less fast level contains a memory that exchanges data with several memories of the faster level, each of which is managed in an autonomous manner by a lead organization and each serves as a buffer for an instruction processor, which before each access to a modifiable, generally accessible information in the memory executes a TS command to one in the command to lock addressed section of memory of the less fast level, and that at each Confirmation of the execution of a task and / or each change of the task context Output characterizing the state activated, in addition to the modifiable and general in the system Lei / Ma 709838/0773 ORIGINAL INSPECTED accessible, (global) information, non-modifiable program information and local There is modifiable information assigned to the tasks and further each Faster level memory management organization a repertoire of content state words of predetermined storage locations and further wherein each master organization of a storage includes facilities for the selective blocking of data in the memory, characterized by devices, which are activated by each execution of a TS command by a processor to be used in the of this memory of the faster level used, at least those in this memory To block global information, and by entities that are issued with each execution confirmation and / or at each change of the task context are activated to at least the lock in the memory the local and / or global modifiable data. 2) Arrangement according to claim 1, characterized in that the devices enable the activation of a sequential Querying the status words in the repertoire and switching the release indices of the relevant ones Bring information to the "locked" state. 3) Arrangement according to claim 2, characterized in that the status words contain no marking, which indicates whether the information to which it relates is modifiable or not, and that the lock is set in each status word. 709838/0773 4) Arrangement according to claim 2, characterized in that the processor has facilities which For each piece of information, mark whether it is a non-modifiable piece of information, a local one modifiable information or a global modifiable information acts that the lead organization of the memory via means for writing the markings in the words of the Repertoires and that decoding facilities for the markings in the course of the Query the selectivity in the status words effect the set block. 5) Arrangement according to claim 2, characterized in that the query by the execution of an address change microprogram is controlled in the processor. 6) Arrangement according to claim 2, characterized in that the query by a local machine the control organization is controlled by the request for blocking coming from the processor is triggered. 7) Arrangement according to claim 2, characterized in that in the course of the query when the processor not the immediate re-entry of the information he has modified into the memory of the less fast levels step by step, facilities this re-entry before or at the same time effect with the blocking. 709838/0773 8) Arrangement according to claim 7 »characterized in that devices are provided which one the Modification of the information indicating marking at least in the relevant status word of the Bring in repertoires when a modification of the information by the processor occurs. 709838/0773