DE2709380C2 - Circuit arrangements for deriving a clock signal in multi-phase networks - Google Patents

Description

20th

The invention relates to circuit arrangements for deriving a clock signal in multi-phase networks.

For the time bases of maximum counters, but also for other purposes in measuring devices in industrial electronics in general, it is advisable to use the mains frequency as a reference. This occurs with three-phase networks The problem is that if one or more phases fail, such a device will not function should be affected.

Circuit arrangements for deriving a signal are known. For example, the US PS 30 02 113 an arrangement that ν. .ι a three-phase network Picking up impulses and feeding them to a consumer. In doing so, an impulse is given to you for each phase Relay contacts controlled pulse width network supplied, which consists of three successively arriving Pulses generates a pulse of greater width.

Another arrangement according to DE-OS 20 38 123 uses a logic circuit for binary information processing, each with a memory and a gate per input one the number of inputs forms an excessive number of input signals into one output signal.

These known arrangements have a relatively high control effort due to additional external ones Control signals.

The invention is based on the object of creating a circuit arrangement which, with simple Averaging derives a continuous 50 Hz reference frequency from the power grid, regardless of whether a

or multiple phases are present.

This object is achieved by the invention as set out in the characterizing features of the patent claims is set out.

The invention is explained in more detail below with reference to the drawing, which consists of two figures. It shows the

F i g. 1 the circuit arrangement for generating a reference frequency and the

Fi g, 2 shows the corresponding arrangement within a measuring device that has a computer

In both figures, the same components or connection points have the same designations.

The method for deriving clock signals is based on the fact that signals are first derived from all three phases, with measures generally being taken to suppress interference. The phase 5 signal is then shifted by 120 ° and that of phase T by 240 °. There are now three of the same size due to suitable dimensioning. Signals are available that coincide in time. These three signals are fed to an OR gate. At the output A (FIG. 1) of this gate, a 50 Hz signal appears in any case as long as at least one of the three input signals is still present in sufficient size. Small deviations in the phase shifts from their setpoints are irrelevant for the present purpose. The ODF.R gate can be implemented in a variety of ways and will expediently take over the conversion of the sinusoidal input signals into a 50 Hz square wave signal at the same time.

The permissible tolerances for the phase shifter result from the requirement that no additional Zero crossings are allowed to occur. The tolerance requirements can be reduced if the three phase signals must be reshaped into rectangles before the OR link. For this purpose, between points 1-1, 2-2 and 3-3 square pulse generator switched. In the event of non-coverage over time, this changes only the duty cycle of the output signal what for that Use as a clock signal is irrelevant. It is also required that at any time in every period all input signals of the OR gate reach the value zero once.

If a computer C (Fig. 2) is used in a maximum counter or a similar measuring device, it is advisable to use a diode OR gate D 1, D 2, D3, RD (F i g. 2) to one of the computer inputs; the computer C can then scan this input regularly, the waveform of the signal practically no longer playing a role.

1 sheet of drawings

Claims (2)

Patent claims: 1. Circuit arrangement for deriving a clock signal in multi-phase networks, especially three-phase networks, characterized in that a signal is derived in a known manner from each phase (R, S, T) and all signals by suitable switching means, preferably RC phase shifter, which at the same time Eliminate interferences, bring them approximately in time to coincide, convert them into square-wave signals and feed them to an OR gate made up of diodes (DU D 2, D 3). 2. Circuit arrangement according to claim 1, characterized in that the output signal of the OR gate is fed to the input of a computer (C) and is regularly scanned by this.