DE2660692C2 - Voltage transformer arrangement - Google Patents

Description

(30) consists of several 1 η losers (31,33,35) coupled in a ring circuit.

5. Voltage converter arrangement according to claim 4. dadui ch characterized in that each inverter to each other having complementary metal oxide half-citer field effect transistors.

6. Voltage converter arrangement according to one of the preceding claims, characterized in that that the signal generator (30) has a signal shaping circuit (32) for shaping the output signal of the

Has oscillator circuit (30).

7. Voltage converter arrangement according to claim 6, characterized in that the signal shaping circuit (32) consists of a plurality of inverters (36, 38, 40) connected in series.

8. Voltage converter arrangement according to one of the preceding claims, characterized in that that the switching device has field effect transistors.

9. voltage transformer arrangement according to one of the preceding claims, characterized in that a gekoppeltet with a terminal of the energy source (10) Pufierkondensator (C 4) and between the buffer capacitor (C 4) and one of the output terminals of the switching device (12 ') connected switching device ( 70) are provided that connect the output terminal of the switching device (12 ') to the buffer condenser tor (C 4) only couples the plurality of capacitors with a particular preset type of connection.

10. Voltage converter arrangement according to one of the preceding claims, characterized in that that the energy source (10) consists of a lithium battery.

11. Voltage converter arrangement according to one of claims 1 to 9, characterized in that the Energy source (10) consists of a silver oxide battery.

12. Voltage converter arrangement according to one of the preceding claims, characterized in that that it is coupled to a drive system for an electro-optical display, which is an electro-optical Display unit, a circuit for generating display information signals and a driver circuit responsive to the display information signals for generating drive signals whose potentials tiale depends on at least the output voltage of the energy source and the lower output voltage voltage converter arrangement, whereby the electro-optical display unit is activated to display information.

The invention relates to a voltage converter arrangement according to the preamble of claim 1.

Particularly in the case of battery-operated small electrical devices, there is a constant requirement that the power consumption is kept as low as possible and thus the battery life is increased. An example this is due to the progressive miniaturization of electronic clocks, the size of which is mainly determined by components such as a crystal oscillator, a pulse motor, display elements and the battery. the

so the battery life is mainly determined by the leakage current of the battery as well as that of the other elements determine the power required. In the case of a mechanically operated display, the Improvements in gear train design made in recent years, along with more powerful motor designs, have increased the amount of power required to operate the display compared to the required power of 10 microwatts a few years ago 1 microwatt reduced. In the case of an electronic watch using a liquid crystal display, the power required to operate the display is less than 0.5 microwatts. Therefore, if the to operate the If the display required power were the only proportional factor in the battery power consumption, it would be possible to use batteries with a tenth of those batteries that have been used previously, or one Achieve long operating times of up to 10 years before replacing the battery. Currently lies however, the power consumption in an electronic watch is in addition to that related to operating the display Power on the order of 3 microwatts to 1.5 microwatts. Two thirds of this power consumption requires the crystal oscillator circuit and one third of this power consumption is used for the frequency divider and other circuits. It can therefore rightly be stated that the main obstacle to the recent trend towards smaller, especially flatter watches and longer battery life.

b5 it can be attributed to the various electronic circuits built into the watch.

Similar problems arise with other small electrical battcriegetricbcncn devices, for example Microcomputers. From DE-OS 23 47 404 an electronic clock is known in which the voltage converter devices are used to generate voltages in the clock which, however, are higher than the Battcricspan-

are. In this case, a charged capacitor is connected via a partially switched diode Field effect transistor adds another voltage

The invention is based on the object of specifying a voltage converter arrangement which has a lower Output voltage than that of the energy source, with this output voltage as lossless as possible, d. H. should be divided with high efficiency.

The voltage converter arrangement according to the invention is characterized by the features of claim 1.

The invention is based on the knowledge that units serving only internal control purposes, such as the crystal oscillator and frequency divider of a clock, can be operated with a lower voltage than, for example, the display device. The energy consumed in such circuits is reduced in this way by a factor which is equal to the reciprocal of the square of the voltage decrease. If the supply voltage is reduced to half the battery voltage, the power consumption is proportional to V- ² , that is, a quarter of the power consumption when full battery voltage is applied or 1/25 if the voltage is even reduced to t / 5 of the battery voltage. The voltage reduction is carried out with the voltage converter arrangement according to the invention with a very high degree of efficiency, ie with the lowest power losses.

The present invention works extremely well in a multi-function watch such as a multiple alarm watch, a calendar watch, etc. is applicable. It is also for anyone Suitable for applications where it is desirable to use two or more different voltages for use the different but interrelated functions. For example, the display of calculation results usually using signals having a relatively low frequency which are supplied with low voltage. However, in order to be able to perform arithmetic operations even at a high speed, one needs higher frequencies and thus an energy source with a higher tension. Since using the voltage converter arrangement according to the invention a high Supply voltage can only be applied to computing circuits when they are actually working high computing speed can be combined with low energy consumption.

Embodiments of the voltage converter arrangement according to the invention are explained below with reference to the drawings.

F i g. 1 shows a block diagram of an electronic clock used in the voltage converter arrangement finds

F i g. FIG. 2 shows in detail the circuit diagram of a preferred exemplary embodiment of the FIG. 1 shown Voltage converter arrangement that provides an output voltage that is half the battery voltage,

3A shows in detail a partial circuit diagram of another preferred exemplary embodiment of the voltage converter arrangement which supplies an output voltage which is equal to one third of the battery voltage,

F i g. 3B shows the circuit diagram of a modification of the circuit diagram shown in FIG. 3A, in which the output impedance with respect to the load is reduced,

F i g. 4A and A B show the basic mode of operation of the voltage converter arrangement in simplified diagrams,

F i g. 5 shows in detail a partial circuit diagram of an exemplary embodiment of a circuit of a clock in which a Voltage converter arrangement is installed together with a voltage stabilization circuit,

F i g. 6A shows in a block diagram another exemplary embodiment of a circuit of a clock in which the Voltage converter arrangement of the present invention together with means for compensating every frequency drift of the crystal oscillator due to temperature changes is built in,

F i g. 6C and 6D show the signal waveforms for the in FIG. 6B circuit shown,

Fig. 7 shows in detail the circuit diagram of a signal level shift circuit by which the level of the Signals generated in the circuit operating on a low voltage supply shifted is used to apply the signals to a circuit that works with a higher voltage supply,

F i g. 8 shows in detail a partial circuit diagram of a modified embodiment of the invention in which for use for a display drive unit, voltages equal to half, equal to one and a half times and generated equal to twice the battery voltage of the watch.

F i g. 9A is a simplified diagram showing the arrangement of a liquid crystal display matrix;

F i g. Fig. 9B shows in detail the circuit diagram of part of the display operating circuit for a liquid crystal display;

F i g. 9C shows the waveform of the signals for the in FIG. 9B circuit shown,

F i g. 10A and 10B show in graphical representations the effects of the voltages applied to the electro-colored display elements;

F i g. IOC shows the circuit diagram of an exemplary embodiment of a control circuit for the electro-colored display elements.

F i g. IOD shows the circuit diagram of an exemplary embodiment of a control circuit for the electro-colored display elements using the voltage converter arrangement according to the invention,

10E shows, in a diagram, the signal waveforms for the in Fi g. IOD shown circuit,

1IA explains in a circuit diagram how the voltage converter arrangement according to the invention is used in a clock is used with an electromechanical converter,

F i g. Fig. 11B is a graph showing the signal waveforms for the Fig. 11B. 11A circuit shown.

F i g. As an exemplary embodiment, FIG. 1 shows a block diagram of an electronic clock with a voltage converter arrangement, the strong lines indicating energy flow paths and the weak lines indicating signal paths. According to F i g. 1, the electronic watch generally comprises an energy source 10, a voltage converter circuit group 12 which contains a signal generator 14 and a voltage converter 16, a frequency standard 18

Frequency converter 20, a timing counter 22, a signal level shift circuit 24, and a display device 26. The power source 10 may, for example, consist of a silver oxide battery or a combination a solar cell with a rechargeable battery.

The signal generator 14 includes an auxiliary oscillator which can provide an output signal, and a wave-shaping circuit which is coupled to the output of the oscillator in order to mutually complementary to deliver output signals. The auxiliary oscillator can consist of CMOS inverter stages, which act as a ring oscillator are switched. The wave-shaping circuit may contain a plurality of inverter stages, as will be described in detail later. The voltage converter 16 contains a number of switching elements that operate synchronously the output signals from the waveform shaping circuit are operated to generate a reduced voltage, e.g. B.

equal to half of the output voltage of the energy source 10, which is shown on the line 17 as V "l / 2 appears. This voltage is fed to the frequency standard 18, the frequency converter 20 and the time measuring counter 22 that operate at a low voltage level.

The frequency standard 18 can be a quartz-controlled oscillator that operates at a frequency of, for example 32 768 Hz oscillates. This relatively high frequency is fed to the frequency converter 20, which is in the form of a

Has frequency divider that divides the frequency down from the frequency standard 18 in such a way that the output signal of the Converter 20 has a low frequency of e.g. B. 1 Hz. This signal is applied to the timing counter 22 which provides various output signals including time and date information. These output signals with smaller Voltage amplitudes are fed to the signal level shift circuit 24 which is supplied with a high voltage, e.g. B. the supply voltage level of the energy source 10 is working. This signal level shift

Circuit 24 changes the voltage level or amplitude of the various outputs from timing counter 22 without changing the information carried. The number of signal paths and the signal frequency, applied to the level shift circuit changes depending on where the level shift circuit 24 is located. If it is ahead of the timing circuits, the power consumption increases as a result the higher frequency. On the other hand, if it is behind the timing circuits, the power consumption

would decrease, but the number of level shift circuits would increase.

The time information or other information contained in the timing counter 22 is displayed by the display device 26 which comprises a display control circuit and display device.

FIG. 2 shows a preferred exemplary embodiment of the voltage converter circuit group shown in FIG. 1. As shown in FIG. 2 is shown, the signal generator 14 includes an oscillator 30, the with the

Battery 10 is coupled and operates on a supply voltage of 1.6 V, as well as a waveform end Circuit 32 which is connected to an output of the oscillator 30. The oscillator 30 includes a plurality of Inverter circuit stages 31, 33 and 35, which are arranged in a ring and each of which is a complementary one Pair of a P-channel metal oxide semiconductor field effect transistor 30a, hereinafter referred to as P-channel MOSFET and an N-channel metal oxide semiconductor field effect transistor 306, hereinafter referred to as

N-channel MOSFET, which are connected between the positive supply line Vdd and the negative supply line V ₅₅ I of the battery 10. The Galeelectrodes of the P-channel MOSFET 30a and the N-channel MOSFET 30i> are coupled to one another and are connected to the output of the inverter 35, ie to the connection node of the drain electrode of the P-channel MOSFET 30 "a and the drain electrode of the N. -Channel MOSFET30 "in connection. Similarly, the gale electrodes of P-channel MOSFET30'a are and the N-channel MOSFET 30 'are coupled together and b, that is connected to the output of the inverter 31 to the connecting node of the Drainelcktrode of the P-channel MOSFET 30a and the drain electrode of the N-channel MOSFET 306th The gate electrodes of the P-channel MOSFET 30 "a and of the N-channel MOSFET 30"/> are coupled to one another and are connected to the output of the inverter 33, ie to the connection node of the drain electrode of the P-channel MOSFET 30'a and of the drain electrode of the N-channel MOSFET 30'ö in Link. As already mentioned, the source electrodes of the P-channel MOSFET 30a are "connected in a parallel to the positive supply line V _IW of the battery 10, while the Sourceelcktroden the N-channel MOSFET 30b, 30 'b and 30"30'a and 30 i> are connected in parallel with the negative supply line V _w i of the battery 10. The oscillator 30 constructed in this way oscillates at a frequency between 100 and 1000 Hz in order to deliver an output signal Φ _ο on the line 34. The current consumption of the oscillator 30 is between 0.1 μΑ and

0.01 μΑ. Field effect transistors with a low slope CM are z. B. for the P-channel field effect transistors 30a preferred in order to reduce the current that flows at the times when both are switched through simultaneously, ie during the voltage level transitions, in each inverter stage ^ The current consumed by the oscillator can also be reduced by the fact that the oscillator is connected to the energy source via a high resistance. The output signal Φα on line 34 is at the waveform end

Circuit 32.

The waveshaping circuit 32 comprises a plurality of inverter circuit stages 36,38 and 40, each of which includes a complementary pair of a P-channel MOSFET32a and an N-channel MOSFET326 the waveform shaping of the output signal Φο from the oscillator 30 is made by the Inverter36 whose output signal to two inverters 38 and 40 connected in series is connected. The output signals of inverters 38 and 40 are denoted by Φ and Φ

each designated and complementary to one another. The signals ^ and Φ are at the voltage converter 16. According to the invention, it is not necessary for the signals Φ and Φ to be exactly complementary to one another. It is, for example, possible to apply a polyphase signal together with its inverse signal to the voltage converter by applying the output signals from adjacent inverters in the auxiliary oscillator to a decoder, for example an exclusive OR element. The reason for this is that the initial

signals from the odd-numbered inverters in the local oscillator have the same level, but their phase differentiate. In the case of the voltage converter of the in FIG. However, in the exemplary embodiment shown in FIG. 2, a single-phase pair of complementary signals is used, for example The voltage converter 16 contains a multiplicity of devices 41 and 41 which store electrical energy

a switching device 42 in order to alternately switch the electrical energy storage devices in parallel and in series between the positive supply line Vdd and the negative supply line V "1 in response to the output signals from the signal generator 14. In Fig. 2, the electrical energy storage devices 41 are shown as a first capacitor Ci and a second capacitor Ci . The switching device 42 consists of a plurality of switching elements, ie a complementary pair of a P-channel MOSFET 44 and an N-channel MOSFET 46 and first and second pass gates 48 and 50, each of which is a P-channel MOSFET and an N-channel MOSFET. The gate electrodes of the P-channel MOSFET 44 and the N-channel MOSFET 46 are coupled to one another and are connected to the output of the inverter 38 of the wave-shaping circuit 32, to which the control terminals of the through gates 48 and 50 are also connected. The source leakage electrodes of the P-channel MOSFET 44 and of the N-channel MOSFET 46 are each connected to the positive supply line V / and of the negative supply line V ₁₅ I. The drain electrodes of the P-channel MOSFET 44 and the N-channel MOSFET 46 are coupled to one another via the second capacitor C2. The first passage member 48 has one electrode coupled to the first capacitor G and the other electrode coupled to the second capacitor Cz. In a similar manner, the second through member 50 is connected to the first capacitor C 1 by one electrode and to the second capacitor C ₂ and the drain electrode of the N-channel MOSFET 46 by the other electrode. The control terminals of the pass gates 48 and 50 are connected to the output of the inverter 40 of the waveform shaping circuit 32.

If, in the arrangement described above, the output signal Φ comes to a high logic level, the switching elements 46 and 48 are switched through, while the switching elements 44 and 50 block. The capacitors Ci and C2 are connected in series with each other across the energy source 10. In this state, the capacitors Ci and G are charged and the sum of the charge voltage is equal to the voltage of the energy source 10. If the output signal now comes to a low logic level , the switching elements 44 and 50 are switched through, while the switching elements 46 and 48 block. In this state, the capacitors Ci and Ct are connected in parallel so that the 2s charge voltage is the same. This voltage, ie VV, 1/2, appears at output 17.

It is possible, capacitors _C1 and C2 to be used that do not have the same capacity. However, in this case, since the voltages to which each capacitor is charged when the capacitors are connected in series are not equal, Joule losses occur due to the charge transfer for voltage equalization when they are switched to the parallel connection. This leads to a drop in efficiency. By cyclically switching the signals Φ and Φ at a sufficiently high frequency, a constant output voltage equal to half the battery voltage at the output terminal 17 is thus obtained. It is appropriate that the conversion ratio of the output voltage of this circuit is decided only by the circuit connection regardless of the value of the capacitances.

The impedance of the MOSFET 44 and 46 and the gates 48, 50 must be in the blocked state must be extremely large and the leakage current from the source to the drain must be very small in order to avoid losses due to the potential between the source and drain in the blocked state.

It is also possible to use a circuit group which is the type of local oscillator shown in FIG. 2 is shown, does not contain. Instead, the switching signals for the voltage converter 16 from the Quartz oscillator circuit, which serves as a time normal signal source, or is supplied by a frequency divider stage connected to the output of the crystal oscillator. In this case the battery voltage would be are applied directly to the crystal oscillator circuit. It is also possible to have an auxiliary oscillator with a different structure also in the example of Fig. 2 should be used. By converting the voltage level to The low voltage obtained in this case can be used to drive the matrix of a liquid crystal display or for Providing low level biases may be used for various components of the circuit.

When a wave-shaping circuit as shown in FIG. 2, which follows the auxiliary oscillator, is not provided, then the current consumption of the inverter stages 38 and 40 will increase. This is due to the fact that the relatively slow rise in the waveform of the output signal Φα of the local oscillator causes a short-circuit current to flow from the battery through the inverters 38 and 40 whenever a signal level transition of the signal Φα occurs ensure that the transitions occur sufficiently quickly that the current consumption by the inverters 38 and 40 is extremely small.

Figure 3A shows another preferred embodiment of the invention which can provide a voltage equal to one third of the battery voltage of the watch. In Figure 3A, a battery 10 outputs its power to an auxiliary oscillator 30 from whose output signal is applied to a waveform shaping circuit 32, the inverters 36,38 and 40 includes When the output signal Φ comes from the inverter 38 to a high logic level, then the N-channel MOS-FET 54 switched through together with the through gates 62 and 58. Three capacitors Ci, C: and Ci are thereby effectively connected in series with one another and with the energy source 10 and are charged by this. If the output signal Φ then comes to the low logic level, the MOSFET 54 and the pass gates 62 and 58, which are referred to in the following as TG , go into the blocking state, while the P-channel MOSFET 52 and 56 and the TG 64 and 60 come into the switched-through state. The capacitors Ci, Cj and Cj are thereby connected in parallel. If these capacitors all have the same capacitance, then each of them will be charged to one third of the voltage of the energy source 10. If they are now connected in parallel, a voltage equal to one third of the battery voltage appears at the output terminal 17 '. Even if the three capacitors Ci, Ci and Cj do not have the same capacitance, then a third of the voltage will appear at the output terminal 17 ', which is equal to the mean value of the voltage to which each capacitor is charged.As already mentioned, are for one optimum efficiency, however, capacitors with the same capacitance are preferred

The larger the capacitance of the capacitors Ci, Ci and Ci , the lower the output impedance occurring at terminal 17 'will be. On the other hand, from the standpoint of reducing the cost of the components, these capacitors should be as small as possible. FIG. 3B shows a circuit in which these contradicting requirements for capacitor dimensioning can be reconciled with one another. Low capacitance capacitors are used in the voltage converter circuit group 12 '. A through element 70 switches the output signal from the voltage converter circuit group 12 'to a buffer capacitor C ₁ with a comparatively large capacitance. It should be mentioned here that the switching element 70 connects the output of the voltage converter circuit group 12 'to the capacitor C ₄ only during the time, while the three capacitors in the voltage converter circuit group 12', the Ci, Ci, Ci in FIG. 3A, are actually connected in parallel. Joule losses due to the charge transfer to the capacitor Ca while the capacitors in the voltage converter circuit group 12 'are being charged from the voltage source are thus avoided. In the structure shown in Figure 3B, the output impedance for the load is reduced.

Figures 4A and 4B show how a voltage equal to n / m times that can be obtained

is voltage of the voltage source. It is assumed that each of the capacitors 72-1 to 72n-m has a capacitance G, that the voltage of the voltage source, ie the potential difference between Von and V "1, is equal to Vo, and that the capacitors have not been charged beforehand. If the circuit is now in the form shown in FIG. 4A, a charge Q = Cn VVn is stored in each capacitor and a voltage Vo / λ appears across the terminals of each capacitor.

InFi g. 4A, m columns of capacitors are connected in parallel which, as mentioned above, contain capacitors with the same charge. If these capacitor connections are now rearranged in the manner shown in Figure 4B, maintaining the same capacitor charging conditions as in Figure 4A, then a voltage m / n ■ V _n across the set of n columns of m- Capacitors appear.

It should be understood that this example is only intended to provide a clear understanding of the basic operation of the To enable the subject of the invention. In practice, a smaller number of capacitors will be used usually sufficient. The following describes two ways in which the number of capacitors can be reduced.

1. If n / m> 1/2, then it follows that (1 - n / m) < 1/2. It is thus possible to use the difference between the output voltage of the voltage converter circuit group and the voltage of the power source to provide a voltage V ₀ (1- n / m) . If the capacitors were arranged in the manner described above, then η times m capacitors of equal capacitance would be required to obtain this voltage. It is thus possible to save (m / 2 - n) capacitors overall if η is chosen to be greater than m.

2. If / η-columns of η capacitors connected in series are switched anew, so that n-columns result from m capacitors connected in series, each of the last-mentioned columns of capacitors connected in series can be replaced by a single capacitor of low capacitance . If there are thus π columns of η capacitors connected in series, ie a total of ^ capacitors, these can be replaced by η capacitors, each of which has a capacitance equal to Mn the capacitance of the series capacitors.

One way in which the voltage conversion in the form shown in Figs. 2, 3 and 4 circuit shown is carried out summarized below.

First, the capacitors are connected in series to each other and to the energy source and from the Energy source charged. Multiple columns of series capacitors can be used with the power source can be connected in parallel or one of the capacitors can be parallel to another capacitor be switched. The capacitors connected in series or the columns of those connected in series Capacitors that are charged in the manner described above are then connected in parallel to one another and the charge voltages are balanced. It is necessary in the no-load idle state that the Charge voltages in the capacitors shortly before the series-connected capacitors are rearranged are the same size in a parallel connection. If this requirement is not met, the result is a lesser one Efficiency. The compensation connector. can be done sequentially in several stages or in different stages Way can be combined with the first-mentioned way.

As already mentioned, it is possible to supply a voltage n / m V ₀ using m capacitors, provided that both η and m are integers and η is less than m . In this case the

m capacitors first connected in series to the energy source and charged by this. One of the m capacitors is then connected in series in parallel with each of the remaining capacitors (m -1) to equalize the voltage across the terminals of each capacitor, resulting in a voltage V ₀ Zm The (m- 1) capacitors remain in series switched and an output voltage is obtained at the terminals of the η series-connected capacitors. The output terminal of the η capacitors can be connected to the one shown in FIG. 3B may be connected to the circuit shown.

In Figure 5, the inventive voltage converter circuit group is in a combination with a Voltage stabilization circuit shown, the work of which is based on the threshold voltages generated by the active semiconductor circuit components are developed. The in Fig. 5 is illustrated embodiment Effective for watches that use power sources such as lithium batteries, which have high performance, for a long time

Have a service life and a better voltage stabilization than silver oxide batteries. The one from a lithium battery however, developed voltage is quite high for use in an electronic watch and is approximately 3.2 V.

In Fig. 5, a battery 90 is connected to an auxiliary oscillator 91 which contains inverters 92, 94 and 96.

which are connected as a ring oscillator with an extremely low current consumption. The output of each inverter is delayed by two with respect to the other stage phases. The waveform shaping of the output signal of this auxiliary oscillator, which is formed by the inverters 92, 94 and%, takes place via a wave-shaping circuit 98, which is composed of MOSFET 100, 102, 104 and 106. The output of the waveform shaping circuit is fed through inverters 108 and 110 to a voltage converter 112 which includes a switch circuit 114 and capacitors 116 and 118. The stepping down to a level equal to half the battery voltage is thereby carried out in the same way as was described for the other exemplary embodiments of the invention. The output signal of the voltage converter 112 is applied to a voltage stabilization circuit 120. A voltage regulating circuit with a characteristic similar to that of a Zener diode is formed by an inverter with a DC negative feedback loop 122. The voltage developed across inverter 122 is equal to the sum of the absolute values of the threshold voltages of the P-channel and N-channel MOSFETs and can be referred to as (| VTP | + VTA /;). Inverter 122 is in series with P-channel MOSFET 124 which is connected as a source follower so that the total voltage developed across the combination is equal to (2 | VTP \ + VTN) The N-channel MOSFET 126 acts as a high-value resistor, so that a small current through the Inverter 22 and the MOSFET 124. The P-channel MOSFET 128 has a large current capacity and operates as a source follower, so that the output voltage at the source of the MOSFET 128 is | VTP |, ie the threshold voltage of Since the voltage at the gate of MOSFET 128 is equal to the sum of the voltages across inverter 122 and MOSFET 124, the voltage drop across MOSFET 124 precisely compensates for the gate-source voltage drop in MOSFET 128 The output voltage at the source of MOSFET 128 is thus equal to the voltage across inverter 122, ie equal to (| VTP | + VTN). Since any change in the level of this voltage due to manufacturing tolerances of the clock's CMOS integrated circuit will be equal to the change in the value of the threshold voltage of the CMOS transistors supplied from the source terminal of MOSFET 128, this circuit provides precise control of the supply voltage independently safe from deviations in the manufacturing process. The output signal of the voltage stabilization circuit 120 is applied to a frequency standard 130, so that the power consumption is reduced to a low, desired level and the frequency of the output signal is not influenced by changes in the supply voltage of the battery.

The frequency standard 130 is controlled by a quartz crystal 132 so that it has an output signal with a generated relatively high frequency. The output signal from the frequency standard 130 is waveform shaping Circuit 134 is fed to a frequency converter 136 in the form of a frequency divider, which divides the frequency from Frequency normal 130 divides down to a low-frequency signal. A time counter 138 receives the relatively low frequency Signal from frequency converter 136 and operates with a slight reduction in power utilization with the same relatively low supply voltage as the frequency standard 130. The frequency converter 136, which is a high main impedance for the power source, is also from a low voltage supply operated so that maximum efficiency results. The level shift circuit 140 and display device 142 operate in the manner previously described.

F i g. 6A shows another example of an electronic watch having a temperature compensation circuit which is assigned to the voltage converter circuit group according to the invention. The electronic clock includes a power source 150 to which a local oscillator t52 is coupled.

The auxiliary oscillator 152, which is not only used as a temperature-sensitive oscillator, but also as a signal generator for the voltage converter works, contains three inverters 154,156 and 158 with low slope. The frequency of the oscillator 152 is controlled by a trimmer 160 and a resistor 162. The capacitor 160 or the resistor 162 has a linear characteristic with respect to temperature so that the frequency of the Oscillator 152 changes linearly with temperature variations. These elements 160 and 162 can also absent and instead the ring oscillator can be designed in such a way that it generates an output frequency, which changes phase in proportion to changes in the ambient temperature. In this case it can the ring oscillator preferably with the one shown in FIG. 5 stabilization circuit 120 shown can be combined. Either the capacitor 160 or the resistor 162 or both elements can be connected to the Plate of the integrated circuit of the oscillator 152 be switched on, so that, for example, the resistor 162 a thermistor or the capacitor can be a capacitor sensitive condenser. In this case The setting of the frequency of the oscillator 152 can be based on a change of such Component. Resistor 162 can also be in the integrated circuit die of the oscillator be built in, while the capacitor 160 may consist of a stray capacitance. One such procedure is possible provided that there is sufficient reproducibility in the manufacture of the integrated Circuit can be retained.

When a super oxide battery is used as the power source 150, and the temperature coefficient of the oscillator 152 is high, then the voltage of the battery can be applied directly to inverters 154, 156 and 158. if however, a Manganbaueric, for example in a household clock, is used or if the temperature sensitivity is supplied by components located on a wafer, as mentioned above, e> o so that the temperature coefficient of the oscillator 152 is not large then it is desirable to use the oscillator 152 from a simple voltage regulator. One suitable type of voltage regulator is the based on Fi g. 5 voltage regulator 120 described above, since this regulator is not just a compensation the changes in the transistor characteristics caused by deviations in the manufacturing process but also provides compensation for the battery supply voltage

The block 164 in FIG. 6A represents a voltage converter, as described above, which is switched by the output signals Φ and Φ from the auxiliary oscillator 152. A crystal, in particular quartz-controlled frequency standard 166 is connected to the output of voltage converter 164 and works with it

Wi

3 * 1 »

a low supply voltage Kss1 / 2. The output signal from the frequency standard 166 is at one first frequency converter 168. which also works with the supply voltage level V ^ I / 2

When an X-cut crystal or a crystal with the orientation I in the frequency standard 166 is used the frequency / of a signal whose partial frequencies are added can be a temperature-compensated frequency deliver, are expressed as:

a) (1) I.

where / o is the frequency at a certain reference temperature. 6? the temperature and a and θο are constants, "'where a = 16 ~ ^4. θο - 25 ° C f ^;

ίο A relatively low-frequency signal from the first frequency conversion element 168 is due to a temperature compensation | sationsschaltung 170 to which a Ausgangssigna] Φ from the local oscillator 152 is applied via line 153 | i temperature compensation circuit 170 includes generally a data-FHP-flop 172 (data type flip-flop), a | j Frequenzquadrierungsschaltung 174, a second Frequenzwandierglied 176, a first frequency summing element 178, an inverter 179, a data flip-flop 180 (data type flip-flop) which serves as a synchronization circuit, a third frequency converting element 182 and a second frequency summing element 184. _ ' in FIG i g. 6A corresponds to the first frequency component, ie the value 1 in brackets in the above equation. ; ' a circuit path on which the output signal of the frequency standard 166 at an input of the frequency §>. summing link 178 and from there via another frequency summing link 184 to the last frequency converter element 186 and the time counter 190. The second expression in brackets in the above frequency equation corresponds to the circuit path via the flip-flop 180 and the frequency converter element 182 to the frequency summing link 184 the temperature component in the equation corresponding to expression (1) gives way via the flip-flop 17Z F ^r equenzquadricrungsschaltung 174 and the second frequency converter section 176 again. r

The flip-flop 172 serves as a frequency test circuit, and generates a test output signal whose frequency is proportional to the number of periods per second by which the frequency of the local oscillator 152 of one previously specified reference frequency has deviated, which can be, for example, the frequency fo / 32 , which is generated at a ί special predetermined temperature of 25 ⁰ C, the temperature with the Temperaturkoeffi- '

is referred to as zero. If the output signal ^ of the oscillator 152 is at the clock input of the flip-flop 172 and the output signal of the frequency converter element 168 is at the data input of the flip-flop 172, if the ν frequency of the output signal Φ is an exact fraction of the frequency of the output signal of the frequency converter element 168 is. the output of the flip-flop 172 are at 0 Hz. For example, the output signal of the first frequency converter element 168 can have a frequency of 16,384 Hz and that of the auxiliary oscillator 152 can have a frequency of 1024 Hz. If the frequency of the oscillator 152 changes to 1023 Hz, then the flip-flop 172 generates a signal with a frequency of 16,384.16 χ (1024-1023) Hz, ie of approximately 16 Hz. The frequency of this output from flip-flop 172 is shown in FIG. 6A denoted by χ.

The frequency squaring circuit 174 generates an output signal having a frequency proportional to the square of the frequency χ of the input signal. The output signal of the squaring circuit 174 is applied to the second frequency conversion element 176, the output signal of which is supplied to the frequency summing element 178 together with the output signal of the first frequency conversion element 168 in order to generate a signal whose frequency reflects the frequency deviation a · f <{8- ofo ^ in the above equation OJ

The output signal Φ of the auxiliary oscillator 152 is thereby synchronized to the output signal of the frequency standard 166, but phase shifted by 180 ° with respect to the output signal of the standard 166, because the 0 signal at the data input terminal of the data flip-flop 180 and that through the inverter 179 are inverted. ; The output signal of the normal 166 is applied to the clock terminal of the flip-flop 180. The synchronized output signal from the flip-flop 180 is divided with respect to its frequency by a suitable factor in the third frequency conversion element 182 and then added to the output signal of the frequency summing element 178 in the frequency summing element 184.

Thus, the frequency of the output signal of the summing link 184 is equal to the sum of the Frequencies of three signals. One of these frequencies is a direct fraction of the frequency of the output signal of the crystal-controlled frequency standard, i.e. H. of the output of the standard 166, the other frequency is a frequency that changes linearly with temperature, i. H. the frequency of the output signal of the third Frequency converter element 182, and the third frequency is a frequency which changes with the square of the temperature d. H. the frequency of the output signal of the second frequency converter element 176. Since this Example exclusive-OR gates used for frequency summing is the one used by inverter 179 Inversion of the clock signal that is applied to the flip-flop 180 is required to produce a correct phase difference to the output signal of the summing link 178 so that the frequencies can be added in the frequency summing link 184.

The output signal from the summing combination element 184 is applied to a fourth or last frequency converter element 186, the output signal of which runs to the time counter 190. The time counter 190 generates time signals that operate the display device 192 and, in the example of FIG. 6A also shows a signal REF which is used in the frequency squaring circuit 174. The operation of an example circuit for block 174 is described below.

As shown in FIG. 6B and in the waveform diagram of FIG. 6C, the flip-flop 172 in FIG. 6A an input signal χ . The input signal REF'isi is a low duty cycle pulse train, as shown in Figure 6B, which remains at the logic high and low levels for fixed periods of time. Although the figure shows that the signal REF is passed by the timer 190 in FIG. 6A, the signal /? E can also be generated by any other oscillator or frequency converter capable of providing suitable pulses. The Signa! REFwWd inverted and in a data flip flop (data type flip flop) 200 with

the clock of the Triggcrtaklimpulsc Φ, \ synchronized, which gives the signal ~ Φκιι . Because the data input and the (^ output of the flip-flop 200 are connected to a NAND gate 202 , a shaped output signal R is generated, the duration of which is equal to one period of the clock pulses Φ ₍ \ The output signal R is used to create a chain of flip-flops 204 which are connected so that they form a first counter, which in this example is a binary counter. The output signal x * from flip-flop 206 is inverted with respect to the input signal χ, with each negative going and positive going transition of the signal x * is synchronized with the negative flank of the pulses Φ _ΐ \ The signal x ** has the same frequency as the signal x *. However , it is inverted and delayed by one period of the pulses Φ _ν \ with respect to the signal jr "Since the Signals at * and χ "are at the blocking inputs of the logic element 208 , a single pulse with a duration equal to one period of the pulses # _c i is applied to each negative edge of the signal x * ie generates a pulse train with the same frequency as the input signal x, but which consists of pulses with a relatively narrow width. This pulse chain is labeled D in FIG. 6D denotes the logic element 210 generates pulses which are identical to the output pulses of the logic element 208 , but which are only emitted during each period during which the signal Qnti is at a low logic level. 6B and 6C labeled Cp.

Following the leading edge of each AEF pulse, the binary counter 204 is therefore reset to zero and is in the binary counter from ti to ti in FIG. 6C a subsequent chain of Cp pulses is counted while the signal Qrf.f is at a low level. The count of the binary counter 204 increases linearly during this time and reaches a final count of, for example, M, as shown on the lower line of F i g. 6C is shown. This counter reading is obviously directly proportional to the frequency of the Cp pulses during the KEF pulse, which is used to count down to the value A / 2, ie proportional to the frequency of the input signal x during this REF pulse. Because of the low duty cycle of the signal ÄEF (suitable values are, for example, one second for the high level of the signal REF and 15 to 300 seconds for the low level) the counter readings stored in the binary counter 204 are very little influenced by noise or instability of the input signal χ For a watch enclosed in a metal case, the time constant for heat conduction of sudden changes in temperature is on the order of 8 to 15 seconds, while the smallest time for changes in temperature due to the watch being worn on the human body is in The order of magnitude of a few minutes. In addition, an additional 20 to 30 hours are required for temperature changes, so that visible deviations in the functioning of the clock are the result. It is therefore possible to make the low level period of the KEF signal very long, for example 1 hour or more, provided that errors in timing accuracy of 0.5 seconds or slightly less can be neglected.

The clock pulses D, from the logic element 208 are applied to a second binary counter 212, which consists of seven flip-flops with outputs Qm, Q01 to Co ?, Q17. The waveforms of these output signals are shown in the upper set of lines in FIG. 6D. If, for example, in the illustrated AND element mati ix 214 the counter 3s was in the counter 204 such that only the output signal Q \ _{b of} the counter 204 is at a high level, then the output signal Qn of the counter 212 is used as an input signal for a Frequency summing logic gate 216 selected. Since the output signal Qi _{6 is combined} with the signal D _x according to an AND function before it is combined with the output signal Qi in the AND element matrix 214 according to an AND function, the signal actually present at the summing element 216 in this case is the in Fig. 6D pulse chain denoted by D _x ■ Qu 1. Similarly, if only the output signal Q15 of the counter 204 is high, a signal Obt · Qn · D »is present on the summing gate 216.

The matrix 214 thus selects pulse trains with different frequencies from the output signals of the counter 212 as a function of the count of the counter 204. The signals selected by the matrix are designated as follows.

Ci = Q) i

C2 = On · Ο »

Cj = Q) I ■ Qö · QiI

Ci = Q) i * Q) 2 * Q) I * Qm

C5 = Q) i Q) 2 ■ Qu Q Q) 5

r) Q) 7

The general equation for the signal output by summing logic element 216 can thus be written as follows:

+ D _x - C ₃ - Q ₁₄

+ D ₁ -G sc

+ D ₁ -G ₁ -Q ₁₂ ^6U

+ D _x ■ C "· Q ₁₁

+ D _x -C ₇ - Q ₁₀

where y is the output from summing gate 216 . As shown in FIG. 6D, the pulse trains represented by the expressions of the above equation are interlocked in such a way that frequency summing can only be done using a logical OR gate. In a similar way, an AND element can also be used if there are impulses running in a negative direction. In both cases, any combination of pulse trains that have any combination of the

Output signals from the counter 204 corresponds, without mutual interference between the pulses in their frequency are added exactly. If an exclusive OR Güed is used for frequency summing, it is only necessary to ensure that the tendrils of the impulses do not meet in the various impulse chains.

As explained above, the is in the counter 204 while the frequency summation is taking place, ie during the time interval fc to fj in FIG. 6C, the stored counter reading is directly proportional to the frequency of the input signal x, which can be denoted by f (x). The value stored in the counter 204 can thus be referred to as k \ ■ f (x) . It can be seen that the frequency of any summed combination of pulse trains selected in matrix 214 becomes proportional to the frequency of the input signal to counter 212, ie, the input signal

to D _x . Therefore, the frequency of any of the pulse trains can be denoted by ki · f (x). Due to the operation of the matrix 214, the selected combination of the pulse trains thus has a frequency which is equal to the product of two quantities which vary linearly with f (x) and which is thus proportional to the square of f (x) That is, that the frequency of the output signal of the summing link 216 in FIG. 6B can be written as:

r (y) -k, f (xP

where k ₃ eKie is the constant for the in FIG. 6B has a value of 2 ~ ⁷

The frequencies of the various pulse trains present at the summing link 214 can be expressed as follows if, for example, ((Q ■ £>,) is the frequency of the pulse chain denoted by Q ■ D _x in FIG. 6D:

((Q ■ D _x ) - 2- '· ((D ₁ ) - 2 "· / CC ₇ · D _x ) ((C ₂ ■ D _x ) - 2-' · f (D _x ) - 25 - ( (Q · D.) ZfC ₃ · D _x ) - 2-> · f (D _x ) - 2 * - ((Q ■ D _x ) ((Q. ■ D _x ) - 2- < ((D _x ) = 2-3 · ((Q ■ D,) f (Q ■ D _x ) - 2-5 · f (D _x ) - 2-2 ■ ((Q - D _x )

((Q ■ D _x ) - 2- "■ ((D _x ) - 2- '· ((Q ■ D _x ) ((Q ■ D _x ) - 2-' · ((D _x ) - 2» · ((Q ■ D _x )

In the waveform diagram in FIG. 6D a logic of triggering on the negative edge is assumed, i.e. H. that each switching of a flip-flop output signal to the one running in the negative direction Edge of an applied clock pulse occurs. Although it is shown in FIG. 6A it is shown that the frequency components of the temperature compensation signal are derived from the 0 output of the local oscillator 152 it is also possible to use other sources for the signals with suitable frequencies and temperature frequency characteristics.

In Fig. 7 shows an exemplary embodiment of a signal level shift circuit for use in the voltage converter system according to the invention or the voltage converter circuit group according to the invention. The input signal A is level-shifted so that it becomes the output signal Λ '. The inverter stage 222 operates at a low voltage and the input signal A and the output signal 222 of the inverter stage 220 are complementary to one another. NAND gates are formed by MOSFET pairs 224 and 226, 228 and 230, 232 and 234 and 236 and 238. These are connected in the form of a bistable multivibrator, so that the P-channel MOSFET 224 is switched through when the signal A is at the low level, the N-channel MOSFET 234 being blocked at the same time. Since the signal A 'is at the high level in this state, the P-channel MOSFET 230 is blocked and the N-channel MOSFET 238 is turned on. Due to the positive feedback effect, the output signal A 'quickly reaches the VW level. The P-channel MOSFET 226 is turned on and the P-channel MOSFET 228 is turned off, while the N-channel MOSFET 232 turns off and the N-channel MOSFET 236 turns on. The circuit is now in a stable state.

The output signal Λ 'is shown in opposite phase to the input signal A. If an output signal of the same phase as input A is required, that signal can be taken from the drain terminals of MOSFET 228 and 230.

In constructing the level shift circuit of FIG. 7 it must be ensured that the current carrying capacity of the P-channel MOSFET is made relatively high and that of the N-channel MOSFET is made relatively low. Then the N-channel MOSFETs 234 and 238 show _{a higher impedance when a voltage (Kv 4} -I - Kv.s2) is applied to their gates than the P-channel MOSFET 224 and 230 when a voltage is applied (Von- KwI) at their gates. This ensures that the setting of the flip-flop is determined by the MOSFET 224 and the MOSFET 230. This condition can be met by making the channels of MOSFETs 224 and 230 relatively wide and those of MOSFETs 234 and 238 relatively long when manufacturing the integrated circuit.

F i g. Fig. 8 shows an example of a circuit of an electronic watch incorporating a further preferred embodiment of the voltage converter circuit group according to the invention. In this case, both an upward conversion and a downward conversion are provided. The electronic watch includes a power source 250 and voltage conversion circuitry 251 that includes a local oscillator 252 coupled to the power source 250. The local oscillator 252 can be of the type of the ring oscillator described above. An output signal of the local oscillator 252 is applied to a wave-shaping circuit 254, which consists of inverters 256, 258, 260 and 262. The inverter 258 perform the 262_und Wcllcnforb5 mung through and deliver likewise complementary Additives food / .schallsignalc Φ and Φ. The switching signal Φ is also generated by the inverter 260 and applied to a voltage downpower indlcr 263, which contains capacitors 263; i and 2Mb. The voltage down converter 263 is similar in structure to the voltage converter illustrated with reference to FIG. 2, so that a detailed description can be omitted. The switching signals

- Φ and Φ are also due to a voltage over- expander 264, the switching elements formed by P-channel MOSFETs 266 and 268 and N-channel MOSFETs 270 and 272 , capacitors 274 and 276 and diodes 278 and

{: 280 contains In the voltage outperformer 264 , the diode 278 is a clamp diode and the capacitor 274 R is a clamp capacitor. When the switching signal Φ comes to the high level, the diode 278 in passage-K is directionally biased the same time, the Elektrodcdes capacitor 274 which is connected to the output of the inverter ir 258, positively charged and the opposite electrode is negatively charged. When the switching signal Φ comes to the low level, the diode 278 is blocked by a bias in the reverse direction and the previously positively charged electrode of the capacitor 274 is at a low voltage level, ie to the voltage Vss \. The potential of the previously negatively charged electrode of the f-condensate; fs 274 becomes even more negative than Viii by the amount (V »» - VvlvI), where Voa is the voltage drop in the forward direction across the diode 278 the diode 278 and the> capacitor 274 a voltage from the output signal of the inverter 258, which is clamped to the potential V ^ l as its high level. The substrate and the source of the N-channel MOSFET 270 are connected together ψ and through a capacitor 282 coupled to the VW line For operation, the MOSFET 270 can be viewed as a diode in the blocked state, the forward direction of the diode being the direction of current flow from the source / to the drain. The output obtained by '■■') clamping signal Φ to potential Vsyl as its high level through diode 278 and capacitor 274 is further rectified by diode 270 , causing charge storage in capacitor 282 If the output impedance of inverter 258 is significantly less than the impedance exhibited by MOSFETs 266 and 270 when they are on, then the high level of clamped output 275 is nearly equal to 2 V.svl. The level is not exactly equal to 2 Vssl, since the forward voltage drop across the diode causes the clamp level to be slightly more positive than Vssl. If the potential at the output terminal 277 is close to 2 Vsyl, then the MOSFETs 272 and 268 at the source have voltage levels Vxsl and 2 Vssl, respectively. Thus, when the voltage level 253 becomes equal to 2 Vssl , since the voltage level 273 is equal to Vss \ , the MOSFET 270 is turned on . Due to the low impedance of the MOSFET 270 in the on state, the voltage drop of the MOSFET 270 in the forward direction, which occurs when the MOSFET operates as a diode, is eliminated.

In this embodiment of the invention, therefore, the forward voltage in a diode clamp circuit can be effectively removed, and a very powerful voltage-stepping circuit can be formed. The circuit can be modified in that when the capacitor 276 and the diode 280 are used, the capacitor 282 is removed. On the other hand, if capacitor 282 is used, then capacitor 276 and diode 280 can be omitted. The diode 280 can be replaced by an N-channel MOSFET whose gate, source and backgate are all connected to line 273 and whose drain is connected to Vss1 . The same principle can be used for the other diode 278 as well.

A second voltage converter 284 operates in the same way as the circuit 264 just described. In this FpIl, instead of the level VwI, the level 0.5 V _S s \ , which is the level of the output signal 265 from the voltage down converter 263, is clamped. By adding Vw! at 1/2 Vssl a potential of 3/2 Vss \ is thus obtained.

As shown in the drawing, therefore, can be achieved by a combination of the above Circuits three or more power supplies with potentials of 1/2, 3/2 and 2 Vssl can be generated. In addition, potentials can be generated that differ from the voltage VwI of the energy source as the reference voltage by 1/2 V $ sl or 2 Vssl in both the positive and negative directions with respect to the potential Vs.s-1 differentiate. A liquid crystal display panel can thus be made using a dynamic matrix drive system operated with an arrangement in which third voltages are applied. Stand with it the voltage applied to selected and unselected parts of the matrix in a ratio of 3: 1 to each other.

The in F i g. The electronic clock shown in FIG. 8 also has a crystal or quartz-controlled frequency standard 286 which generates an output signal with a frequency in the order of magnitude of 2 ¹⁵ to 2 ²² Hz. The output signal from the standard 286 is applied to a frequency converter 288 in the form of a frequency divider which generates a relatively low-frequency signal. This relatively low-frequency signal is applied via a level shift circuit 290 to a time counter 292 which generates 35 signals of the time or date information. These signals are applied to a control circuit 294 which controls the display device 296 in order to display the time or date information.

The following describes one way in which the voltage converter circuit group according to the invention can be applied to a liquid crystal display matrix which corresponds to block 296 in FIG. 8 corresponds to illustrate the advantages obtained thereby. These advantages result from the fact that it becomes possible to use fractions or whole multiples of the Baueric voltage of the clock to generate control signals for the liquid crystal display matrix, that is to say that the optimal voltages required can be used and that in this way the usefulness is as great as can become possible.

In Fig. 9A shows the basic layout of a matrix for a liquid crystal display unit. S \ 1 to 5 "" denote display elements that are controlled via η columns and / n columns of electrode control conductors. The / 7 rows of conductors can be formed on an upper glass substrate while the m-rows of conductors can be provided on a lower glass substrate, these substrates being separated from one another by suitable insulating spacers into which a layer of field effect liquid crystal material in Sandwich Ba'j is stored. In order to address a typical element S ^ im) , the voltages present through the / th row and / th column and common for the display element 300 must be greater than the threshold voltage of the liquid crystal. The liquid crystal element should be able to

so that the element can and should be switched on by a control pulse of a short duration also have such a long decay that the switched-on state during each period of the Control pulses is stored and that the ratio of the threshold voltage to the saturation voltage is greater than 0.5: 1.

According to the waveform diagram of FIG. 9B, each of the rows of the matrix of FIG. 9A, which for example correspond to the upper electrodes of the matrix, selected by one of the signals Φα to Φα _Π ι . The selection of the columns, ie the lower electrodes, takes place depending on whether the switched-on or switched-off state is required for the selected element, by applying either the signal Φ or the signal Φ,.

An example of a circuit for controlling the display which is suitable for use in the voltage converter system according to the invention or the voltage converter circuit group according to the invention is shown in FIG. 9C. The signals # _v represent, depending on the polarity of the signals Sj and 5, either #j or & _s in FIG. 9B. The 0 _V signal thus determines whether the selected element is switched to the switched-on state or the switched-off state. To the element S "in FIG. 9A for example To bring se into the switched-on state, the low level is selected for <ß, j during the time in which the signal Φα is at the high level of the signal Φ , as the signal Φ has. If the signal Φα, is at the low level that the signal Φ has, then the signal Φ », like the signal Φ \, goes to a high level. If again, for example, the segment S ₁ ; + ι is to be switched to the switched-off state, then the signal Φ * is selected as the signal Φ ^ + ι, while the signal Φα; himself on the level

from Φ is located

Due to the capacitance of the liquid crystal elements, a discharge current always flows from the driven segments when the polarity of the changing voltage of the control pulses changes. In the conventional structure of liquid crystal operating or control devices, this current flows through the battery in this way the clock that a higher energy consumption is caused. In order to save this energy consumption

by the signals Φ and Φ, which are at the control terminal of the circuit, to produce the output signal Φα; to generate, which replaces the signals Φ * and <? *, which only differ slightly in phase. In the other case, signals fund £, as shown in FIG. 9B and 9C are shown in such a way that a short-circuit path is formed in order to reduce the effective voltage applied to the segment in the switched-off state to a value which is below the threshold voltage of the liquid crystal cell.

Since according to FIG. 9B the voltage across a segment that is to be switched off can be expressed as (Φα, - Φ ·), whereas the voltage across a segment that is to be switched to the on state can be expressed as (Φαί— Φ ·) , it can be seen that a voltage is applied to switch the segment to the switched-on state which is three times the voltage in the switched-off state, although this high voltage is only for a short period of time applied The respective potential level for the signal Φ _ν in F i g. 9C are Κ »-1/2 for the high level, Ks ₅ I for the intermediate level and Vs <; 3/2 for the low level. While the signal E is at a high level, the signal 0 "is at the intermediate level and when the signal £ is at the low level, the signal Φ ₅₁ varies between V _S s \ / 2 and Vv; v3 / 2. When S _{1 is} high, Φ ^ comes into the same phase as Φ, when # „· is low, Φ _ν comes into the same phase as Φ. The signal Φα; varies between one

high level V _DD and a low level V _s £ with an intermediate level Vss \. Φα; goes to the intermediate level when either £ or D ₁ is high and has the same phase as Φ when D; has a low level The high and low logic levels of the signals Φ, Φ, E, E, D; and D; in Fig. 9C can be viewed as V Od and Vss2, respectively. In the case where the signal is of fine low level, the relationship between the threshold voltage of the liquid crystal and the signals shown in Fig. 9C can be shown in can be expressed in the following way:

(((m - \) (Vss \ l2-Vss \) ² + (V _m > - VssM2f) - = - m) "* < VW ((((m - \) (VssM2 - Vss \ y + (Vim + V _SS \ I2Y) + m ¹ *> VW

Depending on VW, different voltages, such as 1 / 3.2 / 3.3 / 3 and 4/3 of the Voltage of the voltage source supplied using the voltage converter system according to the invention that can be used for such display operation, with three thirds of the Voltage of the voltage source means that the voltage of the voltage source is simply applied directly.

In the liquid crystal materials currently available, those composed in a matrix form can be used Elements are operated with a voltage V _1x of 1.1V. These elements can be operated in a matrix

that consists of 8 columns and 2 rows to 8 columns and 8 rows, for example

It is reasonable to perform information processing on a low voltage and the facility Display signal e, for example the signal 0, to be generated by a level shift to a higher voltage.

The F i g. 10A and 10B show the relationship between the voltages applied to PLZT or electro-colored display elements and the resulting state of the element. The control for an element with the one shown in FIG. 10A depends on whether the element is switched on at point B ' and switched off at point O (Q- (^, or whether the element is switched on at point ^' and switched off at point ^ Q represents the degree of polarization of the element, the oN state occurs at the point ß'und the off state between points a / 'and D'on. the element can thus be switched in that a voltage is applied that is greater than the Range O to A 'and can be switched off in that an opposite voltage with a value between Wound D'angclegl. In the case of an electro-colored display element, a similar control method can be used. In this case, Q denotes the amount of electrochemically separated material ( positive for a separation on the face of the element and negative for a separation on the rear surface).

If a PLZT element, an electro-colored or an elastomeric display element with the characteristic shown in FIG. 10B is used, it is necessary to limit the amount of electrical charge accumulated in the element to a value corresponding to the point D or when the element is switched off corresponds to point A depending on the arrangement or shape of the element. The applied switch-off voltage can also be applied to the point Ofest, which forms a smaller loop. If it is possible to clearly distinguish between the states of the element at points B and £, then the element is switched on by applying a voltage which brings the element into state B and switched off by applying a voltage which is sufficient to bring the element into the state Bring £.

FIG. IOC shows an example of a control circuit 302 for a PLZT element or an electro-colored display element having the type shown in FIG. 10A shown characteristic curve. In response to the rising edge of the display signal Sk , a signal Skon in the form of a single pulse is generated synchronously with the signal Φ. On the trailing edge of the S * signal, a Stoflsynchronous signal is also generated in the form of a single pulse. The Skon signal is used to switch the selected display element to the visible state, while the Skoff signal switches the selected element to the switched off or invisible state.

Fig. Ί OD shows an example of a control circuit 304, which the circuit 3Ü2 of Fig. iOCenthäit. and is suitable for the application of the voltage converter system according to the invention. P-channel MOSFET 306 is turned on when the Skon signal goes high. Thus, the output signal φ * comes to the level VW, when the signal S * o / "/ goes to the high level. Then the P-channel MOSFET SOe is switched through and the signal Φ ^ comes to the level KwI / 4. It should be noted that the signals Skon and Skoff are not both at the same time can the high level view. When both signals Skon and Skoffaui are the low level, the MOSFET 306 and 308 are completely blocked, the voltage applied to the display element 312 thus falls with a time constant to zero. ab.diedurch the leakage resistance and the capacitance of An output signal SP _n ,,,, synchronous with ^ but with a different voltage level is generated by the inverter 310. This signal is applied to the display element 312 in order to jointly generate an electrode voltage that the entire potential on the selected element 312, denoted by V «·. *, the waveform shown in Fig. 10E orm has. In Fig. 1OE are lihflldiWllfdSilPöSSdS / Jfdll

A method by which the voltage converter system according to the invention can be used to increase the efficiency of an electronic watch with a pulse motor is described below with reference to FIG. 11A and the corresponding waveform diagram of FIG. 11B. Part of the circuit portion 322 of the clock in FIG. 11A contains a crystal-controlled frequency standard, a frequency divider and a wave-shaping circuit, which are operated via the low voltage Kssl / 4. The level shift circuit 324 can generate output signals with a lower potential than the negative level of the battery voltage Vssl by utilizing the supply voltage Vss2 generated by a voltage converter. The voltage Vss2 is twice as large as the voltage Kssi and the voltage Vs.st/4 has a value equal to a quarter of the value of the voltage V «l. A pulse motor A / is operated by field effect inverters 325 and 327, which have a high current carrying capacity. When a signal with a low potential with an amplitude twice as large as Vs.y1 is applied to the gates of the P-channel MOSFET 326 and 330, these field effect transistors are switched on. The circuit shown has the advantage that the impedance of the MOSFETs 326 and 330 when switched on is equal to a quarter of the impedance of the MOSFETs which are used in a conventional circuit in which the voltage supply Kv.s-2 is not provided. The reason for this is that a low-voltage signal with an amplitude of 2 ν _ΑΛ 1 is applied to the gates of MOSFET 326 and 330 in order to switch them through. The surface area on the clock's integrated circuit die that is required to accommodate the inverters to drive the motor can therefore be reduced.

In the case of the in FIG. In the circuit shown in FIG. 11A, such a decrease in impedance does not occur when the N-channel MOSFETs 328 and 332 are turned on, compared with a conventional circuit. However, since the gate signals 329 and 331 have a potential more negative than Vssl when these signals are low, the MOSFETs 328 and 332 are completely turned off. Therefore, the leakage current flowing in the MOSFETs 328 and 332 in the blocked state is extremely low.

If the on impedance of MOSFETs 328 and 332 is to be further reduced, this can be achieved by connecting capacitors between their gates and inputs 329 and 333 and 331 and 339, respectively, to form a DC block. The gates can then be connected to the potential Vssl via diodes so that they are clamped to this potential. The input 334 should still be connected directly to the gate of the MOSFET 326, while the input 339 should still be connected directly to the gate of the MOSFET 330 . An additional supply voltage of 2 V _D a d h can also be used. a voltage positive with respect to Vdd may be provided. In this case, the inverters 325 and 327 can be controlled via signals whose logic level range lies between Kss2 and VoD2

From the above, it can be seen that, according to the present invention, an electronic watch with an extremely low Power consumption can be supplied to increase the life of the power source of the watch. It is also it can be seen that according to the invention the combination of the down-conversion of the voltage and the level conversion of the signals in an electronic watch with an extremely high efficiency can be done.

15 sheets of drawings
65

Claims (3)

Patent claims: 1. Coupled to an energy source voltage converter arrangement for outputting an output voltage which is lower than that of the energy source, characterized by a plurality of Capacitors, which are arranged in several predetermined connection options, and through Switching devices for periodically switching the plurality of predetermined connection options the number of capacitors with respect to the energy source, whereby the plurality of capacitors for Output of the low output voltage can be switched periodically in parallel or in series. 2. Voltage converter arrangement according to claim 1, characterized by one with the energy source (10) ίο coupled signal generator (30) for generating an output signal to which the switching devices (e.g. 44,46) respond to connect the plurality of capacitors in a parallel connection or a series connection. 3. Voltage converter arrangement according to claim 2, characterized in that the signal generator has a having an oscillator circuit (30) coupled to the energy source for emitting the output signal is 4. Voltage converter arrangement according to claim 3, characterized in that the oscillator circuit