DE2659221A1 - Integrated semiconductor circuit with MIS logic circuit - responds to at least one input signal and delivers output signal using complementary inverting stage - Google Patents

Abstract

The output signal level is determined by the presence or absence of charges in a load capacitance. The output wire is crossed by a second signal wire. A complementary inverting stage is connected by one end to a voltage source potential and it is connected by the other end a reference potential. It is inserted into the output wire (11) between the MIS logic circuit and the crossing point between the output wire and the other signal wire.

Description

Integrated semiconductor circuit

The invention relates to integrated semiconductor circuits, in particular on an integrated semiconductor circuit with NIS (Netall-Isolator-Semiconductor) -Logic circuits consisting of MIS field effect transistors (FET).

Logic circuits made up of MIS-FETs can generally be divided into two Types are divided, namely so-called. Relation logic circuits and so-called. Relationless Logic circuits. The ratio logic circuit can depend on the ratio the conductivities gm between a load and a feed or driver MIS-FET generate a binary output signal, while the disproportionate logic circuit does this is intended to generate a binary output signal with two different levels, by removing previously stored charges from a load capacitance via a switching MIS-FET discharged, which is controlled by an input signal, the Ratio logic circuit has the disadvantage that it has a relatively high Consumption of electrical power has, since over the load and the feed MiSFET A direct current flows0 In contrast, the power consumption can be reduced when the Logic circuits are significantly reduced because the consumed electrical Power can only be attributed to the charging current of the load capacity. aside from that can use the proportionless logic circuit in high integration density on a proportionately small area, because the ratio between the conductivity of the Load MISFET and the switching MISFET to which the input signal is routed to r, need not be used.

In the case of integrated semiconductor circuits, it is common practice to use the Wiring to be carried out in the form of multilayer wiring, with the lowest Metallization layer an electrically conductive polycrystalline silicon layer is used, on which an interposed film made of PSG (phosphosilicate glass) a metallization layer of Al with a thickness of 1 to 0.9; is formed. As a result, parasitic capacitance arises at the intersection of the two Metallization layers, which because of the crosstalk in the case of the disproportionate Logic circuit whose signal level is in a floating or floating state can lead to incorrect operation.

A complementary MI S circuit does not, in principle, consume any power and generates a fixed level output signal, so that the MIS circuit in a relatively wide work area can be operated. In general is however, it is necessary to form n-channel MISFETs in a p-conducting region. Since also twice as many MISFETs as input signals are required the integration density is reduced accordingly.

The invention is based on the object of an integrated semiconductor circuit arrangement with a MIS logic circuit to create that executed with high integration density and operated with reduced power consumption in an extended working range can be.

The semiconductor integrated circuit according to the invention includes a MIS logic circuit that responds to at least one input signal on an output line the same an output signal can be generated whose level by the presence or the lack of electrical charges on a load capacity is determined, wherein the output line is crossed by a second signal line. According to the invention is in a central area or an intermediate area of the output line of the MIS logic circuit provided a complementary inverter, one end of which is connected the potential of a voltage source and its other end to a reference potential connected. The output line is outside the reverse stage through the second Signal line crossed.

With this arrangement, the output line of the MIS logic circuit can a stabilized output signal can be obtained, the crosstalk from the second signal line is suppressed to the load capacitance.

Since the additional complementary reversal stage is only required when the output line of the MIS logic circuit is crossed by the second signal line by restricting the use of the inverter stage to such a MIS logic circuit a relatively high integration density can be maintained.

As further the power consumption of the complementary Reverse stage is theoretically zero, the addition of such an inverse step is not accompanied by increased power consumption. Because the influence of crosstalk is effectively suppressed, the circuit can be operated in a wide operating range will.

Based on the embodiments shown in the drawing the invention explained in more detail. 1 shows the circuit diagram of a circuit arrangement according to an embodiment of the invention, Fig. 2 is a block diagram for Explanation of a general circuit arrangement according to the invention, FIG. 3 the Circuit diagram of a circuit arrangement according to a second embodiment of the form of the Invention and FIG. 4 shows the pattern or the schematic, enlarged plan view of a Integrated semiconductor circuit with the circuit structure according to FIG. 3.

1 shows a circuit arrangement according to the invention with an n-channel NISFET Q1, which forms a switching device, and a clock pulse W1 for precharging a Load capacitor C1 ge. #% - eitor # becomes. A channel MISFET Q5 forms a discharge switching device, which is controlled by a clock pulse # 2 and a discharge path for in the load capacitor cl forms stored charges. The phases of the clock pulses pl, and are to each other so that the MISFET Q1 is turned on or off when the MISFET Q5 is turned off or off is switched on. Between MISFETs Q1 and Q5 are p-channel NISFETs Q2 and Q3 connected in series; parallel to these MISFETs is a p-channel NISFET Q4. the NIS-FETs Q2, Q3 and Q4 to which the input signals A, B and

C are supplied to form a logic block; with positive logic can an output signal A B + C can be obtained from this logic circuit. The level of the Output signal is determined by whether the logic circuit of the p-channel MISFETs Q2 through Q4 is the discharge current path for the load capacitor C1 forms or not when the p-channel MISFET Q5 through the clock pulse ~ 2 is switched on. If the MISFET Q5 is on, it will be discharge the charges stored in the loading capacitor C1 when the current path consists; they are held when the current path fails. The level of the output signal is held until the MISFET Q1 after the MISFET Q5 is switched off by the clock pulse #l is turned on. If accordingly an output line to which the load capacitor ci is connected, is crossed by another signal line 12 and capacitive coupled to this, the load capacitor C1 is supplied with a signal voltage the cutting or crossing signal line 12 is charged via a coupling capacitance C2, when the MISFET Q5 is turned off and the) load capacitor C1 is discharged. An output signal with a reference potential level (ground level) is thus produced according to the invention such crosstalk is prevented by a complementary DC inverter, which consists of an n-channel MISFET Q6 and a p-channel MISFET Q7, and thereby, that the logical output signal is tapped from the complementary inverter.

In other words, according to the invention, the circuit arrangement in which a signal line crosses the output line, the complementary inverter in an intermediate area in the output line before the intersection with the Signal line provided. One end of the inverter is connected to the potential VDD connected to a voltage source, while the other end to a reference or is connected to ground potential. at this arrangement of the reversing stage the influence of crosstalk can be effectively prevented because the output line OUT of the inverter stage at a fixed DC voltage level corresponding to the potential VDD of the voltage source or ground potential.

In the embodiment described above, the n-channel MISFET Q1 is used as a switching device for discharging the loading capacitor C1 in order to Achieve a high signal level by applying a high charge voltage to the load capacitor C1 is admitted.

However, the invention is not limited to such an arrangement. A p-channel NISFET can also be used as a charging switch. In this case a clock pulse 01 with opposite polarity is used instead of the clock pulse ~ 1 is that of the clock pulse ses Fig. 2 shows in a block diagram the general Structure of the circuit arrangement according to the invention. A MIS logic circuit 1 is designed so that the input signals A, B, C, - a logical output signal OUT 'is generated. This forms a binary signal that is dependent on the present or from the lack of electrical charges on the load capacitor C1. If the exit guide 11 of the MIS logic circuit 1 is crossed by a signal line 12, the output signal OUT 'of the MIS logic circuit 1 run once through the complementary reversing stage 2, its output signal OUT on the output line crossed by the signal line 12 li is transferred.

Fig. 3 shows a circuit arrangement to which the invention is applied is on a complementary inverter that acts as an input / output circuit for a cascading read-only memory or read-only memory (ROM) 3 is used. Three n-channel MISFETs QIS, Q16 and Q17 form the read-only memory 3, while a p-channel MISFET Q8 serves as a readout element for read-only memory 3. Input signals 115, 116 and 117 are fed to the control terminals of the n-channel NISFETs Q15 to Q17, while a control signal ~ a is fed to the control terminal of the p-channel MISFET Q8.

The output signal OUT "is from the read-only memory 3 in accordance with Input signals 115, I16 and I17, controlled by the control signal #a, are generated. MISFETs Q9, Q10, Q11 and Q12 form the clock-controlled complementary inverting stage, which is used as an output circuit for the read-only memory 3. The one on one side the inverting stage formed by the p-channel MISFET Q10 and the n-channel MISFET Q11 p-channel MISFET Q9 is connected to a potential Vss; its control connection a control signal ~ b is supplied. The one provided on the other side of the reversing stage n-channel MISFET Q12 is further connected to potential VDD; its control connection a control pulse signal ~ a is supplied. The p-channel NISFET Q9 and the n-channel MISFET Q12 are switched on or off at the same time by the # + control signals from and 4. The output signal OUT 'is generated by the clock-controlled complementary inverter generated when MISFETs Q9 and Q12 are turned on at the same time. The level of the output signal OUT 'can be activated with the MISFETs Q9 and Q12 switched off by the in a capacitor C'1 stored electrical charges are determined, which at connected to the junction between MISFETs Q10 and Q11.

In the operation of the circuit shown in FIG. 3, the MISFET G8 is through the clock pulse ~ switched on, so that a signal at the output OUT "of the memory 3 connected capacitor C3 is discharged. If the MISFET Q8 switched off, so the level of the output signal OUT "is determined by the states of the input signals I15 to 117 of the memory 3 are determined. Switches one of the input signals 115 to 117 does not pass through any of the MISFETs Q15 to Q17, the capacitor C3 does not come out of the Voltage source potential VDD charged. If, on the other hand, all MIS-FETs Q15 through to Q17, then the capacitor CD is removed by these MISFETs Voltage source potential VDD charged.

When the output signal OUT "passes through the input signals 115 to I17 is stabilized, the clock pulses and ~ b switch the MISFETs Q9 and Q12 of the clock-controlled complementary reversal stage. As a result, the inverted output signal appears OUTt 'of the read-only memory 3 at the output OUT' of the clock-controlled complementary reversing stage.

In the circuit of FIG. 3, the output is OUT ″ of the memory 3 Connected to the clock lines ~ b and ~ b via stray capacitances C'4 and C4. Nevertheless sets the crosstalk from the clock lines ~ b and ~ b to the output OUT'1 Dr3ktisch no scfri ##; erigkeit because the phases. of the clock signals ~ b and ~ b each other are opposite and the crosstalk from the clock line the crosstalk from the clock line ~ b practically extinguishes.

On the other hand, since the output signal OUT 'of the clock-controlled complementary Inverse stage is indefinite when MISFETs Q9 and Q10 are off, the Influence of crosstalk must be taken into account. Therefore form a p-channel MISFET Q14 and an n-channel MISFET Q13 'those on the output side of the clock-controlled complementary Inverter stage are provided, similar to a complementary DC inverter stage the MISFETs Q7 and Qg, as described above with reference to FIG. Since that Output signal OUT of the complementary DC inverter stage via the output line 11 is tapped, which crosses the clock lines ~ b and ~ a, a talk about from the crossing output line 11 to the output OUT 'of the clock-controlled complementary Reverse stage prevented.

Fig. 4 shows, as an example, the arrangement pattern in the lower one Half of the circuit shown in FIG. 3 when the circuit is implemented in the form of a integrated semiconductor circuit. In Fig. 4 with solid lines are the control connections the MISFETs, which are formed by a conductive polycrystalline silicon layer and a metallization layer at a first level is shown. The dashed lines represent diffused layers, which under ver # j # aversion of the polycrystalline silicon layer is formed as part of a diffusion mask are. The dash-dotted lines represent metallization layers made of Al, the is isolated from the conductive polycrystalline silicon layer by PSC film.

The part 4, that of a line broken by double dots is outlined, is a p-type area in which the n-channel MISFETs Q11 'Q12 and Q1 are trained. For this purpose, the diffused layer is n-conductive in area 4. A p + -conducting diffused layer 5 serves as a so-called protective ring. A conductive one polycrystalline silicon layer 6 serves as a protective layer to shut off a leakage current to the p-conducting area, which contains the sources or gates of the p-channel MISFETs.

In Fig. 4, reference characters Q8 to Q14 are at locations of the gate areas of the trained MISFETs. A contact CP1 connects the lines of the voltage source VDD, which are formed by the metallization layer made of Al, with the diffused Layers forming the sources of MISFETs Q12 and Q14. A contact CP2 is used to connect the Al lines for the clock signals with the conductive one polycrystalline silicon gate area of the MISFET Q12 ° In addition, there is the metallization layer made of Al via contacts CP4, # P10 and CP, with the conductive polycrystalline silicon gate area of the MISFET Q11, the conductive polycrystalline silicon gate region of the MISFET Q10 and the diffused drain layer of the MISFET Q8. Contacts CP5, CP6, CP11 and cP12 connect the drain of MISFET Q11, the gate of MISFET Q14, the drain of MISFET Q10 and the gate of MISFET Q13 via the metallization layer of Al together. A contact CP15 connects the line from Al for the clock signal ~ 6 with the conductive polycrystalline silicon gate area # of the MISFET Q6 in similar Way, a contact CP16 connects the clock line #a to the gate of the MISFET Q8 during the contact CP r- the line made of Al, which is at the ground potential VSS, with the diffused layer that connects a common source of the MISFETs Q8, Q9 and Q13 represents.

Contact areas CP7, CP8, CP14 and CP13 connect the drain of the MISFET Q14 to the drain of MISFET Q13 'which is the output line. In this context it should be noted that the contact CP is used when the output line is in the upper Area of Fig. 4 is to be wired or formed.

With the circuit arrangements according to the invention described above can the object on which the invention is based, as described, in an advantageous manner Way to be achieved.

In general, the e-complementary DC inverter basically takes no power on. The power consumption is correspondingly due to this additional reverse stage not increased. Since the output signal of the inverter is on the potential VDD or Ground potential Vss is a fixed DC level, the circuit does not suffer the adverse influence of crosstalk and there is no risk of operational errors the circuit. Accordingly, the circuit can be used for an extended working range be interpreted. As the complementary DC inverter stage only in such logic circuits is additionally provided, the output line of which crosses other signal lines, can maintain a high integration density of the semiconductor integrated circuit will. In short, the invention provides a semiconductor integrated circuit with low power consumption, high integration density and a wide working range provided.

In the foregoing, the invention has been described in connection with MIS logic circuits described as an example. However, the invention is limited to the exemplary embodiments not restricted, but can be used to a large extent on any NIS logic circuit be applied, with which an output signal on an output line of the same can be generated on at least one input signal. The level of the Output signal due to the presence or absence of electrical charges a load capacity determined. The output line intersects the second signal line or -> other signal lines.

Claim

Claims (1)

Integrated semiconductor circuit with one on at least an input signal responsive MIS logic circuit for generating an output signal on an output line of the same, its level by the presence or absence electrical charges on a load capacitance is determined D being the output line is crossed by a second signal line g e k e n n n z e i c h = n e t through a complementary Umkehrstuie (2) whose one end with a voltage source potential and the other end of which is connected to a reference potential, which is in an intermediate range the output line (li) between the NIS logic circuit (1) and the crossing point the output line is provided with the other signal line (l2).