DE2657281B2 - MIS inverter circuit - Google Patents

Description

Known MIS inverter circuits have the disadvantage that at certain levels of the input voltage A state of equilibrium can develop in which the output voltage is in the undefined range between the logical "0" and the logical "1" In this state of equilibrium, no recharging current flows to the node capacities. Also in the vicinity of the In the state of equilibrium, the charge reversal currents are very small, so that this critical area is relatively slow is left.

The invention is concerned with an MIS inverter that is clocked with respect to a two-phase clock system circuit, i.e. with an inverter circuit whose logical state should only change during the two clock pulses of the clock system according to a logical input signal.

In integrated circuits or with circuit t> 5 systems with such circuits but the difficulty that the input pulse with respect to his Edge steepness and its phase relation to the clock signals of the clock system is difficult to determine what for example, can be traced back to signal propagation times.

The invention relates to an MIS inverter circuit for generating a pulse that is synchronized with respect to a two-phase clock system from an input pulse according to the preamble of claim 1. Such an MIS inverter circuit was from DE-OS 2315 201 known In this MIS inverter circuit, the lead electrode of the fifth MIS field effect transistor is connected to the voltage supply via a load transistor. The fifth MIS field effect transistor and the load transistor represent an inverter The output of this inverter is one with the second clock signal via the source-drain path controlled MIS field effect transistor connected to the gate electrode of the second MIS field effect transistor.

The object of the invention is a comparatively faster MIS inverter circuit with less Circuit complexity for generating a pulse synchronized with respect to a two-phase clock system an input pulse whose edge steepness and phase relation to the clock system is arbitrary

According to the invention, this object is achieved by those specified in the characterizing part of claim 1 Circuit measures solved

The MIS inverter circuit according to the invention has im remaining over the known advantage that at the former a quasi-stable state of equilibrium is avoided, which can then develop when the voltage at the gate electrode of the second MIS field effect transistor of the series circuit is approximately equal to the voltage at its connection point

The MIS inverter circuit according to the invention is explained below with reference to the drawing, whose

F i g. 1 shows the basic circuit of an MIS inverter circuit on which the invention is based, whose

F i g. 2 to 4 modifications of the MIS inverter circuit according to FIG. 1 concern whose

F i g. 5 shows the circuit arrangement of a first embodiment of the MIS inverter circuit according to the invention, the

F i g. 6 shows the circuit arrangement of a second embodiment of the MIS inverter circuit according to FIG Invention, whose

F i g. 7 show the circuit arrangement of a third embodiment of the MIS inverter circuit according to the invention and its

Fig. 8 to explain the functioning of the MIS inverter circuit according to the invention is used

The circuit arrangement according to FIG. 1 shows a known clocked inverter with the two MIS field effect transistors Γ2 and Γ3 connected in series via the source-drain paths. The input signal is applied to the gate electrode of the second MIS field effect transistor T2, whose source electrode is connected to the reference potential Uss or to ground, via the source-drain path of a first MIS field effect transistor Tl. The first clock signal Φ 1 is applied at the gate electrode of this first MIS field effect transistor Ti. Both the drain electrode and the gate electrode of the second MIS field effect transistor Γ3 of the series circuit, which acts as a load transistor, are connected to the voltage source Udd. The second clock signal Φ 2 receives the gate electrode of the

fourth MIS field effect transistor TA, the source-drain path of which lies between the common connection point of the two MIS field effect transistors T2 and Γ3 forming the series circuit and output A CI means the output capacitance of the clocked MIS inverter circuit.

At any ratio of the 0 values of the two MIS field effect transistors T2 and Γ3

β Tl

where is the source-drain current

i = γ (Ua-

10

15th

is, there is a Ug at the gate electrode of the MIS field effect transistor T2 in which there is a steady-state case with Ua - Ug , ie a case with a negligible capacitor charging current ic where h = h, which currents in FIG. 1 are registered. This state is left only slowly in accordance with an input signal Ue . The MIS inverter circuit according to the invention provides a remedy here.

Instead of the between the dashed lines 1 and 2 of FIG. 1, MIS inverter circuit parts shown in FIGS. 2 to 4 can also be used in the MIS inverter circuit according to the invention with certain advantages. While in the inverter stage according to FIG. 3, the second clock signal Φ 2 also is not applied to the gate electrode of lying on the supply voltage Udd third MIS field effect transistor, according to Figure 2, a further MIS field effect transistor T6, is the gate electrode thereof to the power supply Udd in the circuit arrangement , zv / ischen inserted into the third MIS field effect transistor Γ3

The F i g. 4 shows an MIS inverter circuit part with a complementary pair of MIS field effect transistors T2 and Γ3, at whose common connection point there is a transmission gate with two MIS field effect transistors Tl and TS connected in parallel, to whose gate electrodes the second clock signal Φ 2 is applied.

In the first embodiment of the MIS inverter circuit according to the invention according to FIG. 5, in which the MIS inverter circuit of FIG. 1 is assumed, the common connection point of the two MIS field effect transistors Γ2 and Γ3 is connected to the gate electrode of a fifth MIS field effect transistor TS , whose source-drain path between the gate electrode of the second MIS field effect transistor ΤΪ of the series circuit Tl and Γ3 and the reference potential Uss . This fifth MIS field effect transistor T5, which acts as a discharge transistor at the gate of the second MIS field effect transistor, provides the MIS inverter circuit according to FIG. 1 a preferred position.

In the case of a preferred application with a subsequent digital differentiating circuit, the following conditions apply to be observed:

a) The output resistance of the inverter G 1 connected to the input E must be so small that, despite b5 of the conductive MIS field effect transistor TS, the MIS field effect transistor T2 receives an input voltage that is sufficiently high to see through.

b) The circuit part consisting of the MIS field effect transistors Γ2, Γ3, TA and TS must be designed to be fast enough so that it assumes the final state of logic "0" or logic "1" within the clock pulse duration

The MIS inverter circuit according to the invention as shown in FIG. 5 can be modified using the MIS inverter circuit parts shown in FIGS. The output inverter C 2 controlled by the clock signal Φ1 is connected to the output A.

In the circuit arrangement according to FIG. 5, an inverter G1 with a low output resistance is required according to the above condition a). This disadvantage is in the circuit arrangement according to FIG. 6 by inserting an MIS field effect transistor Γ6, to the gate electrode of which the clock signal Φ 2 is applied, avoided in series with the fifth MIS field effect transistor T5. This makes it possible to use a simple standard low-power inverter for the inverter GX , since no charge can flow away while the MIS field effect transistor Γ1 lying between the inverter GI and the gate electrode of the second MIS field effect transistor T2 is conductive MIS inverter circuit according to the invention caused positive feedback is therefore only effective when the MIS field effect transistor T6 is conductive

In the embodiment according to FIG. 7 of an MIS inverter circuit according to the invention, the gate electrodes of the two MIS field effect transistors T2 and T3 of the inverter circuit part are connected via the inverter G 3. This has the advantage that the positive feedback effect achieved via the fifth MIS field effect transistor TS becomes effective the fastest. This inverter G 3 is preferably implemented in the conventional manner in the form of a series connection of two further MIS field effect transistors

Although in the circuit arrangement according to FIG. 6, a relatively high-resistance inverter G1 can be used at input E , is an MIS inverter circuit according to FIG. 5 faster, since the positive feedback effect of the circuit part with the MIS field effect transistors T2, T3 and 7 "5 starts at the beginning of the clock signal Φ 1.

To explain the positive feedback achieved in the MIS inverter circuit according to the invention, FIG. 8 the two clock signals Φ1 and Φ 2 of the clock system plotted in chronological order. Underneath is an input signal Ue with a relatively low edge steepness, the leading edge of which still falls within the clock range of the clock signal Φ 1 so that a Signa! occurs at the gate electrode of the MIS field effect transistor 7 "2. As a result, the potential at the common connection point of the two MIS field effect transistors T2 and T3 is reduced, but there is no clear logical" 0 "at the common connection point as long as the threshold voltage of the MIS field effect transistor TS is not undershot and this is therefore blocked. Therefore, the charge still applied during the clock pulse Φ 1 in the rising part of the input signal Ue can flow away again from the gate electrode E 'of the MIS field effect transistor T2 , so that an output signal Ua with an unambiguous logical "0" according to FIG. 8 until the next pulse of the tactical pulse signal is set as Φ 1

Because of this behavior, an MIS inverter circuit according to the invention is of particular advantage in digital differentiating circuits, since the edge of an input signal Ue in the “gray area” between a logical “0” and a logical “1” is not differentiated.

The MIS inverter circuit according to the invention can be used in any for the production of MIS integrated circuits suitable technology, the MOS, the CMOS or the silicon gate technology.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. MIS inverter circuit for generating a pulse synchronized with respect to a two-phase clock system from an input pulse which is applied to the gate electrode of a second via the source-drain path of a first MIS field-effect transistor, whose gate electrode is the first clock signal the reference potential lying MIS field effect transistor of the series circuit of at least two MIS Fekleffekttransistors an MIS inverter circuit part is placed, in which the synchronized pulse at the common connection point of the two MIS field effect transistors is the source-drain path of a fourth MIS field effect transistor, at its gate -Electrode the second clock signal is tapped, the common connection point via a fifth MIS field effect transistor whose source-drain path connects the gate electrode of the second MIS field effect transistor to the reference potential and whose gate electrode is connected to the connection point, on the gate electrode e of the second MIS field effect transistor is fed back, and the voltage is supplied via a third MIS field effect transistor of the series circuit, characterized in that one of the two lead electrodes of the drain-source path of the fifth MIS field effect transistor (TS) is connected directly to the gate electrode of the second MIS field effect transistor (T2) is connected 2. MIS inverter circuit according to claim 1, characterized in that a sixth MIS field effect transistor (T6) is connected in the source-drain series circuit to the fifth MIS field effect transistor (TS) , the source electrode of which is at the reference potential (Uss) and the clock signal Φ 2 is applied to its gate electrode. 3. MIS inverter circuit according to claim 1 and / or 2, characterized in that the gate electrodes of the two MIS field effect transistors (T2 and Γ3) of the series circuit of the inverter circuit part are connected via an inverter (G 3). 45