DE2657038A1 - DEVICE AND METHOD FOR REDUCING THE SPEED OF DATA EXTRACTION FROM CHARGE MEMORIES - Google Patents

Description

PATENTANWÄLTE A. GRÜNECKEfi

H. KINKELDEY

Df ¹ . ΙΓ-iü

W. STOCKMAiR

DRING AGE fCALTcCHj

K. SCHUMANN

. “W DFI HER NAT. -

Xerox Corporation ^ρ · ^Η · Jacob

Xerox Square "Γ

Rochester, Hew Xork 14 644 USff

bezold

8 MUNICH 22

MAXIMILIANSTRASSE 43

December 16, 1976 P 10 746-40 / egg.

um VFT? F A HPEN 7, UR WP ^ IHGJi]

DATENABZUGS-G-ESGMIEOIGIvEIT FROM IA

The invention relates to devices, the elements for storing information in the form of electrical Deliver cargo. In particular, the invention relates to the extraction of information from the charge ^ store with einor Speed below normal machine speed.

Recently, a type of device has been developed in which a variable amount of charge can be temporarily stored in elements of an arrangement and then through a FoI ^ e of interconnected filaments through to an output circuit can be pushed. These devices, commonly referred to as charge couplers, can carry an amount of charge store, which is the analogue of a physical parameter. The size remains during a pushing process the load pushed from element to "plement" unchanged and thus provides an analog shift register.

TELEPHONE (OBS) 32 28 63 TELEX OB-3O38O TELEQRAMME MONAP-AT TELEH OPIER

For example, the elements of the analog shift register connected to light-sensitive cells. Fine cargo, caused by the action of light falling on the photosensitive element, can affect the intensity of the light-sensitive element reaching light. A gate circuit that connects the light-sensitive element with a Charge storage co-op, can be maintained, thereby the Transferring intensity-dependent charge of the light-sensitive element into the saliva element. After that, by appropriate Electronic signals transmit the intensity-dependent amount of charge to an output element. It becomes obvious, that by mapping an image onto a matrix of photosensitive elements or by scanning an image A sequence of charges can be obtained along a linear arrangement of elements, which charges are assigned to an image and can be used to reproduce it.

It has been found, however, that the operation of charge storage devices both in the high-frequency and in the low-frequency Operating range is limited. In the area of high frequency Operation appears to be the ability to shift the amount of charge through the elements of the analog shift register, to be limited by such physical parameters as the mobility of electrons in the material that makes up the cells of the analog shift register. imBereidides low frequency Operation seems to be limited by mechanisms that prevent the loss and dissipation of charge into the material of both the register and the photosensitive cells. It is the problem of the low frequency Limitation on what the present invention is concerned with.

An object of the present invention is to provide an improved charge storage device.

Another object of the present invention is to provide an improved Create analog shift registers.

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A broader object of the present invention is low frequency Extract information from an analog shift register.

A particular object of the present invention is the relatively low frequency extraction of successive groups of signals which are assigned to a charge stored in cells of a charge storage device.

Another particular object of the present invention is to divide the elements of an analog shift register into a plurality split by groups and from a group by one behind the other subtract signals from arranged cells during a subsequent register cycle *.

Yet another particular object of the present invention is to provide for the extraction of information from an analog shift register at a frequency lower than the register cycle rate by sending signals
subtracted from predetermined groups of elements during each register cycle and adding the signal groups with
the lower speed can be passed on to an output element.

It is yet another particular object of the present invention create a sequence of signals from an analog shift register that consists of groups of signals, each. Group of signals from preselected analog shift register elements is withdrawn during successive register cycles.

The foregoing and other objects of the present invention are achieved by means which extract successive, sampled portions of the data input during each cycle of operation of an analog shift register arrangement. According to a first embodiment
the elements of the analog shift register are divided into a plurality of groups. During the cycle time in which

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typically the entire signal data of the arrangement is subtracted would subtract a group of "signal data" at a low frequency. Consecutive groups of signal data are extracted in a suitable sequence to achieve a continuous extraction of data from the elements of the arrangement. According to a second embodiment, groups of data signals from the analog shift register are sequentially Groups in a first and then in another of a zx-x-sided arrangement of intermediate analog shift registers pushed. While data signals in one of the intermediate analog shift registers are input, the data signals contained in the second intermediate analog shift register are subtracted.

The output signal sequence in each of the two embodiments consists of a plurality of register signal groups. The signals are sequentially withdrawn from the spring elements of the arrangement. However, each signal group is subtracted ^{during a different register cycle 1.}

A preferred idea is to achieve a lower speed for extracting data from a charge store, in particular a charge-coupled arrangement, than is normally feasible on the basis of the physical parameters of the device. The invention relates to an arrangement of elements of a device which contain the stored charge and which is divided into a plurality of element groups. The data from a single group of elements is extracted during one cycle of operation ^{1 of} the device. During subsequent operating cycles, data is extracted from groups of elements arranged one behind the other, resulting in serially arranged data sequences consisting of groups of data extracted during various operating cycles of the device. The invention further relates to a plurality of intermediate storage devices which store preselected parts of the data sequence of the device during each operating cycle ^1. the

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Data stored in the intermediate facilities are then withdrawn with the lower take-off speed. The intermediate bodies are suitable for recording successive data sections during subsequent operating cycles. The extracted data are serially arranged from sections obtained from different operating cycles.

In the following, the invention will be described in more detail with reference to in the drawing illustrated embodiments explained νerden. In the drawing show:

Fig. 1 is a schematic block diagram of a device for Reduction · of the withdrawal speed of rows of analog shift register elements corresponding to the first Embodiment

2 shows a timing diagram for describing the puncture the device in Fig. 1;

Fig. 3 shows a device for reducing the withdrawal speed a "series of analog shift register elements according to a second embodiment; and

4 is a timing diagram for describing the function of the device in FIG. 3.

In the drawing, FIG. 1 shows a schematic diagram an analog shift register, with assigned light + sensitive elements. The light-sensitive elements 31-42 are sensitive to those incident thereon Radiation and, under suitable conditions, build up a charge according to the intensity of the incident radiation. Each photosensitive element 31-42 is an element of the arrangement of elements 51-62 of the analog shift register. The through gates 71 - 82 create the facilities for the controlled transfer of charge from each photosensitive element 31-4-2 to the associated elements 51-62.

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The transfer of charge is carried out by external signals sent to the gates 71-82 are created, controlled.

The transfer of charge between the elements of the shift register is controlled by signals from a system clock 20. The system clock 20 provides a first output terminal with a series of potential levels between one positive voltage level and a zero volt voltage level. A similar conclusion is drawn to a second conclusion Series of voltage levels out of phase with those of the first output port. The second episode of potentials can be shifted in phase by 180 ° compared to the phase of the first .Fsequence of potentials. When the phase difference between the first and the second sequence of potentials is other than 180 ° or if another charge transfer system is used as the two-phase system, changes can be made in the two described below Embodiments may be required as will be apparent to those skilled in the art. The transfer of charge between the elements 51-62 of the shift register arrangement in FIG. 1 takes place in the direction shown schematically by arrows.

The register elements 51 - 62 are divided into four element groups 51 53, 54 - 56, 57 - 59 and 60 - 62 divided.

The input from the element counter 21 is connected to one of the Clock signals coupled. Bin connection of the element counter 21 is connected to an input terminal of the group counter 22 and coupled to an input terminal of the delay element 23.

Output terminals of the group counter 22 are with input terminals a decoder 24 coupled. There are four on the 24- decoder Output connections are provided, the number of output connections being determined by the number of groups of the shift register arrangement constituting elements is determined. The delay element 23 generates the switching pulses which the switching gates 71 - 82 control.

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Each output connection of the decoder 24 is coupled to a control connection of the "through gates 91» 92, 93 and 94. An input connection of the gate 91 is coupled to an output element 60 of the element group 60-62. Input connections of the gate amplifiers 92, 93 and 94 are each with an output element 57 of _{the element group 57 - 59}} an output element 54 of the element group 54 - 56 and an output element 51 & eT element group 51 - 53. Output connections of the ports 91, 92, 93 and 94 are coupled to connection 100.

The 'function of the device of Figure 1 is by consideration of the timing diagram from Figure 2 understandable. Positive Logic signals are successively generated at each of the four output connections of the decoder 24. These four logic signals are determined by counting the signals generated by the element counter 21. That to the output connection of the delay element 23 applied signal provides a positive logic signal a fraction of a clock period after the beginning of a positive logic signal at one connection of the decoder The time of the at the output terminal of the delay element 23 arriving positive signal is indicated by a count. the clock signals determined. The duration of the positive logic signal at the output terminal of the delay element 23 is used to determine the period of time used during which charge from the light-sensitive elements 31-42 to the shift register elements 51 - 62 is transmitted.

If one summarizes the mode of operation, 10 determines the delay element 23, a time period for the transfer of charge signals from the photosensitive elements to the elements of the analog shift register. The decoder 24 determines by controlling the gates 91, 92, 93 and 94 which group of segment elements Give signals to the output terminal 100. The duration of each of the positive loeik signals created is by the time to remove the storage charge signals the group of elements of the assigned arrangement determines «The time to remove the stored charge is again limited by the length of time in which the charge is in one

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individual element changed by an impermissible amount through various physical mechanisms of charge dissipation will. Because the charge of a quarter of the elements of the arrangement; is removed (in the illustrated embodiment), the extraction of the signals from the entire arrangement can be accomplished at a quarter of the speed that would be possible if the signals had to be taken from the entire arrangement.

In the drawing, in Figure 3 is a schematic diagram of the Second embodiment of a device for extracting data signals from an arrangement of elements of a shift register shown. Photosensitive elements 122-125 can be a Build up charge due to the intensity of incident radiation is conditional. T) he elements of an analog shift register are shown schematically by elements 101-104. Charge built up by the photosensitive elements can lead to a assigned element of the Aiialos shift register v / earth. Gates 126 - 129 control the transfer of charge from the light-sensitive elements to the shift register elements

Charge signals in the element arrangement can be by means of signals from the system clock generator 20 in the seal shown schematically associated arrows are slid · In the preferred embodiment, the system clock 20 generates a group of Lo.eiksignalen between a positive potential and a zero potential change, and a second group of logic signals, which with the first group of signals 180 ° out of phase, which are used to transfer the signal charges from element to element of the shift register arrangement Charge can move from element to element in an analog shift register arrangement using other types of clock signals. However, it requires the use of others Types of Clock Signals Changes in the executing circuit, as will be apparent to those skilled in the art ·

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Logical ITND gates 118 and 119 '"form signal gates for control the application of clock signals to the arrangement of shift register elements,

Two other analog shift register arrangements, in Figure 3 indicated schematically by the elements 106-108 and 111-113, respectively, form shift registers with part of the number of elements of the elements 101-104 Register arrangement. Element 108, the last element in the The direction in which charge is transferred is coupled to port 100 via gate 130, while element 113, the last element in the direction in which charge is being transferred, coupled to terminal 100 via average or 120 is. Gates 120 and 130 apply the signal from element 113 and 108, respectively, to terminal 100 when a positive Logic signal to the control connection of the gate is lived. the Control connections of the nnore 130 and 120 are to the complementary ones A. The output connections of the El ipflop keep us; 28 coupled, this ensures that the signal from only one dor Elements 108 or 113 is applied to terminal 100. The first element of each small shift register north junction, i.e. 106 and 111, with the last element 104, are of the cargo order of elements 101-104 via through gates 145 and 146 coupled, which are also controlled by the flip-flop circuit 28. When a shift register 106-108 is able is to receive input information from the long shift register 101 104, its output is switched off by gate 130 is blocked and the shift register 111-113 outputs through the switched-on gate 120, while the gate 146 is transmitting to shift register 111-113.

The first clock signals used to shift charge between the elements of the array 111-113 are used applied via an output connection of the logical OR gate 139, while the second clock signals, which are used to shift charge between the elements of the arrangement 111 - 113 are used, v / ground via an output connection of the logical OR gate 143. A first entrance

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connection of the OBER gate 139 is connected to an output connection of the logical AND gate 137 coupled, while a second input terminal of the OR gate 13 $ with an output terminal of the logic UND gate 138 is coupled. A first input terminal of the OR gate 14-3 is connected to an output terminal of the logical UND gate 141 coupled while a second input to the connection of the QDKR gate 143 with an output connection of the logical AND gate 142 is coupled. A first clock signal used to shift charge between elements in the array of elements 106-108 is used, is applied through an output terminal of the logical OR gate 133, while a second clock signal, the used to push charge between elements in the array of elements 106-108, via a Output terminal of each logical OR gate 136 is applied. A first input connection of the OPER gate 133 is with a Output terminal of logic [MD gate 131 coupled while a second input to the connection of the OR gate 133 with a Output terminal of the logical AND gate 132 is coupled. A first input at the end of the OR gate 136 is with coupled to an output connection of the logical ÜND gate 134, while a second input terminal of the OR gate 136 with An output to the connection of the logical üilD gate 135 is coupled is. A first clock signal from the system clock generator 20 is with a first input connected to the AND gate 131 and a first Input terminal from AND gate 137 coupled. A second clock signal from the system clock 20 is connected to a first input terminal from AND gate 134 and a first input terminal coupled from gate 141. A first entrance from UM) gate 132 and a first input connected to the AND gate 138 are coupled to an output terminal of the flip-flop 29, while a first input terminal of the AND gate 135 and a first input terminal of the UNB gate 142 with a complementary one Output terminal of the flip-flop 29 are coupled. A first output terminal of the plip-flop 28 is connected to a second

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Input terminal of the AND gate 142, a second input terminal of the AND gate 138, a second input terminal of the AND gate 134, a second input terminal of UITD gate I3I and a control terminal of the gate 145 coupled. The complementary output terminal of the flip-flop 28 is with a second input terminal of the AND gate 141, a second Input terminal of the AND gate 137 * to a second input terminal of the AND gate 135i to a second input terminal of the AND gate 132 and a control terminal of the gate 14-6 coupled.

A signal from the system clock 20 is on an input port of the counter 25, to an input terminal of the counter 26 and applied to an input terminal of the counter 27. An output terminal of the counter 25 is connected to a second input terminal of AND gate 118 and coupled to a second input terminal of AND gate 119. An output terminal of the Counter 25 is connected to control connections of the slack gates 126 129 created. An output terminal of the counter 26 is with an input terminal of the flip-flop 28 and an input terminal of the counter 121 are coupled. An output terminal of the Counter 2? is applied to a flip-flop 29. An output terminal of the counter 121 generates a reset pulse which turns on Counter 25, counter 27, flip-flop 28 and flip-flop 29 is applied.

The function of the device in FIG. 3 can be understood by comparing the figure with the timing diagrams in FIG. The mode of operation is as follows: the signals thawed in the elements 101-104 are ^{transmitted out of the arrangement at a relatively high speed during a device cycle 1} (1100 clock periods). Elements of the arrangement elements 101-104 are transferred to arrangement elements '111-113 during cycle number 1100 "to cycle number 2200. During the next cycle 'the charge signals are transferred to terminal 100 at the lower speed determined by counter 27 and flip-flop 29» The charge signals from the successive groups of elements

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are applied to port 100 up to the 20th sequence. After this sequence, the counter 121 resets the counter 25, counter 27, flip-flop 28 and flip-flop 29 in order to synchronize the system. The extraction of charge signals from either of the two embodiments can take place at a lower speed than the speed limited exclusively by the properties of the register arrangement. As a result, in either embodiment, a sequence of signals associated with stored charge in a sequence of elements of an array is delivered at a slower signal rate than the physical properties of the main register permit. Furthermore, the output sequence of signals is not created by the same scanning process - transmission from the photosensitive elements to the element array. The output sequence of signals is removed in groups in successive removal processes. A portion of signals from the arrangement of elements 101-104 is shifted into a first of the small register arrangement consisting of elements 106-108 or the small register arrangement consisting of elements 111-113. During the next device cycle ¹ , a portion of the signals from the elements 101-104 of the large arrangement follows the element from which the portion of the signals transmitted in the previous device cycle was subtracted. At the same time, the signals from the original small array of elements are applied to output terminal 100, but at a slower rate. In FIG. 3, m relates to the number of elements in the large register arrangement and in FIG. 4 1000 has been chosen as an example for this number. In FIG. 3, η relates to the number of scans which are used to carry out a complete scan, and in FIG. 4 20 was chosen as an example for this number.

Consequently, the counter counts 25 I050 (m + m) cycles of one

η system clock signal. An output of the counter 25 switches

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AND gates 118 and 119, producing charge transfer signals on items 101-104. At the end of a count of 1000, the counter gives 25 signals, that turn off gates 118 and 119, and signals that turn on amplifier gates 126-129. During the on the count of 1000 following period becomes charge from the photosensitive elements 122-125 to the register array elements 101-104 transferred. At the same time, the counter 25 counts 50 (m / n) cycles of the system clock signals. After a count of 50, the counter 25 switches over, xby amplifier gates 126-129 are turned off and AND gates 118 and 119 are turned on. From the number of cycles IO50 up to the cycle number 1100 become the charge signals of the first 50 elements of the arrangement of elements in the 50 elements of the arrangement of elements 106-108 are transferred. The system clock signals are, in addition to being applied to the array of elements 101-104, also applied to elements 1Q5-108, with the output of flip-flop 28 the AND gates I3I and 134 and the Through gate 145 turns on. When counting 1100 (m + 2 m / n), the counter 26 generates a pulse, its signal the counter 121 counts by one and causes the state of the flip-flop 28 to change, whereby the AND gates 131 and 134 and gate 145 switched off, but the AND gates 132 and 135 are switched on.

At the same time, the counter 27 delivers (n + 2) / 2 after every 21st Cycle the system clock one pulse. The pulse causes the flip-flop 29 to switch. The one from the flip-flop 29 output logic signals are used to form low frequency charge transfer signals, the Complementary connection supplies the signal that is opposite to the direct flip-flop output signal is 180 ° out of phase. Hence, at a count of 1100, the low frequency . Charge transfer signals via the now connected AND gates 132 and 135 to the arrangement elements

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106 - 108 created. At the same time, the flip-flop 28 has a das-amplifier gate 130 turn-on signal supplied so that the Charge signals in the array elements 106-108 to the Terminal 100 can be created.

Count 1100 compartment becomes the system clock signals applied to the arrangement elements 111-113. It is it can be seen that the actuation of the counter 25 and the Counter 26 out the charge signals from the second fifty Elements shifted into register elements 111-II3 during the period between cycle counts 2150 and 2200 and shifted out between the 2200 through 3300 cycle count on port 100.

For a person skilled in the art of semiconductor materials it can be seen that many of the components used in the present invention are incorporated into the same material from which the analog shift register is made. The various logical elements and gates, as well the second analog shift register of the second embodiment can be shared with the shift register Substrate to be included.

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Claims (12)

Patent claims 1. Analog slide register, marked by an array of analog shift register cells (51-62), by means for inputting signals into the shift register cells and by electronic means for subtracting successive groups of information from the cell array, the successive devices create a signal sequence in which each component of the signal sequence is assigned to a signal originating from an assigned fan cell. 2. Analog shift register according to claim 1, characterized g e ken η shows that the arrangement of shift register cells (51-62) into a plurality of groups is divided by cells and that the successive facilities facilities for extracting data from each of the groups included in a preselected order. 3. Analog shift register according to claim 1, characterized by a first group of analog eegister cells (51-53), a second group of analog shift register cells (54-56) and devices for successive loading of successive groups of information from the array of cells and means for simultaneously extracting information from the other second set of Shift register cells. 709827/0833 ORIGINAL INSPECTED 4-, device for the extraction of signals, which one in Elements of an analog shift register are assigned to the charge entered, marked by devices for the periodic input of charge signals into the shift register elements, Means for extracting a sequence of charge signals from a preselected one of the shift register elements devices during a time period associated with the time period of the charge input devices for controlling a group of shift register elements which are addressed by the means for extraction wherein the control device causes a predetermined series of groups to be addressed by the extraction device. 5. Analog shift registers of sequential type Deduction of signals from elements of the shift register, characterized by devices for periodic input of signals into the shift register elements and devices for the extraction of signals from predetermined sequences of groups from the shift register elements. 6. Analog shift register, characterized by a large number of shift register elements, Means for transferring charge from one shift register element to an adjacent shift register element and means for extracting signals from a successive group of shift register elements during successive shift register cycles. 709827/0633 7. analog shift register according to claim 6, characterized by a device for applying signals from a preselected group of shift register elements to an output terminal of this Shift registers, means for inputting signals into the remaining groups of shift register elements and means for disconnecting the transmission facilities from the groups of! legal elements in which signals are input ". 8. analog shift register according to claim 6, characterized in that the means for deduction of signals comprises at least a first and a second secondary shift register arrangement of elements. 9. Analog shift register according to claim 8, characterized in that the device for deduction of signals Means for transmitting signals 'included therein at a first and second frequency. 10. Analog shift register, labeled by a plurality of elements for storing charge, which are arranged in a predetermined sequence, Means for transferring charge to an adjacent subsequent element in a predetermined one Direction, clock devices for determining a working speed of the transmission devices, devices for entering charge in at least a part of the register elements after a preselected one has elapsed Period of time and means for transferring charge to one terminal from a portion of the shift register elements during the selected period. 709827/0633 11. analog shift register according to claim 10, characterized g e kenzeich that a plurality of the shift register elements are coupled to the terminal, wherein the plurality of shift registers forms a plurality of groups of shift register elements. 12. Analog shift register according to claim 10, characterized by two secondary analog shift registers, Means for transmitting signals from successive groups of elements to alternately one or the other of the two secondary shift registers and devices for the extraction of signals from the secondary shift registers at a slower rate than that determined by the clock Speed. 709827/0833