DE2656854A1 - READING STATION - Google Patents

Description

Reading station

The invention relates to a single reading station used for character recognition. The invention "relates in particular on the optical character data acquisition, and in particular on a method and a system for optical Character data acquisition in which there is the ability to place one or more lines of writing on the face find, capture and select a continuously moving document.

There are two widely used plague methods and for reading lines of print that are randomly placed anywhere within a relatively large Detection area on a document, such as a letter, cashier's check, or credit card statement. In one of these methods, a single scanning device, usually a scanning device with a movable scanning point, namely a cathode ray tube, used to roughly scan the detection area first, to determine the lines of character data (locally); a second pen scan is then made to capture the character image and convert it into electrical © signals for character recognition. This possible solution makes it necessary that the document remains stationary during the scan sequence so that the subsequent line scan with the character line position data, which during the original rough

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TELEPHONE: (089) 298527

TELEX: 5-22039 patwd

-V

can be related.

The second commonly used method achieves the same result of generating electrical signals for character recognition in moving documents. In this last-mentioned solution, however, two reading stations are required, each of which usually requires a linear array of photocells in order to cover a tape on the document. The first reading station, commonly referred to as the "prescan" or "search station" ¹ , picks up the image of the array of character lines for a complete detection area, and the data from this first reading station is processed in the form of electrical signals to determine the location The resulting line coordinate data are made available to the control electronics of the second reading station, which is arranged downstream of the first station at such a distance that this second reading station can access a detailed image of the This is achieved by arranging the sensors either mechanically in the correct vertical position for the detection of the drawing lines of interest, or this is done electronically by selecting only those sensor outputs which he is in the correct vertical position in a large linear array of photocells. thus determining the selected line in an arrangement of character lines on a document. Horizontal positioning in this second method is achieved by turning the sensor outputs on and off at the correct time with respect to a reference point on the document, usually the leading edge.

It is a feature of the present invention to provide a data acquisition system in which documents "im

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Plug ", i.e. in passing, at a single reading station which extends across the document movement. By reading documents in passing, the result is "considerable time savings in data acquisition and processing compared to stationary document reading, which has inherent limitations on the speed of document handling and beyond requires complicated document transport to start a document for reading, to stop and to be arranged precisely. Another feature of the present invention is thus to provide data acquisition, which uses simplified document transport without complicated document registration requirements are. The described dual reading station method adds considerable complexity to the transport device required because the document along a very precise path between the first and second reading station, especially in the vertical plane, since the measurements at the first station are fed to controls, which the second Set reading station to operate on a selected relatively small area of the document. Another one An advantageous feature of the data acquisition system according to the invention is that a minimum of tracking electronics (Tracking electronics) is required in order to complete the data acquisition on a moving document. In contrast, the aforementioned two-step process involves a considerable amount of complicated electronic devices required for document guidance in order to take the lead when a document is moved in the area between the reading stations maintain and synchronize operations. This complexity is compounded by the fact that there is likely to be a document at the first reading station while another document is being read moves past the second reading station.

-ΛΑ-

The present invention relates to a detection system with a single reading station, wherein the entire detection area (detection area) of a document to be read is captured when it moves past a single reading station. The image data read from the passing document are processed in real time using logic circuits to locate the parts of interest the coverage area, d. H. of the character lines to be read from an arrangement of character lines. Using With the present invention it is not necessary to keep the entire image of the detection area in memory, but only a portion of it that is large enough to allow the precise determination of the parameters that can be selected the areas or areas of interest (drawing lines) are required.

According to the invention, the character image data are processed in real time, when the document moves past the reading station and only the data of interest is retained by successive selection (selection) of those areas of the drawing image area which are used for data processing is of interest. Two memories are used for the character data, each memory in its puncture is more specialized than the previous memory to add final drawing picture lines in the last memory of the sequence contain. The number of storage levels is determined by the number of processing steps that are required to resolve the final selection and to process the character data before being applied to a character recognition unit. At each processing step, the image data is selectively reduced to the essence of the information that is specific to a particular one Processing step is required. At the same time, the character image data can be moved from a storage stage to be changed to the next.

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According to the invention, an optical scanning system is provided in which a transducer detects adjacent patterns at a distance arranged lines are scanned to provide digitized (digitally represented) pattern data, simultaneously to means for storing the pattern data of all of the spaced lines scanned by the transducer, and on means to find the patterns from the array of spaced lines to generate line restraint signals and of line reading signals. Through the lines to hold signals Identified patterns are transferred to a memory for the purpose of recording the pattern data for further processing by circuitry responsive to the line read signals to permit the transmission of only selected sample lines to effect a character recognition unit.

Furthermore, according to the invention, successive scans of the neighboring patterns represented by the digitized pattern data compressed into search segments, specifically for the determination the top and bottom layers of each of the spaced rows. These segments are further analyzed, to determine their connection relationship with other search segments for further processing to find an or select several of the spaced-apart lines (lines) of the pattern for transmission to a recognition unit.

Further preferred refinements, objectives and advantages of the invention emerge in particular from the claims and from the following description of exemplary embodiments based on the drawing. In the drawing shows:

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Pig. 1 is a perspective view of a mail address scanner system use case of the present invention using a single reading station;

Pig. Figure 2 is a block diagram of a single station Video capture system with the video electronics assembly, search electronics assembly, storage electronics assembly and reading electronics assembly;

Figure 3 shows a document with three spaced lines (Lines) of character patterns, the inventive Video capture technique is shown;

Pig. Figure 4 is a block diagram of the search correlator logic of the search electronics assembly the pig. 2;

Pig. Figure 5 is a block diagram of the search analyzer of the search electronics; Figure 6 illustrates the effect of search analyzer compression data from the search correlator from 32 samples into a single search segment;

Pig. 7 is a block diagram of the top / bottom detector logic of FIG Search electronics of the Pig. 2;

Pig. Figure 8 is a block diagram of the segment connection logic of the Pig search electronics. 2;

Pig. 9 is a flow diagram of the operating sequence of the control electronics the segment connection logic of the Pig. 8th;

Pig. 10 is a logic diagram of the top / bottom comparison electronics the pig. 8th;

Pig. Figure 11 is a logic diagram of the Pig's line allocation electronics. 8th;

Pig. Figure 12 is a logic diagram of the output format electronics of Figure 8;

Pig. Figure 13 is a block diagram of the line track microprocessor the search electronics of FIG. 2;

Figure 14 is a flow diagram of the plan loop of the microprocessor the search electronics of FIG. 2;

Fig. 15 is a flow chart of the line trace controller of the microprocessor;

16 is a logic diagram of the stripe memory of the memory electronics of Fig. 2;

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17 shows a logic diagram of the extraction registers of the storage electronics;

Fig. 18 is a block diagram of the line block memory controller the storage electronics of FIG. 2;

19 is an illustration of possible positions of the scan data available from the line block memory;

Fig. 20 is an illustration of two adjacent data blocks (multiple scans stored as one unit) in line block memory on a sloping line;

Figure 21 is a logic diagram of the window selection and data format apparatus of Fig. 2;

Figure 22 is a flow diagram of the window selection logic of the format engine of Fig. 21;

23 shows a series of timing pulses illustrating the basic Specify system timing for processing the sample data;

Figure 24 is a timing diagram of the extraction registers of Figure 2 for transferring data between the stripe memory and the line block memory;

Fig. 25 is a timing diagram for the transmission of sample data into line block memory;

26 shows the processing incidents depending on the time for the processing of data and the Transmission of the same by the device according to the invention;

27 shows a representation of five adjacent data blocks in the line block memory for transmission to the window selection and format logic of FIG. 2.

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In Fig. 1, an envelope or other data bearing document 10 is shown and is being processed one at a time at a high speed from a document input module to a transport system entered and moved past the viewing field 14 of an electro-optical scanning module 16. The document 10 is in the Direction of an arrow 18 transported, the whole parallel to an arrangement 20 of lines of characters to be scanned or Drawing lines.

After the document 10 has been scanned, it is transported to a sorting and stacking module 22, where it is sorted according to the Information is arranged in the character lines in a preselected group. An image of the arrangement 20 from across the Lines of characters extending along the length of the document 10 are illuminated by lamp assemblies 24 and 26 and by means of a lens assembly 28 is projected onto a photosensitive scanning device 30 which has a self-scanning photodiode array may have. Typically, the photodiode array 30

Include 512 photodiodes to provide a field of view across a typical document width.

The photodiode array speaks in accordance with the usual character reading processes 30 responds to the incident light level at each of the photodiodes and generates a sequence of output signals. The output signals of the photodiode array 30 are applied to an electronic processing circuit 32, and after processing to an electronic memory circuit 34. Data is sent from the memory circuit 34 to a (not shown) character recognition unit that generates decision signals which are input to a computer for use will.

Fig. 2 shows a block diagram of the video search memory and reading electronics assemblies of an optical character processing system according to the invention. The lamp assemblies 24 and 26 and the lens array 28 are represented by block 36, with patterns on the spaced lines 20

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the self-scanning photodiode array 30 can be projected. The lens assembly 28 is arranged so that they entire array of spaced lines 20 of patterns on the surface of document 10 intercepts. A picture the pattern array is applied through the lens array 28 onto the surface of the self-scanning photodiode array 30 projected. Data from the self-scanning photodiode array 30 is fed into operational amplifiers via a channel 38 40 entered with high gain. The high gain operational amplifiers can typically be an integrating amplifier which has a capacitor feedback from the output of the amplifier to the input channel 38.

The output of the operational amplifier 40 is coupled to the input of the analog / digital converter 44 by means of a channel 42. At the output of the analog / digital converter 44, a series flow of four bit data words is generated, which the are digital equivalents of the photodiode output signals from array 30. The data word output rate from the analog to digital converters 44 is the same as the scanning frequency of the photodiode array. Preferably the digital word "0000" assigned to the output status of the analog / digital converter, when a photodiode sees a completely white area, whereas the digital word "1111" is the output then is when a completely black area is seen.

The analog / digital converter 44 can be a chain τοη gate or Have dropping resistors connected to respective level or level detectors, each of which is connected to a Reference voltage is present. In operation, pulses are generated from analog video data of current waveforms applied to the analog-to-digital converter 44, and a four bit digital representation of the analog value is received on a channel 46. As a result of the integration, the photocurrent time average for the sampled Area of each of the character patterns in the spaced-line array 20 is obtained.

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The digital pulses on channel 46 represent one of the 16 possible "gray levels" that differ from black pattern signals extend to white pattern signals.

Digitized video signals on channel 46 are input to storage electronics 34 and search electronics 32 at the same time. With regard to the memory electronics 32, it should be noted that digitized pattern data are entered into a strip memory 48 which consists of an arrangement of serial buffer registers which have a storage capacity which is sufficient around each line of the character patterns in the spaced Contain lines 20. Functionally, the stripe memory 48 acts as a video delay to allow time for the search electronics 32 to find the approximate location of potential lines for future processing.

When the location of identifiable lines in the strip memory 48 is determined, only the stored video data relating to the identifiable lines is retained for future use Processing withheld. Data relating to the identifiable lines of character patterns is obtained from the Stripe memory 48 is transferred to a line block memory controller 50 by means of an extraction register 52. The line block memory controller 50 consists of a random access memory (RAM), the extraction register 52 being the standard gate logic exhibit.

While the lines of the character patterns of interest are being stored in the line block memory 50, additional Information regarding the character patterns and lines determined from the video data by means of the search electronics 32. This additional information includes a decision as to which storage elements of the line blocker 50 sample lines that are to be transmitted to the recognition unit 58, together with the necessary Parameters of the lines to be read. As in the following

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will be refined, the parameters determined by the search electronics 32 also include the start and stop positions of a Line on document 10, the typical line height (referred to as the normalization factor) and the position of the bottom of the line (representative for the starting line bottom and the skew angle).

When all the parameters of the lines of interest are in the line block memory 50 are determined, the data representing the lines of interest are stored from memory 50 in a window selection and format device 54 as the output stage of storage electronics 34. The selection and format device 54 selects that part of the line block memory 50 which contains the digitized video information which the character pattern which immediately surrounds the lines of interest and is otherwise referred to as a data block. This selected digitized Video information is then fed to reading electronics 58 via channel 56.

Selected line data on channel 56 is initially input to normalizer 60 which does the normalization of the image performs in both vertical and horizontal directions, reducing the overall video field to a selected one Size can be reduced. This character data normalization is carried out in accordance with conventional normalization methods. In addition, the normalizer in conjunction with the window selection and format device 54 effects one skew correction to remove the skew of the selected line read from document 10.

The output of the normalizer 60 is input to a correlator 62 which is the gray level data or gray level data on channel 56 evaluates into black or white digital character signals. The result is a serial data stream a channel 64, namely digitized Videc information of one bit per cell in the photodiode array 30. Die black character data and the white character data are saved in

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a video memory 66 is entered and stored for serial delivery to a character recognition unit. Both the correlator 62 and video memory 66 are common character recognition components.

Simultaneously with the supply of video data from each scan of the document 10 to the strip memory 48, the The same data is also fed to a search correlator 68 which converts the four bit video data into a single bit black and white decision on an output channel 70 converts. The black and white video on channel 70 becomes a search analyzer 72 which performs the function of compressing the video pattern data from multiple search scans in a single search segment. For example, every other scan of is carried out by the arrangement 30 64 search samples compressed by analyzer 72 into a single search segment. These segments are then the smallest elements of horizontal resolution used in the system to determine the actual line position or Position.

Each search segment of analyzer 72 becomes a top / bottom detector 74 supplied, where the individual segments are analyzed for vertical video patterns, which the location of potential Represent lines within each respective segment. The output of the detector 74 is thus an up / down signal pattern, which represent the relative position of the upper ends and lower ends (bottoms) of the potential rows, within each of the search segments collected by analyzer 72. These up / down signals become one Segment connecting device 76 supplied, which has the puncture to determine whether the top / bottom information from consecutive Vision segments belong to the same line of character patterns on the document 10. Signals which connection lines from adjacent viewing segments, and the top / bottom polarization signals from detector 74 are a line trace microprocessor 78 is supplied. The microprocessor

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78 evaluates the various potential lines of the character patterns in order to permanently distribute which of the strip memory 48 to be gated into the line block memory 50. The microprocessor 78 also serves to determine which of the retained Lines in the line block memory 50 is to be read, and it also calculates the above-mentioned parameters of the video data, the window selection and format device 54 and were then transferred to the reading electronics 58. Further line trace microprocessor 78 performs an accountant function to determine in which storage elements they are Parts of the data lines are arranged in the memory 50. The signals generated by the microprocessor 78 are by means of the channels

79 coupled to the extraction register 52, the line block memory controller 50, the window selection and formatting device 54 and the N _o mialisator 60th

The video capture system of Figure 2 provides a two-line reading system although any number of spaced lines on document 10 are identified can and is selectable for delivery to a character recognition unit. An example of a two-line reading process with the system of FIG. 2 is shown in FIG. 3 where document 10 consists of three spaced lines from one has identifiable character patterns in an arrangement 20.

As shown, the document 10 has already moved past the scanning module 16, with the scanning column 80 being video data located on channel 46 for delivery to stripe memory 48 and search correlators 68. The video data of the sample column 80 are entered into the strip memory 48 which, in the example, already contains video data from the sample columns contained within area 82, stores. At the output of the strip memory 48 there is video data from the sample column 84 passed through extraction register 52 into the line block memory 50 (gated).

The line block memory controller 50 is, as already mentioned, a random memory with individually addressable

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Storage elements for holding a block of video data derived from the spaced lines of document 10 where each block of video data was taken from one line and from multiple scans by the photodiode array 30 exists. Each storage element of line block memory 50 stores the video data as it is from one of the blocks in array 20 on document 10 of the pig. 3 have been removed. Selected blocks of video data identified on the document 10 for storage in an element of the block memory 50 are separated by a the reference numerals 86 through 95 for the purposes of the present description. The portion of sample column 84 that is currently being written into a memory element (identified by No. 87) of the line block memory 50 is indicated by the Reference numeral 86 represents. At the same time, parts of the same sample 84 will be in elements 86 and 95 of the line block memory 50 enrolled. The portion of scan 84 identified by reference numeral 98 is stored in the storage element 86 and the portion of scan 84 identified by reference numeral 100 is written into the storage element 95 registered. Other video data within blocks 86, 87 and 95 are already in the numbered elements of the random memory of the block memory control device 50 is stored. Each storage element of memory 50 is loaded with video data on a scan-by-scan basis.

All of the blocks illustrated on document 10 of FIG. 3 represent video data previously stored in block memory 50. Each block represents in a special element data stored in the random memory. Blocks 93, 94 and 95 illustrate areas of video data that are captured and are stored in block memory 50; However, these data blocks are not gated out of the block memory 50, because the line track microprocessor 78 determines when evaluating the video data within these blocks that it is not sufficient much information is contained within these blocks in order to

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to be identified as a line of character patterns.

Although the presently described system is a two-line reading system, there are three spaced lines of character patterns simultaneously in the line block memory control device 50, thereby enabling the system to compensate for any errors made in the capture the video data as represented by blocks 93, 94 and 95 was made. If only two lines of Data is retained, then the video data in blocks 87, 88, 89 would have been lost, as in the case of the video data to the right of block 90.

After processing the procedure corresponding to the document 10 video data taken from the system according to the invention, lines 102 and 104 are taken from line block memory 50 read out after the entire document 10 has been scanned and all parameters of the data have been determined.

To determine the parameters of the video data within the blocks of the document 10 as shown in Fig. 3 and stored In the storage elements of the Bloek store 50, video data on channel 46 is initially sent to the search correlators 68 which include logic elements as shown in FIG. Serial video cell data from analog / digital converter 44 are input to a four-sample delay register 106 via channel 46 and at the same time to the input of one Subtractor 108 applied. Delayed data from register 106 is simultaneously sent to a five sample delay register 110 and an (X9) multiplier 112 is applied. An output of the five sample delay register 110 is applied to a second input of the subtracter 108.

An output from the subtracter 108 is applied to an adder 114 which is an output to a one-sample delay register 116 is generated, which is in a feedback loop is connected to a second input of the adder 114.

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An output from adder 114 is also applied to an adder 118, which has a fixed "offset" signal a channel 120 receives. An output from adder 118 is present at a matching device (comparator) 122, the second signal to the comparator from the output of the (X9) multiplier 112 is coming. An output of the comparator 122 is a signal which is either black or white State for a specific cell of the arrangement 30 indicates.

To make a black and white decision for each cell in array 30, the sum of nine consecutive samples of each cell is used to determine whether the middle cell of the sum should be called black or white. This sum is referred to as the "row sum". If C represents the value of cell C during scan η, then C ₁ - then black if

n + 9
9C _{n + 5} > Σ C _± +10, where C _{n + 5 is} the center cell.

If this criterion for a black decision is not present for cell C ^, then this cell is determined to be white.

According to the above algorithm, if a cell is slightly darker than the average value of that cell for four samples or samples on either side of the cell under observation, that cell is determined to be black. The constant 10, applied to channel 120, provides the offset in the example above.

To obtain the center cell and the cells required to obtain the row total, data from the under observation located cell to the four-sample delay register 106 and then applied to the five sample delay register 110. The row total associated with each middle cell is updated at every sampling time

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(updated) by first subtracting in the subtraction logic 108 the value of the oldest cell C _n (this value appears at the output of the sampling delay register 110) from the value of the newest cell Cg, where C »is the value of the cell data, which are applied to the sample delay register 106 and the second input of the subtracter 108. The difference between the two input quantities at subtracter 108 is equal to the value of the video data in cell C _Q minus the value of the video data in cell C. This difference is applied to adder 114, which is added to the previous row sum as it appears at the output of one-sample delay register 116. Mathematically, the output of adder 114 can be expressed as follows:

η + 9 n + 8 New line total = £ C = ^ j C. + (C - C)

i = n + 1 i = n

This procedure brings the row sum for each cell on a basic scan for "update" scan.

The update value of the line sum is then added to a fixed ¹¹ offset "value in the adding logic 118, the offset value appearing on channel 120. The summation of the new line total with the added offset value is then compared in the comparator 122 with of the center cell multiplied by 9, ie 9C _{Q +} C. The value of the video data for the center cell C ~ is obtained at the output of the four-sample delay register 106 and is applied to the multiplier 112. The center cell value is multiplied by 9 in the multiplier 112 by to generate the second input variable for the comparator 122. Compare FIG.

If the center cell's value times 9.9C ^ j-, is greater than

n + p

the line sum plus "offset" at the output of adder 118, so the resulting black and white decision is for that

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Middle cell C, - black. If the output at multiplier 112 is less than the output of adder 118, then this criterion is not met and the center _cell becomes C IC

n + 5

determined as white. Using the search correlator logic of FIG. 4, a decision is made for each cell in a The document 10 is scanned for each scan time.

Referring to Fig. 5, black and white data appear from the output the correlators 68 on channel 70 and are applied to search analyzer 72. Search analyzer 72 compresses all black and white data in each of a plurality of adjacent samples from the search correlators into a single search segment of black and white data. According to an exemplary embodiment of the invention, the visual analyzer compresses every second sample of the 64 search samples into a single search segment.

The black and white cell data are used to achieve this compression at the output of the comparator 122 of the correlator 68 simultaneously to an input of a sample delay register (a shift register) and one input of an AND gate 126 created. The sample delay register 124 generates a delay of one sample time to generate an output, which is connected to the second input of the AND gate 126. Accordingly, the black and white cell data is obtained from the search correlator 68 processed with the corresponding cell data of the previous scan in AND gate 126. If the The value of the incoming cell data and the value of the corresponding cell of the previous scan are both black Are data, the output of AND gate 126 is at a black data level and the cell under consideration is considered black for the entire search segment.

The logic decision at the output of AND gate 126 is on an OR gate 128 is applied to be supplied to a sample delay register 130 (a shift register). An output of the shift register 130 is at an input of a selection gate 132, which has a second preset

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Input that is preset to the white logic level. One output from the selector 132 is sent to the second Input of the OR gate 128 applied. Accordingly, by OR gate 128 present black level data from gate 126 with any previous black level data from Select gate 132 subjected to a logical OR operation such that once a black decision for any cell was received, it is retained in delay register 130 for the entire search segment.

At the beginning of each search segment, for example the first scan out of 64 consecutive scans, the accumulated Black and white data in delay register 130 from the previous segment compilation or collection to a segment storage register 134 is supplied via a selection gate (selector gate) 136. During this transfer process, the Select gate 132 from sample delay 130 to the second input to generate a white level signal for the OR gate 128, whereby incoming video data (new search segment) is applied to AND gate 126 from the data (previous search segment) which latter are transferred to the shift register 134.

Upon completion of the transfer of the search segment data from the delay register The selection gate 136 transfers 132 into the shift register 134 to the second input for this on line 138 for connecting the vertically adjacent section of a search segment to the section of the search segment in register 134. In this way, multiple segment memory shift registers, one for each search section, are serially connected to each other, to enable the data stored in each such shift register 134 to be linked together and along output line 140 into the top / bottom detector be postponed.

From the above description it can be seen that the logic circuit of the Pig. 5 is duplicated several times to the data compression

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or compression in a time frame for the total number of cells in a sample. The cells a scan are separated into search sections which are connected or gated in series through shift registers 134 to line 140 will.

Figure 6 shows the effect of the search analyzer of Figure 5 in compressing data from 64 search samples into a single one Search segment 142, each sample comprising 64 cells. So that any cell in segment 142 is on a black Level must have two consecutive cell scans or cell samples used in the 32 search scans the 64 samples will be black. Accordingly, cell 144 does not create a black cell in search segment 142. Similarly cell 146 does not create a black cell in the search segment. In all other rows of cell data from the 32 search scans used where a black level signal appears, there are two consecutive such black level signals, creating a black cell in search segment 142.

Fig. 7 shows a logic diagram for the top / bottom detector 74, the results of the data compression at the end of each viewing segmenta from register 134 at the input of one Series / parallel shift register 148. The output signals from the Registers 148 represent nine vertically adjacent cells in the search segment. These output signals are sent to a Hur read only memory (ROM) 150 is applied, which the pattern of the black and white cell data from the shift register 148 in the upper or lower cell position decoded. In the read-only memory 150 becomes the pattern of black and white cell data in the register 148 is decoded according to the following truth table, Table I.

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1 2 5 3 O 1 Tabel (Bodeni 6th Cell position ) at I. for 9 Pattern for 1 1 1 1 Acceptable patterns 5 1 7th K O UP at K 1 1 1 1 BELOW 0 1 1 8th 1 1 1 1 4th 1 0 not interesting. 0 1 0 X 1 O O 1 1 0 0 0 1 X 1 1 0 1 1 1 1 1 X Cells 1 1 1 1 1 1 1 0 1 0 £ + 6 O 1 1 1 1 1 1 1 O K + 5 O 1 1 0 1 1 0 0 K + 4 vertical 1 0 0 1 1 K + 3 Schwärs 1 0 X K + 2 White 0 K + 1 K K-1 V - 1 - 0 = X =

To decode the pattern of the top / white cell data in the read-only memory 150, a controller scans (Controller) 152 samples the data in read-only memory to determine the bottom position of potential lines in register 148 determine. The controller 152 allows a search for patterns in the read-only memory 150, and if the first Ground position or position is determined, an input variable is applied to the control device 152 in order to generate a load signal along a line 156 for a ground position storage register 158. This loading signal gives that Register 158 is free for storing a vertical address which is generated along a channel 160 by a vertical address counter 162 Will be received. Accordingly, the address of a floor position for a potential line in the memory register 158 is Strip memory 48 is stored.

After this first floor address is entered or loaded into register 158, the controller then issues a

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Search for the top of the line of read-only memory free, with any additional "bottoms" detected be ignored. If a high end is determined according to the truth table of Table I, then generated the controller 152 sends a load signal on a line for a top position storage register 166. The load signal gives the vertical address of the top of the line for the Attachment to register 166 free, via a channel 168 from vertical address counter 162.

The operation of the entire system is sequential accordingly arranged in a series of clock pulses. After loading a floor vertical address in register 158 and a The upper vertical address in register 166 is supplied with this data to the segment connection device 76 and the control device 152 is actuated again to start a search for the next floor (the lower end) of a potential row initiate in memory 150. In this way, the bottom vertical position and the top vertical position become each identified potential line in read-only memory 150 for generating a vertical address in the storage registers 158 and 166. The vertical address counter 162 generates the position of the determined upper ends and lower ends (bottoms).

After all the data shifted into register 148 have been evaluated for the upper and lower line positions, the counter becomes 162 deferred as the next segment data is being shifted into register 148 and read-only memory 150. Of the Vertical address counter 162 is incremented by one address position each time data is transferred from a cell to the Register 148 can be moved. In this way, the output of the vertical address counter 162 is representative of the position of any cell in read-only memory 150 analyzed.

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As another operation of the controller 152, a count of the number of top / bottom pairs loaded into registers 158 and 166 is made. The control device 152 continues to operate in the manner described until the maximum number of top / bottom pairs (typically 5 top / bottom pairs) has been counted or until all input data for a given search segment has been analyzed by register 134. To determine the latter state, ie the state where all input data for a given search segment have been analyzed, the output of the YeL tical address counter 162 is applied to a vertical address counter register 170. Register 170 generates a signal on line 172 which is applied to controller 152 when the vertical address of counter 162 represents the maximum height of the search segment. When the control device 152 is operated sequentially to the maximum number of possible top / bottom pairs in the segment, or a signal is generated by the register 170, one end of the segment signal is generated on a line 154 which is sent to the logic of the segment connection device 76 is applied to identify that all of the top / bottom data from a particular search segment has been returned from registers 158 and 166.

Referring to FIG. 8, the vertical address data for the upper and lower ends of potential lines of patterns become as shown in FIG the registers 158 and 166 are input to the control electronics 176 of the segment connection device 76. The input data applied to the control electronics 176 is stored in a segment N-line storage register via a channel 178 180 entered. Each time the top / bottom address data for an identifiable line goes to the storage register 180 are transmitted, an address counter 180-1 is incremented by one address. The next Top / Bottom data is then entered towards the new address and this operation continues until all of the Top / bottom data pairs for a search segment are entered in the storage register 180. When the next vertically

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2G5G354

adjacent search segment is entered into electronics 176, the data stored in register 180 become one Segment N-1 storage register 182 transferred on Address location identified by incrementing a counter 182-1. Similarly, every time the electronics 176 receive top / bottom address data for the next vertically adjacent search segment, data in the register 182 is transferred to a segment N-2 storage register 184.

For each transfer of address data to the registers 180, 182 and 184 an enable signal for a comparison stage or a comparator 186 is generated, which between the Register receives data transferred and also transfers data from register 184 via channels 188, 190 and 192, respectively; see. particularly FIG. 8. Comparator 186 responds to the top / bottom address data from storage registers 180,182 and 184 and makes tolerance comparisons between the address data to generate a rating signal on a channel 194 to line assignment electronics 196.

Line allocation electronics 196 are responsive to the enable signal and generate line numbers applied to the storage registers 180, 182 and 184.

Each of the three storage registers 180, 182 and 184 consists of a random memory (RAM) with a six-word storage capacity for five top / bottom data pairs and an "end of the Segments "data word. Each word of memory contains a 9-bit bottom, a 9-bit top, and a 4-bit line number bit. The register 180 is addressed by a counter which receives a signal to select the next available memory word location generated for incoming data. Registers 182 and 184 are addressed by a single counter, the Counters for registers 180, 182 and 184 can be reset by control electronics 176.

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Each line number signal generated by line allocation electronics 196 is assigned to the corresponding word address of the Storage registers 180, 182 and 184 stored. The line allocation electronics 196 receive the line number output as input from registers 180, 182 and 184 for comparison purposes to generate a new line number signal.

Output data from storage register 184 including top / bottom address data and line number address data is supplied to an output format device 198 which the supplied input data converts into height / floor / line address data and generates output variables that match the data to the line trace microprocessor 78 are related. The format device 198 is enabled by a signal from the control electronics 176 and generates a "complete puncture" signal on line 200 for electronics 176.

Pig. 9 shows a flow chart of the control electronics I76 as Part of the block diagram of the Pig. 8. The electronic control unit 176 works in ten stages, which are sequentially ordered the segment storage registers 180, 182 and 184, the comparator electronics 186, line allocation electronics 196, and output format device 198. During the state "O" is the control electronics 176 at the start of the document 10 reset. The segment counter is also loaded to a count of two and the address counters 180-1 (AD1) and 182-1 (AD2) (see Pig. 10) are cleared to zero in step 554. The control device then advances to state "1".

In the "1" state, the control electronics 176 are in a standby state for the next operation initiated by the controller when it has a top / bottom address data available signal or one end of the data signal or one end of the segment signal from the top / bottom detector 74 receives. State "1" comprises inquiries 556, 558 and 560, which continuously circulate until one of the three above mentioned signals is input to the control electronics 176.

709824 / 08Ai

- a

Depending on the received signal, the control electronics either proceed to state "2", state "2A" or state "8". The state "2" is entered when the control device (controller) the top / bottom address data available signal receives. The control device advances to a state "2A" on receipt of an end of the segment signal continue and advances to state "8" when an end of the data signal is received.

When the controller advances to state "2", the sequence advances to step 562, during which Address data are read out from the top / bottom detector 74 and entered into segment memory 180. A top / bottom data pair and a zero line number are read during the step and into the currently addressed memory word element of the storage register 180 during a step 564. The address counter 180-1 becomes the address of the next storage element further during one processing step 566 increments. After incrementing or advancing the address counter 180-1, the Control electronics 176 return to state "1", and if another top / bottom data pair is available, the Follow again to state "2". Another top / bottom pair of data is stored in storage register 180 along with a Zero line number entered at the current address position or location. The address counter 180-1 is again during Step 566 advances and the sequence returns to state "1".

The above sequence continues until an "end of segment" signal from the control electronics is in the "1" state is received, at which time the sequence advances from query 558 to state "2A". In this state will a all zeros word is loaded from top / bottom detector 74 in step 568 and into the segment storage register 180 during step 570 at the current address of counter 180-1. The end

70982 4 / 08AA

2G5685A

all zeros are written into the memory register 180 Word is used by comparator electronics 186 and output formatter 198 as an end of the data indicator used for a search segment.

Subsequent to step 570, state "2A" advances to query to determine if the last data entry to storage register 180 was from the first search segment is collected from data read from document 10. If the last segment entry to storage register 180 is the first search segment is then the control electronics sequence proceeds to state "7". Otherwise, query 572 switches the Follow the control electronics 176 to state "3".

The state "3" of the control electronics 176 is the normal comparator state, where comparator electronics 186 are enabled during step 574. During step 574 is the regeneration (recycle) mode signal on line 234 (pig. 8) zero and the upper recovery mode signal on line 236 is also zero. The address counters 180-1 (AD1) and 182-1 (AD2) are also reset to zero. In the "3" state, the control electronics 176 run through cycles until the comparator operation (comparison process) is complete is the time at which query 5 76 advances the sequence to query 578. The comparison mode is enabled by an "enable" signal on line 220.

From query 578, the sequence advances to either state "4" or state "5". The sequence proceeds to state "4" then, if the last received search segment (S 4-1) is not the second search segment collected from data taken from the document 10. If the last search segment input (S = 1) in the segment connection device 76 is the second segment taken from document 10, then the sequence advances to state "5".

7098? 4 / 08AA

Ιζ

When the sequential step to state "4" is done is a regeneration or recycle operating signal on line 234 to enable the comparator electronics 186 in a regenerate mode of operation. The address counters 180-1 (AD1) and 182-1 (AD2) are also reset to zero and the high recovery mode signal on line 236 is zero. the Controller remains in state "4" until an inquiry indicates that the comparator operation is complete. The consequence then advances to state "5".

State "5" is entered from either state "3" or state "4", and this is the upper address comparison state. In the "5" state, the comparator electronics 186 are enabled in the upper mode by an upper recovery mode signal generated on line 236 and applied to select gates and 206 (see FIG. 10). The address counters 180-1 and 182-1 are reset to zero and the regeneration mode signal is also zero. The comparator is enabled in a step 584 and continues to operate until an inquiry 586 produces a result indicating that the upper comparator recovery mode is complete, whereby state "5" advances to an inquiry 588. If the last input segment to the segment connecting device 76 is the first search segment (S = 1) taken from the document 10, the control electronics sequence advances to the state "7". If the last input segment is not the first search segment (S Φ 1), the next state for the control electronics is state "6".

In the state "6 ^M , the data on the search segment in the memory register 184 are output to the line trace microprocessor 78. Initially, in the state" 6 ", the output format electronics 198 are enabled in a step 590. The electronic control device remains in the state" 6 "until a request 592 indicates that the data transmission to the line trace micro-

70982 4/0844

processor 78 is complete.

After the data transfer has been completed by the output format electronics 198, as indicated by the control electronics by a signal on line 200, the sequence proceeds control electronics 176 to state "7" at a stage 594 Further. The state "2A" is also entered in stage 594 and entered from state "5". During the "7" state, address data are stored between the segment memory registers 180, 182 and 184 moved. All the address data for the top, bottom (bottom) and line position or space for each potential Line of a segment is shifted between the storage registers. For example, the address data for a search segment written in the memory register 180 into the memory register 182 and the preceding search segment address data, which were previously stored in register 182 are written into storage register 184. When the shift the address data between the registers is complete, then the control electronics sequence is advanced to the state "1" by inquiry 596.

When an "end of data" signal by the control electronics if it is in the "1" state, the sequence advances to the "8" state. In this state, the top, bottom and line position address data of the next search segment to the line trace microprocessor 78 via the output format device 198 delivered. The output format device 198 is enabled by a signal during step 598. The control device (controller) holds the format device 198 in the release state until a complete signal is received on line 200. This provides for a positive response to query 600 and the status "8" proceeds to step 602. In step 602, the top, bottom, and line position address data for the Search segment in memory register 182 is transferred to memory register 184. Upon completion of the shift of the Data during step 602, inquiry 604 advances to subsequent state "9". When the status "8" is completed

709824/0844

- ie Yf

only storage register 184 contains upper, lower, and row address data of a search segment.

In state "9", step 606 enables output format device 198 to transfer the top, bottom, and line address data of the last search segment collected from data from document 10 to line trace microprocessor 78. Upon completion of step 606, as indicated by a positive If the response to query 608 is indicated, control electronics 176 returns to state ¹¹ 0 ″. Segment connection device 76 now awaits the forwarding of additional search segment data for the next document from top / bottom detector 74.

Pig. 10 shows a detailed logic diagram of the comparator electronics 186 including the storage registers 180, 182 and 184. As mentioned, the storage register 180 has an address counter 180-1, which is indicated by the output an AND gate 180-2 coupled to an OR gate 180-3. The storage registers 182 and 184 become driven by an address counter 182-1 which is incremented by the output of an AND gate 182-2, the latter having an input connected to an OR gate 182-3.

The comparator electronics receive the upper / lower address data from register 180 on an upper / lower select gate 202 and the upper / lower address data from registers 182 and 184 at a segment selector gate 204. Segment address data selected by the gate 204 are an upper / lower selection gate 206 at the same level as the selector gate 202 supplied. Selected address data from gate 202 is coupled to a counter 208 and data selected from the select gate 206 are fed to a counter 210. Output data from counters 208 and 210 are fed into a comparison device (Comparator) 212 is entered.

709824/0844

The comparator 212 generates three output signals: One (210> 208) connected to counter 208, a second (208> 210) connected to counter 210 and a third (210 = 2.08) connected to one input of an AND gate 214. An output of the AND gate 214 is to a flip-flop latch tied together. Address data is loaded into counters 208 and 210 in response to the comparator enable signal to a control counter 218, received on line 220 from control electronics 176 during states "3", "4" and "5". A load signal from control counter 218 is also applied to tolerance counter 222, which records tolerance data a channel 224 receives. The output of the tolerance counter 222 is passed through an inverter 226 to a second input of the AND gate 214 coupled, the latter being coupled to the locking device 216. Also one A flip-flop interlock forms part of the comparator electronics 228 for generating data signals for the OR gates 180-3 and 182-3. The flip-flop 288 is generated by the output of a AND gate 230 is activated. Reset signals for the two flip-flops 226 and 228 are transmitted via a line 232 from the Line assignment electronics 196 supplied.

Initially, on receipt of the address data for the first search segment collected from line data on the document 10, the control electronics generate 176 a signal to clear memory registers 180, 182 and 184. The comparator enable signal on line 220 is also generated for the control counter 218, with additional Signals are generated by electronics 176 including a "recycle" operating signal on a Line 234 during state "4" for select gate 204 and an up recovery mode signal on one Line 236 during the "5" state for selector or selection gates 202 and 204.

The release of the taxpayer 218 sets this counter up Back to zero and then allows the counter reading to increase with a clock rate or clock frequency. Typically that is

709824 / 08ΛΛ

- eat -

Counter 218 is a 0-15 roll-over counter which is used to operate the comparator electronics 186 in a sequential order. This counter generates three signals; Count 1 (Cc = I) loads comparator 212 with the upper or lower address data from storage registers 180 and counters 208 and 210 (182 or 184) via counters 208 and 210 as selected by select gates 202, 204 and 206; Count 2 (cc = 2) is applied to AND gate 230 in order to control the selection of the next upper / lower address data pair to be compared, namely by generating at the output of flip-flop 228 the signal ¹ next- N or next-N. The next-N signal is applied to OR gate 180-3 and the next-N signal is applied to OR gate 182-3. The third signal generated by control counter 218 is a count 15 (ce = 15) signal used to control address counters 180-1 and 182-1 by connecting respective AND gates 180-2 and 182-2. The counter reading 15 signal is also applied to the flip-flop latch 216.

When the control counter 218 counts zero, the counter registers have 180-1 and 182-1 Access to a special top / bottom address data pair of the most recently passed search segment (N) in storage register 180 and a preceding search segment (N-1) or (N-2) in storage registers 182 or 184. The selected top / bottom address data pair is passed through select gates 202, 204 and 206 for the Availability at the inputs of the comparator 212 by the Counters 208 and 210. When the count is 1 (Cc = I), counters 208 and 210 are with address data from selection gates 202 and 206 and also the tolerance counter 222, which is typically a set of binary switches, is loaded with a tolerance level Loaded via channel 224.

The tolerance counter 222 counts after its loading from a preset value back to zero, namely with the Clock rate of the counter 218. The tolerance counter generates a

709824/0844

HP

Connection release signal (connection release signal or "link release signal") at the output of inverter 226 to the system at one input of AND gate 214. The connection enable signal generates a time frame (frame) beginning with generation of the control counter reading 1 and ending when the tolerance counter 222 counts from zero to the tolerance level.

In operation of the comparator 212, one of three signals generated, each upper or lower during the comparison Address data pair from two search segments. The three signals are as follows:

1. Counter 210 is at a higher count level or level than counter 208;

2. Counter 208 is at a count level greater than counter 210; and

3. The count level of counters 208 and 210 is the same.

The two "greater than" signals are used to set the counter with the lowest count level for each clock pulse from the control counter 218. Venn thus the meter reading level of the counter 210 is greater than the level of the counter 208, the comparator 212 generates a signal for Incrementing or advancing the counter 208. When the count level of the counter 208 is greater than the level of the counter 210, then the comparator 212 generates a signal for advancing the counter 210.

If the count level of each of the counters 208 and 210 is the same, the third signal is generated, which is applied to one input of the AND gate 214, the second input variable of which comes from the tolerance counter 222 via the inverter. The output of AND gate 214 switches flip-flop latch 216 during the time frame generated by counter 222 to generate an ⁿ terminal segment ^N signal on line 194 applied to line assignment electronics 196 or OR gates 180-3 and 182 -3, which indicates that there is a row connection between the cells-

709824/0844

data of a search segment and the corresponding cell data from a previous search segment. The connection signal to the OR gates 180-3 and 182-3 increments the counters 180-1 and 182-1 to select the next upper or lower address data for line extension evaluation.

When the comparator 212 has a signal other than the "counter equals" signal (3) generated, indicating that a segment connection is not present, during the tolerance counter time frame, so the next upper or lower address data pair which is to be transmitted to the comparator 212, is selected by the generation of an increment signal "A" at AND gate 230, with the selection of the next upper or lower address data pair is controlled by the address counters 180-1 and 182-1.

The counters 180-1 and 182-1 are individually advanced or incremented, depending on the status of the previous one Comparison. The counter 180-1 is applied to the control counter 218 when the counter reading 15 (cc => 15) signal is generated Gate 180-2 increments when the terminal segment signal by latch 216 or the next-N signal from of lock 228 was generated. As already mentioned, the connection segment signal is generated when the comparator 212 detects a comparison between counters 208 and 210 and the two upper / lower address data pairs in the corresponding Counters are within a connection tolerance, such as this by counting down the tolerance counter is determined.

The next-N signal is at the output of the flip-plop latch 228 is generated when the upper or lower location (position) of a search segment is in either the storage register 182 or 184 is above the upper or lower position of the next most recent search segment (H), which is in the memory register 180 was entered. The next-N signal is also generated when the most recent search segment (N) is introduced

70982A / 0844

-35 -

in the memory register 180, has already been assigned a line number which is indicated by the line 1 ^ 0 signal generated on line 232 by row allocation electronics 196.

To advance the address counter 182-1, the control counter 218 generate the count 15 (cc = 15) signal, and either the port segment or the next-N signal must for the OR gate 182-3. The connection segment signal is generated in the manner described, and the nextxe-H signal is generated at the output of the flip-flop latch 228. This signal is activated when the counter reading 15 signal occurs and when the comparator 212 does not generate an increment signal "A" to the AND gate 230 at the time when the control counter reading 2 (ce = 2) is generated.

During operation of the comparator electronics 186, the control electronics charges 176, as described, into the segment storage register 180 upper and lower data for each of the potential lines, which can be identified on the document 10. The top and bottom data for any row is put in an address space loaded and for each potential line the data is loaded into a separate word address the line allocation number for each word of memory register 180 is zero to indicate that the word is not yet a line number was assigned even though the line number was previously identified and stored in storage registers 182 and 184 can be. After completing states "2" and "2A", all of the top and bottom data for potential lines in the Register 180 stored with the last word containing all zeros to indicate the end of a search segment. the Control electronics 176 then proceeds to state "3".

As explained, in the state "3" the address counters 180-1 (AD1) and 182-1 (AD2) are reset to a zero address and the "Recycle" and upper operating mode signals are located at a zero level, with an enable signal on line 220

70982 /, / 0844

of the control counter 218 is applied. While the Control electronics in state "3" are the upper and lower Line data of one word is applied from the storage register 180 to the upper / lower selector 202, and the upper and lower data of a word in storage register 182 and 184 are applied to segment selector 204. When it is at zero level Recycle mode signal on line 234 conducts the voter 204 the upper and lower data from storage register 182 to upper / lower selector 206.

In state "3" is the upper recovery mode signal at the Nulluid level, voters 202 and 206 only leave the lower (bottom) data to the respective counters 208 and 210. This lower data is sent to the comparator 212 applied, the incrementing signals for the counter generated with the lowest floor space. The counter for the lowest floor space or lowest floor location is continuous switched on and the data compared in the comparator 212. If a comparison is made within the tolerance time frame established by the tolerance counter 222, then the latch 216 generates a connection signal on line 194, which indicates that the ground data is from storage registers 180 and 182, corresponding to the comparison in comparator 212 of FIG come from a potentially identifiable line.

The terminal signal on line 194 is sent to the OR gates 180-3 and 182-3 are applied to AND gates 180-2 and 182-2, respectively to adjust. The next time the count 15 (ec = 15) signal occurs AND gates 180-2 and 182-2 generate an increment signal to address counters 180-1 and 182-1, respectively. This increments the addresses to the next word address position of the storage registers 180, 182 and 184.

State "3" resumes recirculation with soil data for each address in storage registers 180 and 182 is compared in the comparator 212. As long as the comparison is achieved within the tolerance time frame, a connection signal is generated.

- yr-

If the comparison does not occur within the tolerance counter's time frame, the enable signal switches to the AND gate 214 the output of the comparator 212 from the latch 216 away. The next time the counter reading 15 signal occurs, the latch 228 is set to either the next-N signal or the next-N signal, and that is determined through the output of AND gate 230. A signal is generated at the output of AND gate 230 during the count 2 (cc = 2) signal generated when the output of the comparator Ulan shows that the soil data (lower data) in counter 208 is lower on document 10 than the soil data in counter 210. Venn if this occurs outside of the tolerance time frame, the indication is that the soil data in storage register 180 has no connection with the soil data compared from the storage register 182. The next-N signal is at the output of the latch 228 is generated and applied via the OR gate 180-3 to the AND gate 180-2 for incrementing the address counter 180-1. At this time the address counter 182-1 is not incremented and the next comparison is made with the bottom or lower data in different address locations or locations in storage registers 180 and 182.

If, at the end of the tolerance time frame, the location of the lower address in counter 210 is lower than the lower address in counter 208, then latch 228 generates the next-N signal jUa to advance the address counter 182-1 for the next comparison of the lower data.

After all lower address data in the registers

180 and 182 have been compared and, if possible, connected, the control electronics 176 proceeds to state ^M 4 "where the address counters 180-1 and 182-1 are again reset to zero. The upper recovery B mode signal also goes to zero is reset and the control counter 218 is enabled by a signal on line 220. The recycle mode signal on line is now at an enable level and during the

709824/0844

"Recycle" mode is the lower data from the memory register 184 is selected by the selection gate 204 to the upper / lower selector 206.

The state "4" of the control electronics 176 is a repetition of the state "3" with the exception that the lower address data of the storage register 180 are compared with the lower address data from the storage register 184. Again, everyone will potential row bottoms are compared to determine either a join condition or a no join condition.

Upon completion of state "4", the sequence of control electronics 176 advances to state "5" which is the upper recovery mode. As mentioned, the state “5” can also be entered from the state “3” if the search segment in the memory register 180 is the first to be taken from the document 10. For this condition, there would be no data in the storage register 184 for the comparison in the recycle mode and the state ^M 4 "would be bypassed.

When the state is "5", the address counters become 180-1 and 182-1 again reset to zero. The recycle mode signal for select gate 204 is zero and the upper recovery mode signal for select gates 204 and 204 206 enables these two gates and the control counter 218 is enabled by a signal on line 220. In the upper The retrieval mode receives upper address data from the segment memory 180 and the segment memory 182 by the Select gates 202 and 206, respectively, are transmitted to counters 208 and 210. During the operation of the control electronics in the "5" state the top addresses of potential lines in each word in storage registers 180 and 182 are compared for a connection condition. The follow-up condition is again determined by the tolerance counter 222. The same comparison of the above data is completed, as previously described, with respect to the comparison of lower data to generate connection signals on line 194 to be generated where a connection exists.

709824/0844

! 656854

The mode of operation of the comparator electronics 186 is continue until upper address data is found that are equal to zero. This condition occurs when the Data from storage register 180 indicate an upper address of zero (signal above 1 = 0 on line 238) or the data from Select gate 204 generate a signal (above 2 = 0) for the control electronics 176 on a line 238. When determining the practice = O address space switches the control electronics 176 the enable signal on line 220 only comparator electronics 186 from.

11 shows a logic diagram of row allocation electronics 196. Top / bottom address data of search segments from the storage register 180 are applied to a "zero" detector 240, and top / bottom address data from registers 182 and 184 are applied to a row select gate 242 which outputs data to a "Zero" detector 244 and a row select gate 246 provides. The "zero" detectors 240 and 244 comprise a logic one Circuit which responds to a zero line element in an address of the memory register.

Additional input variables for the line allocation electronics are the connection segment signal from the locking device 216 of the comparator electronics 186 applied to a delay line 248, a reset signal from the control electronics applied to a line counter 250 and a "Recycle" signal also from the control electronics 176, applied to the selection gate 242 Terminal segment signal is applied delayed by delay line 248 to delay line 252 and also connected to the input of an AND gate. A second input to AND gate 254 is the output of delay line 252, and a third input comes from "zero" detector 240. The output of "zero" detector 240 is also not equal via inverter amplifier 256 as a "line" applied. 0 "signal (line 1 Φ 0) to the comparator 186 on line 232.

709824/0844

An output from the AND gate 254 is applied to an AND gate 257, the output of which is connected to a line counter 250 is; a second input of the AND gate 254 is connected to the output of the zero detector 244. The exit of AND gate 254 is also on delay line 258.

Additional inputs for the line selector 246 are Address data from line counter 250 and a select counter signal from "zero" detector 244. Line select gate 246 generates one of the outputs of the row allocation electronics. The line number write data is applied to this output to storage registers 180, 182 and 184. A second output is generated by the line allocation electronics on delay line 258 and is the line number write enable signal for segment storage registers 180, 182 and 184.

Row allocation electronics 196 are activated by the terminal segment signal released by the comparator 186, namely during the states "3", "4" and "5" of the control electronics 176, which is expanded into a single clock pulse by the action of delay lines 248 and 252. The delayed Signals from delay lines 248 and 252, along with the output of detector 240, become an AND puncture subject. If the currently addressed top / bottom address data from storage register 180 does not already have a Character line are associated, the detector 240 receives a zero word from a current address of the Registers 180 and generates a line zero signal to AND gate 254 for further operation of the line allocation electronics. If the currently addressed top / bottom data with a sample line are associated, then detector 240 receives data from an assigned line number and generates that Zero line signal is not and the line allocation electronics are blocked before further operation. By the way it works of inverter 256, the output of detector 240 is applied to flip-flops 216 and 228 via line 232

7 Π s? 2 λ / o 8 4 4

and supplied to the comparator 186.

The recycle signal from control electronics 176 dials during the states "3", "4" and "5" to the line selector 242 the address of the current line number of the previous search segment (N-1) from storage register 182 or the second previous search segment (N-2) from storage register 184.

The selected number of lines at the output of the selection gate 242 is applied to the "zero" detector 244 and the line selection gate 246. If the selected number of lines from gate 242 is other than zero, as indicated by the output of "zero" detector 244 is displayed on line 260, select gate 246 derives the line number address from Select gate 242 as line number step data to segment storage register 180. When the one selected by gate 244 Line number address is zero, as indicated on line 260, then AND gate 257 generates an incremental signal for the line counter 250. The line counter 250 is incremented and the line selection gate 246 selects the new one Count from the line counter as the line number write data to the segment storage registers 180, 182 and 184.

One clock pulse later, generated at the output of AND gate 254, delay line 258 provides a line number write enable signal and the assigned number of lines from selection gate 246 is written into segment storage register 180, 182 or 184, depending on the recycle signal to the selection gate 242. At the end of the generation of line numbers for each document, a reset signal from control electronics 176 resets line counter 250 to zero.

Output data from the segment connection device 76, see FIG. 12, is generated at the output format device 198, which receives from storage register 184 upper / lower address data and a four-bit line number. The output format device 198 is controlled by the control electronics 176 during

709824/084 *

the states "6" and "8" and "9" are coupled on a line 262 enabled with AND gates 264 and 266. An exit from AND gate 266 is connected to line track device 78 via an inverter 268 and is also at an input an OR gate 270. A second input to the OR gate 270 is the data acceptance signal from the line tracker on line 272. An output of OR gate 270 is connected to a second input of AND gate 264 which an increment signal for an address counter 182-1 to segment storage register 184 is generated.

Line number address data from segment storage register 184 is applied to a "zero" detector 276 which has an output is at AND gate 266. The line number address data is also supplied to the line tracker 78. The "upper End of Line "address data from storage register 184 is sent to divider 278 and also to" zero "detector 280 created. The output from "zero" detector 280 is on AND gate 282 is applied, which also receives a Priierterabesignal from the control electronics 176. The output size of the AND gate 282 is a control signal for line track device 78.

With divider 278 is also the "bottom of the line" address data connected from storage register 184. This data is the address of the bottom (lower end) of an identifiable Line and are also applied to a divider 284. The two dividers 278 and 284 can be through a logic circuit be embodied, which omit a bit of the input word according to common logic operation. By means of the dividers 278 and 284 becomes every top / bottom row element in the segment storage register 184 brought into a floor / height / line address element in a new format (re-formatted). The row bottom data, as applied to divider 284 are re-formatted from a nine-bit number to an eight-bit r number, for conduction to line tracker 78. The line height data is stored in the subtracter / divider

70982A / 08U

SO

278 is calculated by subtracting the bottom line address data from the address data at the top of the line and dividing the total by 2. This information is also applied to line track device 78.

In Pig. 13 is a block diagram of the line trace microprocessor 78 including a microprocessor 286, typically manufactured by Motorola Inc. and identified as a Motorola.6800 microprocessor can be. The microprocessor 286 is coupled to the peripheral interface adapters (PIA) 288-292, each of which Provides interface electronic devices for inputting and receiving data from microprocessor 286. A processor memory 294 is also provided as part of the line tracking device 78, which has the possibility of a Random memory (RAM) and read-only memory (ROM). The individual blocks shown in FIG. 13 relate relate to the Motorola 6800 microprocessor and peripheral interface adapters. The processor memory 294 is available as a 1K random memory (RAM) for data storage and as 2K read-only memory shown for program storage.

Input data including floor / height address data bits from segment interconnect device 76 with associated interrupt signals, data availability signals, end of search signals, and end of containment data signals are connected to microprocessor 286 through peripheral interface adapter 288. The peripheral interface Adapter 289 connects the line block bottom address data to extraction registers 52 along with associated interrupt signals used by the extraction registers to transfer the next block of video bottom data for one line on document 10 from strip memory 48 with the line block memory control device 50. the peripheral interface adapter 291 passes parameters to the N _o rmalisiervorrichtung 60 from which

709824/0844

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on the line inclination, normalizing factors, reading window bottom data and obtain a video storage unit (VSU) number. The peripheral interface adapter 292 generates address data, which extend on line block bottoms to the reading window selection device 54.

In operation of the line trace microprocessor 78, input data controlled by interrupts from segment interconnect device 76, including a data availability interrupt, generates on line 174 which segment address data from the output of output format device 198 to the Enables reading by the peripheral interface adapter 288 for storage in the processor memory 294 in a current segment data area. There are up to five data breaks for each search segment (one for each identifiable line), including an "end of segment" break generated on line 172, which indicates that all of the address data for the current search segment has been entered and is in processor memory 294 are stored. Another interrupt to control the input of the search segment data from the segment connection device 76 includes an "end of enclosure" break indicating that all of the line address data for document 10 are entered in processor memory 294.

The output data from the microprocessor 78 is passed through two Interrupts controlled by line block memory controller 50. The first interruption is generated when the line block storage device 50 for receiving a new line block assignment from the write data control device is conditioned. When this interrupt occurs, the line trace microprocessor 78 generates output address data related to new video frame assignments in line block memory 50 and new block bottom parameters for the Extraction Register 52. The second interrupt which controls the output of the line trace microprocessor 78 then becomes generated when the line block memory controller 50

709624/084 *

2656S54

is done, the line block video data to the reading window selection format device 54 to direct. During this interruption, the line trace microprocessor 78 produces outputs of the Line block allocations for the line block memory controller 52 and new line block bottom data for the reading window selection format device 54.

As a result of an input interruption, address data becomes in word format with respect to that appearing on the document 10 Patterns stored in the random memory of processor memory 294 including ground, height, and Row address data inputs from the segment connection device 76. In particular, the data words are arranged in five sentences of three words each, with each of the three word sentences contains a bottom, height, and line segment address from segment linker 76. Two additional Data words are stored in the random memory (RAM), namely first to indicate the next memory element of the block memory 50 available for input data, and secondly to display the next data that is to be processed by the Microprocessor 286 are available. The last word of data in RAM is the "end of data" signal, which indicates that all Address data for a particular search segment is entered into processor memory 294.

Initially, the RAM does not contain any search segment data and two pointer addresses (X) and (XL) contain the address of the first available soil storage element. The "end of data" signal (EOD) is also reset to zero and the microprocessor executes a scheduler routine shown in FIG the end. The microprocessor 286 continues to execute this scheduler routine until a segment data interruption occurs at what time ground, elevation and line address data for each line of a search segment into memory 294 can be input from the segment connecting device 76. The address data relating to the bottom of a line pattern are stored in the memory location or location

7098? £ / OSU

stores that "or that has the address that is in the first Pointer (X) is included. The address data relating to the line height are stored in a memory location, after saving the address data relating to the bottom of the line. The ones related to the number of lines Address data are stored in the next storage location following the storage of the data height. The first Pointer (X) is then updated to an address for the next available memory element for receiving the next line pattern floor, height and line address data. The microprocessor goes into the scheduler loop of Fig. 14 is returned at the point of interruption when all available line data is from the segment interconnect device 76 are entered.

When the microprocessor 286 is through the Pig. 14 runs, he proceeds to query 296, and there the first Pointer (X) is not equal to the second pointer (XL) after data is entered into the microprocessor, the operation proceeds of microprocessor 286 to subroutine 298. Microprocessor 286 executes subroutine 298, where it is a line trace on the most recent ground, height and line address data from the segment linker 76 acts. During the line trace subroutine, the second pointer (XL) is updated to to contain an address above the previously processed line, upon completion of the line trace subroutine the microprocessor 286 returns to the scheduler loop at request 296.

Pig. 15 shows a flow diagram of the line trace subroutine 298, which includes the operation of the microprocessor 286, namely in connection with the processor memory 294 for controlling the collection of the video data in the line block memory 50 and to perform the necessary intervening line parameter calculations. The memory areas of the processor memory 294 are calculation tables for the top of the line,

7 fi π: ■ '·· /, - Π P. /, Ii

2656354

Height and Line Address, the Line Block Storage Element Distribution Table and the row block storage element allocation table.

This subroutine is requested when the scheduler routine 14 is responsive to a "no" input to query 296 (pointer (X) is not the same as pointer (XL)). The routine of FIG. 15 makes entries into processor memory 294 for each data word of a search segment in the Memory 294 row allocation and calculation tables.

In carrying out the Zeil ens pur ine Subrout Fig. 15 Wix ⁱ d, the address of a row calculation table from the immediately occurring number of lines derived. There are a fixed number of line calculation tables, one for each possible number of lines which is assignable by the segment connection device 76, and each line calculation table contains the parameters for a line of characters. These parameters include the X coordinate of the start of a line assignment and the X coordinate of the end of a line assignment.

Start /, after starting subroutine 298 at step 303, where the address of the line calculation table is determined from the input data line number (XL + 2), the address becomes a Line element in a query 304 to determine if the data is the first element of a sample line. Every Row calculation table contains the parameters for a row, including (X-START), the X coordinate of a Beginning of line and (X-STOP), the X coordinate of the end of a line. Where the address details are the first for a possible Line are, the microprocessor 2So tries to identify the data with the search segment which is immediately precedes the search segment under investigation. .This information from the previous segment that contains the data advance for a possible line, bulk in line block memory 50 can be collected as explained below will.

7 ρ:> ■■■ "MlU

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When a new line of data is identified (X-START [L] = O), query 304 transports the line trace subroutine to the Step 306 where the X coordinate is decremented and through Step 308 where the current coordinate (XC) is now equal to (XC-1), Dispatch subroutine 310. The Dispatch subroutine operates for the purpose of allocating address data for memory elements of line block memory 50 for one anticipated line start block of video data in processor memory 294. Upon completion of the assigned subroutine, line trace processing proceeds to step 312 where the current X coordinate is incremented to XG = XC + 1 and then to an allocated line block memory subroutine 314. The line block allocation subroutine 314 then collects address data the storage elements of the line block memory 50 for storage in the processor memory 294 and all lines of the current search segment.

If a line of the current search segment is not a line start (X-START Φ 0), then query 304 switches the subroutine of FIG. 15 to query 316 where a test is performed (X-START = XG-2) determine whether gaps occur between the character patterns of a line, such as between video data blocks 86 and 89. Gaps occur in a line as a result of the recycle mode connection by the segment connection device 76. If a gap actually occurs in a line of video data, such a gap must be accumulated in the line block memory 50. This is accomplished by decrementing the current X coordinate of the address of a memory element in step 308 (XC = XG-1) and calling the line block allocation subroutine 310 as explained above. The subroutine of the Pig. 15 again advances to step 312 and the allocation line block store subroutine 314.

If a video data block of a line in a current search segment is neither a line start (X-START Φ θ) nor one

7D ^:? 4/0 8 £ A

Sip

Gap in a line of data (X-START = XC - 2) indicates then the line address data is checked for multiple lines of data in the same search segment. Multiple lines of data are a problem that arises when the segment connection device 76 has two cells of a search segment with one cell of the previous search segment. The multi-cell problem is compounded by a negative response to query 316 sought what brings the subroutine to query 318. If there are more cells in a search segment, only the lowest cell of the search segment is allocated to line block memory 50. Multiple cells are detected when the current X coordinate of the address of a memory element is the same as the coordinate of the end of the line (X-STOP = XC).

Purely data cells in a search segment that do not start that column are in required lines or multiple cells, the line block allocation memory subroutine runs 314- for collecting address data for the current data cells of the search segment. The final function of the line trace subroutine of Figure 15 is to update the intermediate Line parameter calculations used by the line selection processor to perform line skew, normalization and calculate the window floor parameters. This updating is carried out by the subroutine of FIG which proceeds through step 320 where X-STOP = XC is made by subroutine 314 for the "update" - (Update) Partial Totals "subroutine 322, where the actual updating of the data he follows. After subroutine 322, the subroutine of FIG. 15 is activated by microprocessor 286 by performing the Step 324 completed.

Line block memory allocation subroutines 310 and 314 have Line block storage elements (storage areas in the line block storage 50) three data cells of the search segment. The subroutine uses a running X coordinate for selection a nine-word block of the line block memory allocation

70982 /./ 0844

- se -

Memory of the proceasors memory 294. The nine word block contains three word sets, each of which consists of a bottom word, a line number word and a memory element number word. The line block allocation subroutines scan these word sets for an empty line block element of memory 50, which indicated by a null line code. If an empty row block storage element is found, the next available Line block storage element taken from the line block availability list and in the line block number of the slot (the empty parts) saved. Next, the current soil data and line number data are stored in the selected block.

Occasionally, all of the available line storage elements of memory 50 are assigned address data, and in this case the storage elements are reassigned. If the address of the ground data of the current search segment is less than the address of the highest allocated floor word, this memory element becomes the new line element assigned. This reassignment is accomplished by overlaying the new ground data and line number data over the previous one saves saved data. There is an important timing consideration in allocating the line block memory elements that the line block memory allocation table must be stable before the line block memory controller 50 generates the interrupt to generate the extraction of the parameters.

After all the line pattern data from the segment connecting device 76 are stored in processor memory 294, the "end of segment" interrupt occurs and the microprocessor 286 proceeds to query 300 with the scheduler routine. It should be noted that the scheduler routine does the Circulation continues until all data is received from the segment connection device 76 line traced (set in terms of line) before the "end of data" break occurs at what time the microprocessor 286

70 9-8 24/0844

SZ

advances to subroutine 302. This subroutine allows the first and second pointers to be reset Floor address "1". At this time, the "end of data" signal (EOD) is also reset to "full", and all while completing the "end of segment" subroutine 302

An important feature of the operation of microprocessor 286 while entering data into processor memory is that the incoming data is entered during an interrupt routine, but processed in the background will. This allows the microprocessor 286 to respond immediately to output interrupts. That that is, when additional data is processed for the reading electronics 58, the microprocessor is immediately available. One timing consideration of the operation of the microprocessor 286 is that the line trace computations and the "end of segment" process for a search segment complete must be before the occurrence of the first segment data interruption for the next search segment.

At the end of each computation and the running of the Mg.15 subroutine, the microprocessor 286 takes the scheduler routine to query 300 again. A positive answer to query 300 (which indicates the end of a data record) switches the microprocessor 286 advances to subroutine 302. The "end of segment" subroutine 302 is at the end of the calculations loop for each search segment. This subroutine provides the first and second pointers and the "end data" signal return. The current X coordinate of an available storage element of memory 50 is also incremented in preparation for the next search segment and each of the row calculation tables is checked for line endings. An end of line is found every time the X coordinate at the beginning of the line is not equal to zero and the current X coordinate (XC) is equal to the X coordinate of the X-STOP + lines is. For each line end found, the line block allocation is

709824 / 08U

lungs subroutine of the Pig. 15 retrieved to collect the last segment of data.

To transfer video data from strip memory 48 to line block memory 50, the microprocessor 286 performs an Extraction Output subroutine to add new parameters to the extraction registers and output the line block memory controller. Initially, the line block memory allocation table of memory 294 is reset to accept line assignments when line trace subroutine 298 is passed will. Allocations to the line block memory allocation table are made by the line block memory allocation subroutines 310 and 314 made. An output start word contains the address of the next parameter area, which comprises the next 9 words. Initially, the first one word of the line block memory allocation table becomes for output to the extraction registers 52 addressed. This first word is reset by the extraction registers 52 at the end of the video data. At every extraction output interruption the parameters of a line block of video data in the allocation table are identified through the output address, to the extraction registers and the line block memory controller 50. the Output address is then updated to the same line block of video data in the next search segment. This routine continues until all selected areas (zones; also called areas above) of video data in stripe memory 48 is transferred to locations in memory controller 50.

During the run of the Fig. 14 scheduler routine through the microprocessor 286 causes a negative response to the query 300 (if additional data for a search segment are found) the advance of the loop to query 326, which, if the answer is positive, a line selection subroutine 328 queries. The line selection subroutine selects the address of the bottoms of two lines tracked by document 10 and creates skew normalization and pensterboden parameters

^ G 5 G δ 5 4

for the selected two lines.

The criterion for choosing the address of the bottom row is to find the stored data with the lowest average Y coordinate, with at least four blocks of data. Tenblöcken rows of patterns with three or less D _a to be rejected as indicating an incomplete line. The criteria for selecting the second line of patterns is that they overlap the bottom line by at least two search segments in the X coordinate direction and must contain at least four data words. After the two lines are selected, any line data blocks identified with other lines of patterns from document 10 are released for reallocation on the next document.

After selecting the lower two lines of the pattern, the parameters of the characters are calculated, including the Normalization factor, the skew factor and the window floor, according to the following calculations:

Normalization factor =

Sum XY - (Sum X) (Sum Y)

Skew factor = sum P

Sum X -

(Sum X) ²

Sum P

-σ "4. -ν λ sum Y inclined- (sum X) _{o> T} ... Pensterboden = - _unity ^{ö + 2 normal1}

ization

Both the skew factor and Pensterboden parameters provide an evaluation of the smallest (Pehler) squares of points derived from the mean elevation representing the row. After the line parameters are calculated, becomes an output pointer (Y) to the first area of the line block memory allocation table of the memory processor 294 which contains data from the selected bottom row of patterns. The bottom line coordinates are then

709824/0844

2G56854

to the reading window and selection format device 54 and the existing line number (L) and the last line allocation number (LL) are set to the line number of the selected line. Subsequently, the next line allocation number (NL) is set to the line number of the selected line and the line selection subroutine 328 is completed by unloading data from the line block memory SO to the reading electronics 58, which is initiated by the output of the first line block bottom address to the window selection and format device 54 and the line block number to the line block memory controller 50. The completion of the unloading of data from the line block memory 50 to the reading electronics 58 is controlled by window select command words.

The process of transferring input and output data to the microprocessor 78 continues while the processing in the Background is completed until the line block memory controller 50 provides an interruption to the processor when new coordinates of data from the reading window selection and format device 54 can be requested. At each interruption by the control device 50 the output pointer (Y) is incremented for the next search segment (Y = Y + 9) and the new parameters of the current one Line (L) are output by the format device 54 to the reading electronics 58. This data transfer continues until the end of a line of pattern data is detected. The end of the line of pattern data will then be detected when there are no address locations in the row block memory allocation table of the processor 294 addressed by the output pointer (Y) are available. Upon finding one end of the line becomes a STOP code from the line block memory control device 50 is delivered and the current line (L) is set to the next line (NL) of data, which are to be transmitted to the reading electronics 58. The microprocessor resumes the scheduler routine and when end of line code is detected (L ^ LL) generated a query 330 a negative answer to advance the micro-

709P24 / 084 *

- 55 -

(£ ■ Z
processors to a "read next line" subroutine 332.

When the "read next line" subroutine is called first, the initial step is to find the next line (NL) address to zero and the last address line (LL) to the second line number. Then the output pointer (Y) reset to the beginning of the second line address and the second line normalization, skew and window bottom parameters are output to the read and select format device 54 and normalizer 60. After completion of this step, the dumped data for the first section (section) of the second line becomes the line block controller 50 submitted. After the transfer of the second line of data is complete, all Line blocks assigned to read lines are reset, and all output addresses are also reset, and although in preparation for the transmission of additional input data to the processor memory 294.

The line selection processing - see Fig. 16 - is completed by extracting stored data from stripe memory 48 for delivery to the line block memory controller 50. The stripe memory is a video buffer with shift registers 334-1 to 334-ri consisting of eight sections in Fig. 16. The stripe memory, as shown, sees a delay of 384 samples the arrangement 30, during which time the search electronics 32 complete the method of row selection. The input data to each register is four-bit video data from analog-to-digital converters 44 and allows the storage of gray levels of each video data cell. The eight-section one The strip memory of FIG. 16 provides the memory output for a detection zone 512 cells high.

FIG. 17 shows a logic diagram of the extraction registers 52 which extract video data containing line information from the Selects strip memory 48 and divides this data into the

7 0 9 8/4/0844

2656S5A

-srt -

Line block memory controller 50 conducts. In the particular system described here, there are three extraction registers operated simultaneously so that three separate pieces of video data are stored in corresponding allocated line block storage elements of the line block memory controller 50 can be written. Figure 17 is a schematic of one of the three extraction registers 52. An output line from each of registers 334-1 through 334-n is associated with an individual Input line from selection gates 336 and 338 connected. These selection gates are generated by output data from a window bottom buffer 340, with an input variable from a window bottom lock 342, is addressed.

Prior to the extraction operation for a block of video data from the strip memory 48, the location of the The lowest cell of data for a specific data block is fed to the extraction logic, which is derived from the interlocks 342 and the buffer 340 exists. The information supplied to latch 342 is known as the "line block window bottom" and is stored in the lock by a signal generated by the line trace microprocessor 78. If that Search segment associated with a new window floor appears at the output of registers 334-1 to 334-n, the window floor buffer 340 is loaded with data from latch 342 by a signal SRP on line 344, which is also is supplied to the line track microprocessor as an interrupt signal. The signal on line 344 identifies that the window bottom latch 342 is ready to be updated for the next search segment that is at the exit registers 334-1 to 334-n appear.

The bottom window code at the output of buffer 340 is an eight-bit binary code, with the three most significant bits (most significant bits = MSB) of the window floor represent the section (section) of the strip memory that contains the Contains bottom cell of the line block, which is in the line block memory control device 50 should be entered. These

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2G5B3C4

Bits appearing on channel 346 are applied to select gates 336 and 338 to select the appropriate sections to be selected for data entry. In the embodiment of the present invention, the selection gate 338 selects the section of the line block video data including the bottom cell, and the selection gate 336 selects the portion of the line block video data immediately above the section containing the soil data.

During the first sample of the next 64 samples, data selected by selector gate 336 is randomized to memory (RAM) 346, while the selected data from the selector gate 338 is supplied to a Randora memory 352 will. Data stored in the random memories 348 and 352 are sequentially scanned and sent to a selector or Select gate 356 transmitted. While data is in memory 348 and 352 are written, data from the previous 64 samples from the random memories 350 and 354 are written had read. Data from the selected random memories is passed through the operation of select gate 356 to the serial / parallel converter 358, and supplied from this to a locking gate 360.

The random memories 348, 350, 352 and 354 alternate between operating in a read mode and a write mode on a sample after sample basis, as laid out by a Scan Rate Clock (SRC) on select gate 362 and a sample rate clock (SRC) applied to select gate 364 is set. To set up the write mode the random memory generates a write counter 336 of address data over channel 368 for select gates 362 and 364. The write counter 366 is incremented or advanced by a clock signal (CCLK) applied on a line 370.

During the reading mode, the reading counter increases by 64 counts switched on for each sampling time, thereby permitting that data from 64 samples in the random memory is equal to

709 8 2W08U

written in early during a sampling time. Pure the read mode generates a read counter 372 address information for the select gates 562 and 364 via a channel 374. The Read counter is also advanced by the clock signal (CCLK) applied to line 370. The read counter generates the Address information through the select gates 362 and 364 during the read mode of the random memories.

The read and write addresses are alternated on a scan-by-scan basis on output channels 376 and 378, coupled as shown, to the random memory, provided cyclically. The read counter 372 is preset with each scan with the five least significant bits (LBS) from buffer 340 as a result of a signal BS applied to the read counter via a line 380. The to the Least significant bits applied to counter 372 represent the stripe memory address which is the bottom cell of the read window contains. This counter is also incremented at a cell sampling rate so that there are 64 cells from the strip memory each scan starting with the window bottom cell.

Data timed by the timing signal (CCLK) to the serial / parallel converter 358 is made from the random storage format converted to a 32 bit wide word and passed to latch 360. Every time all eight cells become the Words in converter 358 are transferred to latch 360 by a load signal (LDL). During the serial / parallel converter 358 is loaded with the next eight cells, the cells previously transferred to latch 360 become the row block memory controller 50 transferred. This process repeats itself for 64 samples at what time new Pensterboden parameters are loaded to facilitate the operation of extraction registers 52 for a new segment of video data to renew.

7 0 9 8? W08U

Data extracted from the stripe memory 48 by the extraction registers 52 - see Fig. 18 - becomes the line block memory control device 50, which is organized in multiple blocks of video data bits, sufficient to Store 64 samples by 64 cells per sample by four bits per cell. In the system described there are three Extraction registers, as in Pig. 17, uses what the simultaneous use of three memory blocks is necessary power. Video data from the extraction registers is saved in a Select gate 382 is entered and on an input data bus (Bus line) 384 one of the memory blocks 386-1 to 386-n fed. For a typical two-line memory system, 64 memory blocks are used, which provides enough memory space to to record two six inch (6 χ 2.54 cm) lines of video data. Each of the memory blocks 386-1 through 386-n is in a matrix of 512 words of 32 bits per word and each block is independent of the next, so that in any Number of blocks can be written at the same time. Internally, each memory block consists of 386-1 through 386-n Read / write memory with direct access (RAM), which are stored in any sequence can be addressed.

Address signals applied to memory blocks 386-1 through 386-n are passed through a block enable decode register 388, addressed by a selection gate 390. Three inputs to the selection gate 390 are connected to a block allocation buffer 392, and a fourth input is from a block allocation read puff er 394 received. The block allocation buffer 392 is coupled to a block allocation lock 396, which receives block assignment codes applied to the inputs. The block assignment read buffer 394 is coupled to a block assignment read latch 398 which provides read code assignment receives.

The selection gates 382 and 390 are activated by the output of a decoder 400 via selection control lines 402 and 404, respectively controlled. The decoder 400 is supported by a matrix wire

7 0 9 «? 4/0844

b ü O O L. A

Counter 406 is addressed, which also has an address on dialing gates 408 creates. Each of memory blocks 386-1 Ms 386-n and select gate 408 receive a read / write control signal on a Line 410 from decoder 400. To selection gate 408 is also a read address is applied by a read address counter 412 which is advanced by a command on a line 414 and a load-write buffer signal on line 416 is generated. The load read buffer signal on line 416 becomes applied to one input of an OR gate 418, which receives a second input from an AND gate 420. The two inputs to AND gate 420 are the most significant Bits from read buffer 394 and the clock signal (CCLK) on line 422. The output from OR gate 418 is applied to read buffer 394.

In operation of the line block memory controller 50, line block memory allocations are made by the line trace microprocessor 78 is applied to assignment latch 396 prior to the occurrence of data for a scan segment at the output of the extraction register 52. The line block memory allocation code for each of the extraction registers applied to the latch 396 is a seven-bit code with bits 2 to 2 ^ for identification of the storage elements of storage blocks 386-1 through 386-n. The most significant bit of the line block memory allocation code, d. H. Bit 2, is used to identify that there is no data for the associated extraction register should be retained during the present scanning segment time. This last bit is used for all Disconnect memory block enable lines from decoder 388 during the normal write cycle of an extract register.

When the extraction register data becomes available for a given set of storage elements, the block allocation codes to allocation buffer 392 by signal WBAB applied to latch 396. This Signal is also one of the interruptions to the line finder

7 η ^f - ^r ? a ■ · η 8 <U

ORIGINAL INSPECTED

26560G4

Microprocessor 78. From buffer 392, select gate 390 directs one of the line block assignment codes for the line block decoder 388, which releases the corresponding line block memory.

Once every eight cell times, new data is on the dial gate 382 available from extraction registers 52. During this eight-cell period, there are three write cycles and one read cycle executed; Each cycle requires two cell times. For the first write cycle, data from extraction register # 1 is transferred to the input data bus through select gate 382 supplied with the corresponding line block allocation code is applied to selector 390 to enable corresponding line block memory 386-1 through 386-n. The next two subsequent write cycles perform a similar operation for extraction register no. 2 and extraction register no. 3, respectively by.

During the three write cycles, a write address is fed from the address counter 406 to the memories via the selection gate 408. This write address is also used in the decoder 400

1 2
decoded with bits 2 and 2 providing dial address data for dial gates 382 and 390. The write address bits

3 11

2 through 2 from decoder 400 generate the 512 memory element addresses for memory blocks 386-1 through 386-n for access

1 2 of a complete block. Bits 2 and 2, as decoded by decoder 400 from counter 406, are also used ANDed together to provide read / write control on line 410 for memory blocks 386-1 through 386-n. These same bits linked by the ÜND also enable the selection gate 408 to set the output of the write address counter 406 to the output of the read address counter 412 to be selected.

After the three write cycles are completed, the read cycle becomes initiated. The format for read block allocation is similar to the format of line block memory allocation for interlock 396. The most significant bit switches during the

709824/0844

Write cycle off the memory enable lines to AND gate 420 and OR gate 418. This most significant bit also becomes the reading window selection format device 54 supplied, whereby this circuit is kept in a waiting mode. The most significant bit of the read block assignment also allows read block allocation buffer 394 to be continuous is loaded with the output data from the latch 398. This allows the initiation of a read cycle whenever requested by the line finder microprocessor 78.

If any of memory blocks 386-1 through 386-n are to be unloaded onto output data bus 424, the corresponding one will be Read code from latch 398 is transferred through buffer to select gate 390. The address is in the decoder 388 is decoded onto one of the block enable lines.

A line block enable code from decoder 388 gives one of the Memory blocks 386-1 through 386-n free, the read / write control device on line 410 identifies that the read cycle is selected, and the read address counter 412 generates an address which is selected by selection gate 408 the corresponding Memory block 386-1 through 386-n is supplied.

The counter 412 is incremented by an instruction on line 414, which instruction is in the reading window selection format device 54 originated to identify the time when the output data was on the bus 424 are transmitted to read electronics 58 and that the next data word is made available to the format device should. Read address counter 412 is incremented to 512 at which time it passes block allocation buffer 394 the ODEK gate 418 loads with a new line block code. This same signal as sent to OR gate 418 from Counter 412 is asserted, generates an interrupt to the line trace microprocessor 78, thus identifying that the block assignment lock 398 is up to date should be brought.

70982A / 08U

-m -

To

Video data from line block memories 386-1 through 386-n is for the reading window selection and format device 54 which selects the portion of each block of video data to be passed to normalizer 60. The reading window selection format device 54 format converts the video data into a serial bit stream and generates a data clock when valid data is sent to the normalizer 60. The format device 54 also provides a "begin reading" scan signal to normalizer 60.

19 illustrates three possibilities which can exist when a read scan segment is extracted from the block memories 386-1 through 386-n should be extracted. Figure 19A. shows the case where the scan is completely available from the line block memory within the read scan segment is where all of the required data for the format device 54 is available are. In Figure 18-B, some cells are below the row block scan stored in line block memory required for processing by the reading electronics. Even though that cells are not actually available, they will Forced by the operation of the format device 54 to appear as white cells. This is done by generating white data cells reached. In Fig. 19 (18) -C is the opposite Situation shown in Fig. 19 (18) -B, where cells above the line block scan in a line block memory for processing to read electronics 58 are required but are not available. Again, those will Cells that are not available are forced to appear as white cells by creating pseudo-value white cells. Although the conditions shown in Figures 19B and 19C do not usually occur, they can but occur with larger character sizes and an oversized line skew.

Fig. 20 illustrates the state where pseudo-value white cell data must be generated in order to obtain a line scan segment

7 0 9 B? U ι 0 S 4 4

to complete. Video data for the cells within block outlines 426 and 428 are stored in elements of the line block memories 386-1 through 386-n. Due to the excessive skew of the characters within the reading window, there is a Area of video data below block 426 and above block 428 not available from line block memories. These cells are forced to appear as white video data to reader electronics 58 for processing.

It should be noted that access to a full line block scan in bytes of eight cells follows, regardless of whether the cells are used by the reading electronics to be or not. This provides for the line block memory controller 50 to be properly unloaded.

Figure 21 shows a logic diagram of the window selection and data format apparatus 54. Before unloading a line of data, the address of the beginning window bottom is put into a register counter 430 invited. This value represents the position of the lower cell in that of the line block memories 386-1 to 386-n sample to read. Data representing the window height from the line trace microprocessor 78 is fed into a decoder 432 to enter the height; each format to be treated To determine sampling. The address of the line block window bottom is also created with the format device 54 to a floor register 434. The line block window bottom data to register 434 is the current line block window bottom, and is changed every time a new line block of video data from line block memory 50 is subject to access.

Both register counter 430 and register 434 supply their output to a subtraction logic (subtractor) 436, which produces the difference between the current line block window floor and the current reading window floor. After this the feed processor is started are the beginning ones

Window bottom data to counter 430 is the current reading window bottom.

70982A / 08U

The D _a th to the counter 430 are periodically changed, namely by an increment / decrement command from the vertical section (section) of the normalizer 60 via a line 438. The rate at which this register counter 430 is changed in value, is a function of the Skew angle of the reading window. This register is represented by a standard up / down counter.

The window selection and data format apparatus includes counters 440, 442, and 444. The counter 440 is used to ensure proper and proper sample buffer loading and serialization of the scan data. The counter 442 contains the location or position where the reading scanning floor is relative to the Line block scan floor should begin. The height counter 444 ensures that the correct number of cells for each Sampling supplies output variables. The interrelationship between these counters is described below.

At the beginning of each scan, the counter 442 is counted with the difference between the current window bottom and the current Load the row block window bottom as provided at the output of the subtractor 436. Simultaneously with the loading of the counter 442 by the difference from the subtracter 436, the counter 440 and the Altitude counter 444 reset to zero.

At this time, data is input from line block memory controller 50 into data buffer 446 via channels 448. When the counter 442 has a value less than full, this indicates that the D th _a transfer below the lowermost cell are required in the buffer from the line memory block. In this case the data output of the buffer 446 is forced to zero in a selection gate 450. This is accomplished by disabling the outputs of selector 450 which acts as a "serializer" for data buffer 446.

709824 / 08U

-6fr-

At this time, a data clock is generated and the counter 442 and altitude counter 444 are incremented. Switching on the counter 442 and 444 continues until Ms the value of the counter 442 is equal to or greater than the zero level is. As long as the counter 442 has a value less than zero ", the output of the selection gate 450 forces the output data to normalizer 60 to a zero or video white level. This state is in Pig. 20 through area 426a shown. Data is also forced to have a pseudo-value white level like this in Pig. 19B is shown.

When the counter 442 reaches a level equal to or greater than zero, a comparison is made in one Comparator and decoder 452 between the counter level in counter 442 and counter 440. If the value of counter 442 is greater is than the value of counter 440, then the bottom reading probe cell is above the bottom of the line block. Under these conditions, the counter 440 is incremented by the comparator and decoder 442 until it reaches a counter reading level equal to that of counter 442.

During the time interval during which the counter 440 is incremented the data buffer 446 becomes the next scan from the line block memory control device 50 loaded. The load signal is generated on a line 454 by the comparator and decoder 452 and is also sent to the Extraction register controls applied. The signal to the extraction registers 52 causes the line block memory address to be advanced.

If the value of counter 442 is at a level equal to the value of counter 440, the latter is tested, to see if it has less than the total number of cells in a data block. In the example discussed earlier, the counter 440 is tested to see if it is less than 64. Concurrently, the altitude counter 444 is tested to

70982A / 08U

- 6η -

IN THE

determine whether the counter level has reached a maximum number of cells in a data block. When the two counters 440 and 444 are at the maximum count level, data is sent to normalizer 60 via the selection gate 450 issued. A data clock is now enabled in the counter 400 and the height counter 444 is incremented, and for every eight cell times, the data buffer 446 is loaded with a new sample.

This operation continues until one of the following two conditions is met; first, when the counter 440 has a value equal to its maximum level, thereby indicating that the upper cell of the data block is output. If the first condition is met and the altitude counter 440 has not yet reached its maximum level, this indicates that the cells above the highest cell in the data block are required. This state is shown in Fig. 19C.

A D _a tentakt is released and data is white forced by the selection gate 450 and the height counter 444 is long passed on, until it reaches its maximum count. During this time, data supplied to normalizer 60 is forced to a white level. When the height counter 444 reaches its maximum count level, a new scan unload sequence begins.

The second condition, which ends the advancement of the counters 440 and 444, is present when the altitude counter 444 reaches its maximum count level before the counter 440 reaches its level. This condition indicates that a read scan is complete, but the line block scan is not fully loaded. The data blocks and the data transmission become purely this condition locked and the counter 440 is switched on until it reaches its maximum level. Again all eight Cells times the data buffers 446 are loaded by the row block memory controller 50 so that a complete download

70982 ^ / 08 4 4

scanning is unloaded from the line block memory. This allows the synchronization of the scan to be maintained. When the counter 440 reaches its maximum count level, a new scan discharge sequence is initiated.

Fig. 22 is a flowchart showing the sequence of operation of the window selector data format logic; the system initially being held in a wait mode 456 until the most significant Bits from buffer 394 of Figure 18 are no longer equal to one, as indicated by a negative response from the query is shown. The sequence of operations continues to step 460 where the counter 442 holds the difference between the registers 430 and 434 is loaded as output from subtracter 436. Counters 440 and Height counter 444 is reset to zero and data is loaded into data buffer 446.

The sequence of operations continues waiter and when the request 462 indicates that the count level of counter 442 is less than zero, then step 464 is completed which causes the Counter 442 advances and allows a data clock to force select gate 450 to peek at white video. To this Time the altitude counter 444 is incremented.

If the value of counter 442 is equal to or greater than zero, the sequence next tests to see if the value in counter 442 is greater than the value in counter 440. When the level of counter 442 is greater than the level of the counter 440, inquiry 466 generates a negative response and the sequence advances to inquiry 468. At this time it is determined whether the value in counter 440 is less than the maximum cell block count.

If the value of the counter 440 has not reached its maximum level, the sequence proceeds to a query 470, to evaluate whether the height counter 444 has reached its maximum count level. If this request a positive Receives an answer, the sequence advances to query 472,

708 P ₁ 7ΛΙ 0 8 U

■ Ve

which evaluates the counter reading level in the counter 440 and at predetermined counter reading levels the sequence proceeds to Step 474 continues where data is loaded into buffer 446. The sequence then proceeds to an incrementing step 476 where counters 440 and 444 are incremented and the sequence returns to query 468.

When the value of counter 440 is at its maximum level, it generates a negative response from query 468 and the sequence proceeds to an inquiry 478 to determine the count level of the height counter 444. if the counter reading in counter 444 is less than its maximum level, the sequence proceeds to step 480, which increments counter 442 and forces pseudo-white video data from selection gate 450 to normalizer 60. A positive one Response to query 478 returns the sequence to the wait mode.

A positive answer to query 468 and a negative answer to query 470 transports the sequence to one Step 482 which disables data from select gate 450 by a disable signal generated by the comparator and encoder 452 on line 484. The sequence of Figure 22 proceeds to an inquiry 486 to determine whether the value of the Counter 440 has reached its maximum level. Until the counter 440 reaches its maximum level, the sequence advances a query 488, which is similar to query 472, and at preset meter reading levels the sequence advances to load data buffer step 490. During step 490, data is received from the line block memory controller 50 loaded into data buffer 446. The sequence then returns to step 482, which also goes through a negative response to query 488 is obtained.

If in query 466 the value of counter 442 is greater than counter 440, a positive response is generated, to advance the sequence to a step 492, the one

70982W08U

2 G 5 G 3 C 4

"Ή *

Cycle to advance the counter 440. The sequence proceeds to inquiry 494 and at preset meter reading levels the sequence advances to a step 496 to load data into buffer 446. With the exception of the preset Count level and upon completion of the loading of the data into memory 446, the sequence returns to the query return.

Accordingly, the window selection format device 54 receives sample data from the line block memory controller 50, evaluates the location of the sampling window and supplies video data to the normalizer 60 in terms of format. The timing of the Operation of the various components of the described system is important to continuous processing of the data from the document 10 to the reading electronics 58 to be provided.

Figure 23 shows some of the basic timing signals for operating the system of Figure 2. The Cell Rate Clock (CCLK) is represented by pulse waveform 498, where the Pulse number for a video sample is defined between the brackets. At the beginning of each video sample, how through As illustrated by waveform 500, a "start scan" (BS) signal is generated. The relationship between the number of cells at the exit of the analog / digital converter 44 and the "start sampling" signal is illustrated by the sequence of numbers on line 502.

On line 504 is a series of "begin scan" signals using a different timing basis than the waveform of line 500. A The "start scan" signal occurs for each video scan and the video data for each cell is for one scan stored in stripe memory 48 and by the search correlator 68 processed to search analyzer 72. As discussed, there are 64 video samples of 64 cells in one Search segment compressed, as shown in FIG. 6.

709824/0844 ORIGINAL INSPECTED

? G b G 3 5 4

- rt -

It should be noted that both the Cell Rate Clock (CCLC) and the "Beginning sampling" pulses originate in video electronics and are the basic clocks from which all other signals be derived.

A segment rate pulse as shown on line 506 is generated once every 64 video samples. The segment rate pulse is generated at the beginning of each search segment and allows the further processing of data condensed into a search segment Data. Also derived from the cell rate clock is a correlated seek sample one (CSSO) signal, such as this on Line 503 is shown and the sample rate clock (SCRC) as shown on line 510.

A "Document Present" (DP) signal, such as this on line 512 is generated by a photocell in the video electronics and identifies the presence of a document at the data collection station. The search reset signal (SR) on line 514 is taken from the leading edge of the "document present "signal. All search functions are performed by this signal is reset. The trailing edge of the search reset signal is used by line trace microprocessor 78 to indicate that there is no more data from the document to be processed Are available. Line 516 illustrates the relationship between the segment rate pulse (SRP) with respect to the "Document present" signal for comparison at the beginning of the scanning signal on line 504.

Figure 24 shows a timing diagram for the extraction register of Figure 16 including the "begin scan" signal on line 500, the segment rate pulse on line 516, and the sample rate clock on line 510. This illustrates the relationship between the three timing signals and also the relationship between the timing signals and the read / write function of registers 334-1 through 334-n. As shown in lines or lines 518 and 520, is when scan one is in the strip memory 48

709824/0844
ORIGINAL INSPECTED

2Bbü5b4

is written, the scan 64 to the extraction registers 52 read.

The sample rate clock is also shown on line 522 on an expanded time base with the "begin sample" · Clock on line 524 on the same extended time base. At the trailing edge of each beginning sample pulse a load output interlock (HL ·) pulse to the interlock 360 of FIG. 17, as shown in line 526. Line (row) 528 indicates which cells are between successive locking pulses can be read. Accordingly, on the trailing edge of latch pulse 526a, all of the data is from cells 56-63 of the previous one Scan loaded into latch 360. At this time the video data is read and sent to the line block memory controller 50 headed. At the trailing edge of the lock pulse 526b, all of the video data is from the Cells 0-7 of the currently read sample are loaded into latch 360 and are then read to line block memory. This sequence of operations continues through the extraction registers where the video data from all eight cells is sequential loaded into the latch 360.

Fig. 25 shows a timing chart of the line block memory control apparatus 50, on line 530 being the load-write block allocation buffer applied to latch 396 of FIG (WBAB) pulse is shown. The trailing edge of pulse 53Oa occurs at the beginning of a sampling time, which is divided into eight equal time segments. As previously explained, during each of the eight time segments, data is from each of the extraction registers via selector gate 382 to block memories 386-1 through 386-n. During the fourth part of each of the eight segments, data is collected from the Block memories 386-1 through 386-n read to read window select and format device 54. This read / write sequential operation thus occurs eight times for each sample rate clock pulse.

INSPECTED

--rr-,

Pig. Figure 26 shows a general sequence of the processing function depending on the time for the purpose of further explaining an example of control parameters of the invention Systems. Pig. 27 shows the search segments N through N + 4 which contain the line character "759ADE". The dashed lines or rows in segments N + 1, N + 2, and N + 3 represent the data bottoms and the tops of the data, as indicated by the search electronics are determined. Search segments N and N + 4 do not contain enough data to determine the determine upper and lower (bottom) positions. In the system described, the search segment N + 1 was determined line information thereby making it necessary to retain the sample data in search segment N. Because the ground and the top of this search segment could not be determined, it will be determined by the read window select and format device 54 forced to have the same block window floor as the search segment N + 1. Sample data within the memory blocks 2, 3 and 4 for search segments N + 1, N + 2 and N + 3, respectively, are withheld because each of these has been determined Storage blocks containing top and bottom (bottom) information. The video samples of search segment N + 4 are stored in the memory block No. 5 retained because it is adjacent to the sample data of memory block No. 4, with the block window bottom is forced to have the same value as the previous memory block.

While the video data is in the memory blocks (each block is 64 cells in height and 64 samples in width) retained in line block memory and controller 50, previously identified as a line of interest, become the window height, the beginning of the penster floor and the skew angle from the top and bottom (bottom) information calculated by the microprocessor 78. When this line of data, as shown in Fig. 27, from the line block memory and controller 50 is read into normalizer 60, the data is between the top window line or Line 532 and the lower window line or line 534.

709824 / 08U

8A

selects and fed to the normalizer. The first sample stored in memory block # 1 is the beginning sample of line "759ADE ^11. The window bottom is changed by incrementing counter 442 based on the skew angle 536,

Fig. 26 shows six equal time segments. During the time segment t.j, time frame 537, becomes the video data of the search segment N the Pig. 27 in the search correlator 68 correlated. During the time frame 537, the data from the search correlator 68 is obtained analyzed by the search analyzer 72 and condensed into a single search segment. During the time period t «, time frame 539, the search segment N is evaluated in the top / bottom detector 74, to determine the locations of the upper ends and lower ends (bottoms) of the rows of patterns in the search segment N.

With the completion of the operation of the up / down detector 74 becomes a connection function with two preceding segments performed by the segment connecting device 76, during time period 538. Output link information for the second previous search segment routed during a time interval 540, and connection information for the next following search segment is routed during of a time interval 542, the connection information for the search segment N is fed to the line trace microprocessor 78 during a time interval 544.

At the beginning of the time interval tg, the microprocessor 78 leads an evaluation during a time interval 546 to determine whether the search segment immediately preceding the segment N should be retained, since search segment N is a Contains line start. During a time interval 548 control signals are processed to the extraction registers 52 and line block storage and control device 50 for the search segment immediately preceding segment N.

709824/0844

82,

During a time interval 550, the sample data in stripe memory 48 for the memory block becomes previous to the segment N of the line block memory controller 50.

If the search segment is correlated N + 1, then processing is the information during each of the pig's time intervals. 26 ordered sequentially to the next search segment. These Processing continues during the "document present" pulse on line 512 of FIG.

Data supplied to the reading electronics 58 are fed to the normalizer 60 entered. The normalizer reduces due to parameter data from the line trace microprocessor 78 the area of the detection zone by a predetermined amount, this quantity is referred to as the normalization ratio. The normalizer 60 also receives skew correction parameters from the line trace microprocessor 78 to correct the skew of the line data as shown in FIG Fig. 27 is shown.

This is followed by normalization and skew correction For example, the video data for a line of patterns on the document 10 is fed to the correlator 62. The correlator 62 determines the black / white state of the cell data from the normalized video information. The black and white video data is then transferred to video memory 56 which is a memory is which is used to display the correlated lines of the read data for later presentation to a character recognition system buffers. The character recognition or pattern recognition unit may be any of those known commercially Be units. Reference is made in particular to the drawing, from which details according to the invention and Features result.

- Claims 9824/0844

Claims (1)

FATEIITAI PROPOSALS 1. Acquisition system has a single reading station for character recognition of multi-line data using a self-scanning photocell array as Reading station, characterized by a memory (48) for the temporary storage of multiple lines at the same time, an electronic search circuit (32) for compressing the read data into search segments for evaluating the upper and lower ones Positions of a character line, a connection circuit (76) for determining the row binding between the elements of a search segment of condensed data and the elements of the previous search segment for future processing, a line tracking device (line guide) (52) for extracting lines of characters from a temporary memory for transfer to a line block memory, and transfer circuits (54 and 58) for transferring the data in the line block memory to a character recognition unit. 2. System according to claim 1, characterized by a plurality of independent line block memories (50) such that a set of blocks can store information from a document, while data from a previous document is from the Memory can be read out. 3. System according to claim 2, characterized in that daf3 block memory (50) Save multiple lines in parallel. 4. System according to one or more of the preceding claims, in particular according to claim 1, characterized by a Circuit (54) for skewing lines of characters when the Lines of characters from the line block memory to a character recognition unit be transmitted. 7 D ° ^ m ■ 0;] U ^u i. System according to one or more of the preceding claims, in particular claim 1, characterized in that the search electronics means have search correlators (68) and analyzers (72) and an upper / lower detector (74). H. System according to one or more of the preceding claims, in particular claim 1, characterized in that the ! Data acquisition takes place when the document moves past the scanning arrangement. Y. Method of reading multiple lines of .data in the Character recognition system according to claim 1, characterized by Scanning with a self-scanning photocell array the width of a document to generate data which represent the data on the document, storage of the data in a memory, Compression of the data in search segments for evaluation dex * upper and lower position of the character lines, Evaluation of the line connection between the elements of a search segment of compressed odex * condensed Data and the elements of the previous search segments, processing of the search segments in a line spacing device and selecting lines of characters from the memory, and selecting information from the selected lines of characters for processing in a character recognition unit. 8. The method according to claim 7, characterized in that "3 each Cell of the photo line arrangement has an output size, which is either black or white, depending on the sampled data, and that a black / white decision is determined for each cell by summing nine consecutive samples of each cell. 7 P'- ■ = ■: -u <Η U * -'S- 2b568b4 9. Optical scanning system in which a transducer records adjacent characters in spaced-apart lines a document and generates digitized drawing data signals for a memory, characterized by means for Identification of a line of characters from an arrangement of character lines from digitized character signals and generation of a line reading signal, Means for receiving the character signals for a selected line of characters from the memory, means responsive to the line find signal to complete the transmission to effect a selected line of characters from the memory to the recording means, and means for transmitting the character signals for a selected one Line from the receiving means to a character recognition unit t. 10. System according to claim 9, characterized in that the means for identification generate a line reading signal to select the bottom line or bottom line from continuous patterns of a row arrangement. 11. System according to claim 1, characterized in that the Means for identifying a line of characters comprise means which represent the top of a selected row Specify character signals and the character signals representing the bottom of a selected line determine. 12. System according to claim 3, characterized in that the means for identifying a line of characters are further Memory means for the character signals representing the top of a selected line, and also for the character signals which represent the bottom of a selected line. 7Γ. -. '. Γ Η Uk 13. System according to claim 12, characterized in that the Means for identifying a line of characters further comprise line position logic for selecting the Character signals which represent a line of characters for transmission to the recording means. 14. System according to claim 13, characterized in that the means for identifying a line of characters further include a Include track logic for scanning the character signals in the memory means to generate the line find signal. 15. System according to one or more of the preceding claims, characterized by means for generating a correction signal for the skewness of a selected line of character signals transmitted to the receiving or receiving means are. 16. System according to claim 15, characterized in that the identification means means for determining the skew one line of character signals in memory. 17. System according to claim 15, characterized by means for Generating a normalization signal for the character signals transmitted to the receiving means. 18. System according to claim 17, characterized by means for Determining the character size from a line of character signals in the memory for generating the normalization signal for the means of reception. 19. System according to claim 15, characterized in that the means for identifying a line of characters is a line locating signal Generate to select the bottom line or line of the arrangement of character lines. 709824 / 08U 20. System according to claim 15, characterized in that the Means of inventory identification of a line of characters include: Devices for identifying the character signals which represent the upper end of a selected line and to identify the character signals which the lower end (bottom) of a selected line, devices for storing the character signals which represent the represent the top of a selected line and the character signals representing the bottom of a selected line , line position logic for selecting the character signals which represent a line of characters for transmission to the storage device, and tracking logic for scanning of the character signals in the memory devices for generating the line find signal. 21. Method of selecting a line of characters from an array of character lines optically transmitted by a transducer are sampled to generate character data signals, characterized by the following steps: Storage of the character data signals in a memory, successive selection of a line of characters from one Arrangement of character lines to generate a line find signal, selectively transferring the character data signals from the memory into a buffer memory in accordance with the line find signal, and transferring the transmitted character data signals to the character recognition unit . 22. The method according to claim 21, characterized by changing the character data signals during transmission from the buffer memory to the character recognition unit. 23. The method according to claim 21, characterized in that the step of successively selecting a line of Characters includes providing a line find signal for the lowest line of characters from the arrangement of FIG 709824/0844 Lines of characters. 24. The method of selecting a line of characters as recited in claim 21, wherein the step of sequentially selecting a line of characters compares a previously selected line of character data with an incoming line of Includes character data, and that the line of character data is transferred from the memory, which has a preselected position. 25. The method according to claim 24, characterized in that the comparison of the lines of character data is the comparison of the ground signals a preselected line of character data with ground signals of an incoming line of character data. 26. System, in particular according to one or more of the preceding Claims including a transducer that scans adjacent patterns of spaced characters and pattern data signals in digital form, characterized by the following combination: Means for storing the data signals of patterns of all spaced lines scanned by the transducer, Means for searching for the lines of patterns from the arrangement of spaced lines of digitized data signals for generating line retention signals and line reading signals. Means for receiving the pattern data signals from selected lines of patterns identified by the zero hold signals, Means responsive to the line break signals for effecting transmission of a selected line of patterns from the receiving means, and Means for transmitting a selected line of patterns to a character recognition unit. 27. System according to claim 26, characterized in that the means for searching generate a line read signal to the bottom line or line of contiguous patterns of a row arrangement to select. 709824/0844 28. System according to claim 26, characterized in that the means for searching for a line pattern comprise means to locate the pattern data signals representing the top of a selected line and to locate the pattern data signals locate which represent the bottom of a selected row. 29. The system of claim 28, characterized in that the means for locating a line of patterns further comprises means to store the pattern signals representing the top of a selected line and the bottom of a selected line Represent line. 30. System according to claim 29, characterized in that the means for searching for a line of patterns further comprises a line position logic to select the pattern of signals forming a line for transmission to the receiving means represent. 31. System according to claim 30, characterized in that the Means for storing comprise means responsive to a plurality of samples to store the sample data signals in condense a single search segment. 70 in? / ♦ / 0844