DE2655829A1 - HIERARCHICAL STORAGE ARRANGEMENT - Google Patents

Description

** lw / bm

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Official file number: New registration File number of the applicant: PO 974 023 / PO 974 024

Hierarchical storage arrangement

Hierarchical storage with monolithic storage elements in the higher levels led to faster and more economical Storage systems, however, also have their drawbacks. Hierarchical systems in particular have considerable communication problems between the hierarchy levels and the volatile monolithic memories in the higher levels of the hierarchy result in problems data integrity resulting from its dependency and sensitivity to or for failures and fluctuations in the power supply result. One solution to the integrity problem would be to use two storage units at each tier, each with contains a duplicate of the data at that level, so that in the event of a failure in one memory, the data from the other Memory could be reproduced. While this improves independence, it also poses communication problems between the stages is by no means resolved and, moreover, in the event of a failure that makes it necessary to switch off the memory or forces for the transfer of the duplicated data from the memory levels containing the volatile memory to the levels which contain non-volatile memories require more time than is desired in the process of switching off the memory system and is actually sometimes available before the failure leads to the destruction of the data.

According to an older proposal by the applicant (P 25 23 414), data integrity is obtained with new copy-back techniques, and that Communication problem became due to the use of new

Copy-back algorithms in conjunction with new copy-back techniques simplified. The new hierarchical storage system has two storage units at each level, one of which has all data on this The storage level contains and the other only the changes made to this data either through additions or changes became. While the first or data storage unit with the next higher level in the hierarchical storage system or with is in communication with the processing units for the data processing system, the second or copy-back storage unit may use the Changes made in the data are transferred to the next lower level in the memory hierarchy if the copy-back memory is free and the main storage unit in the next lower level is not busy with the data transfer upwards. By Duplicate only the changed data and copy back the changes to the data at lower levels when the opportunity arises offers, the amount of data to be moved in the event of an error is kept very small, thus reducing the time that is required to move data in the event of a failure. In addition, the data store and the copy-back data store hang up each level on two different power systems, so that if one power system fails, a complete directory of the data is obtained remain.

In the arrangement described above, however, there is the copy back data memory at a given level is the same size as the data store at that level, so in this case the copy-back technique has the same effect on memory as duplicating all data at each level, i.e. there are twice as many memory elements required at every level of the hierarchy without increasing the capacity of the memory.

The invention is based on the object of the speed and Increase the effectiveness of retransmissions.

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According to the invention, this object is achieved by the characterizing features of the main claim.

The invention has the advantage that less storage space is required will. This saving is by no means due to the necessary, adaptive additive in the retransmission devices.

Advantageous further developments of the invention are set out in the subclaims refer to.

An embodiment of the invention is shown in the drawings and is described in more detail below.

Show it

1 shows a generalized schematic diagram

memory hierarchy employing the present invention,

Fig. 2 is a block diagram showing details of the first

Level of the memory hierarchy shown in Fig. 1,

3 shows in a block diagram the second stage of the in

Fig. 1 shown memory hierarchy,

4 shows a journal directory in a schematic diagram,

which is shown in Fig. 2 in the block diagram,

Fig. 5 is a schematic diagram of the circuit for generating

a copy back command signal for the memory hierarchy shown in FIG. 2,

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6 shows, in a block diagram, details of the copy-back

Forcing circuit in Fig. 2,

7 shows the third, fourth and fourth in a schematic diagram

fifth level of the memory hierarchy shown in FIG. 1 and

Fig. 8 in a sketch the format for addressing the

fourth and fifth stages.

Fig. 1 shows a multi-processor system with a hierarchical memory using the present invention. The memory is divided into two halves, the Α-system and the B system is called. Each storage system is a separate availability axis of hierarchical storage, i.e., data is moved along the availability axis is processed independently of the other availability axis and transmitted upwards and downwards. aside from that Systems A and B are independently powered and designed to prevent loss of whole or part one system does not bring down the other system. Each half The system includes a number of program processing units or PPU's 10 and a process control unit or PCU 12. Each Processor 10 has its own L1 memory 14 (memo memory) and an associated L1 directory and controller 16. In addition there is an L1 copyback data store at level 1 for each processor 18 (CBDS) and an L1 journal and controller 20. For the sake of simplicity of FIG. 1, the L1 copy back memory 14 is and the journal for the PPU 1 next to the memo 14 A for PPU 1 shown. However, for reasons of reliability and recovery, the copy back memory and journal for a PPU in the Α-half of the system with the PPU's on the B-half of the Systems packed together and vice versa.

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Any change made by a PPU stored in its memo memory is written to the L1 memory and the L1 copy back memory set for their system half for communication between the PPUs and a multi-level hierarchical memory with levels L2 / 3, L4 and L5. Data is transferred to memo memory 14 through the hierarchy from level L5 and changes the data is sent back down the hierarchy from level L1 to level L5.

There are two L2 / 3 controls 22 and 24, which are identical in design, for data transmission between levels L1 and L2 / L3 are in normal operation, i.e. when they both work properly but take on independent tasks. The controller 22 takes care of the page up function, i.e. as soon as a processor or PPU requests data that is not in the note memory, takes care of the Controller 22 retrieves the requested data from the relevant L2 / 3 basic memory module (BSM) and forwards the data upwards into the Memo memory (L1) of the requesting processor. In normal operation, the address is sent to the L2 / 3 controller 22A via the right one or left 8-byte address bus 26 or 28, while the BCU (bus control unit) 22B receives the requested data on the right or left 8-byte data bus 30 or 32. In normal operation, the page up control takes care of it 22 for moving the data to the storage hierarchy from level L2 / 3 to level L1.

In contrast, the controller 24 handles data movement in the opposite direction. The so-called copy-back control 24 takes over copying back new or changed data from the CBDS L / l to level L2 / 3. While the controls are in normal operation have different functions, if one controller fails, they can take over the task of the other.

At level L2 / L3, the storage capacity is divided into storage units, which are called basic storage modules or BSMs 34. The BSM ¹ S A1, A2, A3, A4, A5 and B are physical

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packed together and lie in the A availability axis of the system while the BSM ¹ s B1, B2, B3, B4, B5 and A are physically packed together and lie in the B availability axis. The BSM ¹ s A1 to A5 and B1 to B5 are the output points of the data that are on L2 / 3, while the BSM B contains all changes that have been made to data in the BSM ¹ s B1 to B5, and the BSM A contains all changes made to the data in BSM ¹ S A1 to A5.

The last two stages are electromechanical devices, ie stage L4 consists of stacks of discs 38 while stage L5 consists of a tape cartridge unit 40. These units 42 and 44 are interconnected by \ the circuit loops, namely "shall mean any unit by the two loops by means of the! Loops connected to another controller 46 or 48. The ! Disk units are divided between the availability axis A and B: and the tape unit lies in half of the availability axis B, as shown, with one of the stations being controlled by the availability axis A.

With this arrangement, data are copied from level L1 to level L2 / L3 as soon as data memory 14B is free for level L2 / L3 and the processor is not activating its note memory. | The changed data can then be moved from the copy support memory of level L1 into the data memory of level L2. In the same way, data are copied back from level L2 / L3 to level L4, while the memory on level L2 / L3 is free, etc. The changes to the data are copied back in the order in which they were entered in journal 20 was entered, whereby the oldest entry in the journal is copied back first. or in other words, the data j unchanged longest (LRFM) are copied back first, as soon as the opportunity \ digestion unit has it. In this way, data is effectively copied back to maintain a data pyramid without disrupting the upward movement of the data in the hierarchy. A data pyramid is the fact that data at a given level is only allowed if a copy of the data is at a

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Lower level exists and on lower levels to education a data pyramid is copied back.

• Changed data cannot only be copied down in the hierarchy in order to maintain the data pyramid / but they can also be removed from a level and reduced in the hierarchy. ; moved upwards to make room for new data. Before changed data can be moved down in the hierarchy, they must be at the top of the data pyramid or in the top position, i.e. the data to be moved down must not be at a level that is higher in the hierarchy than the level from which they are taken. Through this, that only the top or top position in the pyramid may be rolled back or overlaid, holes in the pyramid should be switched off, since this allows the use of journal management ■ and the copyback technique of the present invention is simplified. ! Of course, unchanged data do not need to be copied backwards to make room for new data, but they need it only to be overlaid by the new data, since a copy of the unchanged data already exists at lower levels.

With the current shielding shown by the dashed line 50 » tion that separates systems A and B from one another, together with the journal and copy-back technology described, the integrity of the data backed up. Current shielding is understood to mean that all devices on one side of the dashed line 50 from one Power supply are fed while all devices on the other side of line 50 are powered by a different power supply will. In addition, at the latest in level L5 of the storage system, the data is stored in a non-volatile storage medium such as duplicated on a magnetic tape. A failure of the power supply of system A or B therefore does not destroy the integrity of the data, since all data are held at least at level L5 in a medium that is insensitive to such a failure. Any changes made to the data stored in stage L5 are also on both sides of the shield 50

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at least one of the other stages L1 to L4 is present. The data can therefore be copied back down the hierarchy using the system that still has power to clean the Update the database at level L5. As a last precaution battery power can still be used in the event that the mains power supply fails for both systems, in order to store data in the copy-back memory and to keep in journal 20 at all levels where the storage medium is volatile, and also at all levels Move data down the data pyramid to a level where the data is stored in a non-volatile medium.

The level L1 of the memory hierarchy shown in FIG. 1 is in Fig. 2 reproduced in detail. The L1 level directory 16A stores the virtual addresses in groups of four for everyone in level L1 of the memory hierarchy at a given moment standing data. The four addresses in a group are called a congruence class, the address of which is determined in level L1 by the exclusive-OR-link certain virtually one address bit with real address bits from the address register 51 in the exclusive OR circuit 52. The output β of the exclusive OR circuit is on given the decoder input of directory 16A to navigate to the directory. When the directory is driven this way four addresses of a congruence class are read out of the directory in parallel. Each read from directory 16A virtual address is compared in a comparator circuit 54 with the virtual address that is used to generate the 3 addressing of directory 16A of level L1 was used. If one of the addresses read from the directory 16A with the The comparator circuit supplies the requested virtual address an output signal of two bits indicating which of the four addresses read from the directory corresponds to the searched address matches. This two-bit signal becomes one operating on the output of the first stage data memory 14A Decoder supplied. The data memory 14A stores all data in the first stage and is via its input decoder addressed by the same signal β as directory 16A

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and then reads out the data at the four virtual addresses in the congruence class. The two-bit comparison signal one-out of four then selects the data from a virtual address of its congruence class for reading out and returning to the program processing * unit 1OA based on the data request. The other two bits for addressing the memory L1 the two address bits are from the address register,

If it turns out that the data is not in the first stage L1, it must be fetched from the second stage L2 / L3. The address in register 51 is therefore transferred to the address bus 26 for the purpose of transfer to the memory L2 / L3, if ^! the comparator circuit 54 does not provide a match output signal. As shown in FIG. 3, the second level L2 / L3 contains a directory 56 like the first level L1. Since the second level stores more data than the first, the directory must be larger. The entry to this directory is thus a larger signal with more bits for selecting the congruence class of the four virtual addresses. This signal "V" is also generated by an exclusive OR circuit 58. The directory 56 is addressed by the signal γ and supplies a real location in the memory in stage L2 / L3, where the data is found As will be seen below, the directory is part of main memory and is therefore relatively slow. There is also a directory look-up table (DLAT) 60 which is faster than the directory and contains translations of some recently used virtual addresses. t) The DLAT 60 is addressed at the same time as the directory, and if the address is in the DLAT, it is accessed more quickly.

According to the illustration in FIGS. 2 and 4, the PP1 supplies a write control signal to switch gate 66 when data is in the memory system are to be written to the output of the circuit 52 in the search address register 68 of the Li Journal 2OA. The journal 2OA is j

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Associative memory. An associative memory is searched by comparing the virtual address with the virtual address stored in the journal. If the virtual address in the search address is the same as that in the journal, the journal or the associative memory 20A supplies a comparison signal which indicates that the address is stored in the journal or, in other words, that the data at this address has previously been changed. If no match signal occurs, it means that the data at that address has not previously been changed and an entry is then made in both journal 20A and copy-back data store 18A to indicate that the address is now being changed. The location of the virtual address is entered in the journal and the copyback memory 18A provides an indication of the order in which the change was made and the address in the journal and copyback memory determine that order in which the change is copied back to the lower levels. For this purpose, a counter 70 counts down each address of the journal 20A and CBDS 18A in sequence. If a mismatch signal is provided by the hit register of journal 20A in conjunction with a PPU write signal, the output of counter 70 is passed through AND gates 72 to select one of the m words in journal 20 and CBDS 18. At the same time, the _virtual: input address in the search register 68 through the AND gate 74 in the journal i and the address and data from the PPU 1OA be entered in the CBDS 18A at the specified location by the counter. The data change is of course also input into the L1 memory 14A.

When the journal entry is complete, the counter is reset to the next number in the addressing sequence by an end of entry signal ΪΓ2 connected upstream. That way, everyone in the journal and in the Entry made by CBDS is placed in an order in which the change in the data is first made by the programming processing unit 10A was requested, so that when data is copied back, it can be copied back in the order in which the Entries were made in the journal by simply

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j controls the addresses in the journal in numerical order. {This is done via the copy-back counter 76, which is determined by the addresses ] in Journal 2OA and in CBDS 18A runs in the order in which they were journaled first, and so will the changes copied back to the lower levels. This includes that! Regardless of the number of changes made to the data each candidate for copy back is formed from the data that has been unchanged the longest. These are the dates whose first entry is in Journal 2OA and CBDS 18A for the longest time, ; and which are most likely not to be changed again by the processor | 10A. The copy back counter 76 is always behind the counter 70 and points to the next candidate to copy back from L1 to L2 / 3. Once the processor 10A has data in its L1 memory 14 not changed and the L1 directory 16A free a cycle for copying back from L1 to L2 / 3 can run. Then the circuits in Fig. 5 give the contents of the copy back counter into the SAR of the CBDS to get the virtual address and 16 modified data bytes. The copy back command is sent to the Copy back control L2 / 3 given. After the entry from the copy back memory 18A of level L1 has been copied back to the level L2 / L3 data and copyback memories and the data changes have accordingly been noted in the journal of L2 / L3, a data signal T1 is applied to the copy-back counter 76 in order to add it to the to switch to the next position. If the conditions for copying back data are still there, the CBDS will be 18 again controlled and the data at the next address in the CBDS 18A in | the next level data and copyback memories are copied back.

The journal 18A also stores in addition to the virtual address Valid bit that is switched on when an entry is made in the journal at the beginning. From Fig. 4 it can be seen that How a valid bit is entered into the search arrangement of the journal directory 2OA. When the PPU 1OA a write command for writing to a virtual address, the virtual address is loaded into the search / write register 68. The search / write register is one bit larger than the loaded virtual address and,

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when the virtual address is entered, it will be the last position or the Y position of the search register is forced to logical 1 »

As has already been shown above, the entire search arrangement 20A is queried at the same time. If the contents of the SearchZ write register 68 matches one of the words of the arrangement bit by bit, only one of the drivers 80 is switched on. Every activated driver delivers a hit signal that indicates that the data has been changed before and that an entry has already been made in the journal and in the Journal directory was made. If none of the drivers 80 is switched on, no hit is displayed either, i.e. it An entry must be made in Journal 20 and CBDS 18A will. For this purpose, the counter 70 is connected upstream in such a way that it controls the next available word in the arrangement 18. Simultaneously the write switching element is prepared so that the content of the SearchZ write register is in the position addressed by the counter is written.

When the data is eventually copied back, journal 20A must reflect the fact that the page is in L1 data storage 14A no longer differs from the copy in the L2 data store 34 differs. For this purpose, the hit address is used at copy-back time in the search arrangement in the match address bars and the validity bit in the SearchZ write register to invalid or lo-.

igisch zero. In the writing part of the cycle, the matching j ^ dreßverriegelungen for addressing the search group. '

The content of the SearchZ write register is written into the addressing racks. The disabled valid bit prevents you Compare in a virtual address search of the arrangement the next time it is searched. The ones in this and others Figures of the specification clock signals T shown by a conventional clock circuit in the associated with the signal Sequence generated.

Two types of copy back are possible; Copy back according to normal retrieval, i.e. when data has been changed and this is in

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copied back to the next opportunity and forced copy back4 A forced copy back is a copy back that i not in the order of the longest unchanged copy back; algorithm is done. That is the algorithm that goes through the journal 2OA through its addresses in sequence is issued by the copy back counter 76. If a forced Copying back takes place, the valid bit is removed from the journal 2OA as during a regular copying back, to indicate to the copyback mechanism that the data has already been copied back and should not be repeated.

Forced copy back occurs for a number of reasons. It is done first if data are to be used in a congruence class in which the data has been changed on all virtual addresses \ in the congruence class and the changes have not yet been copied back. In order to determine whether a forced copying back must take place for this reason, the directory 16A contains four status bits, one each for an address in the congruence class. The status bits are set by the status bit Fortschreibe- \ circuit which is shown in detail in Fig. 6. As soon as ^! If states are either changed or copied back, this circuit changes the status bits to reflect this fact. ! The status bit circuit also contains the AND gate 82. If the ^! Output in the directory contains four ones, indicating that j data has been changed at all addresses in a certain congruence class and a signal for mismatch indicates j that the data is not stored somewhere on the level! A copyback force signal is generated by this AND gate 58 when a new entry is made at this address by a circuit described above. j

A second reason for achieving copy back is overflow! the CBDS 18A and the Journal 2OA. These have only 1/6 of the positions of the data memory 14 and therefore with the help of an i Journal fill counter 84 ensures that the next free space in counter 70 does not overflow the copy back counter and overlap! Entries in the journal on the CBDS begins that have not yet been copied back became. Journal fill register 84 is a two-way H

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counter showing the number of m sections in the journal and in the CBDS
that are used and not copied back. When a
certain percentage of these sections falls into this category, t the journal filling counter issues a copy-back regeneration command to ι the circuit shown in FIG. 6 for a copy-back operation; initiate. For example, it can be beneficial to have copy back requests
to submit when the journal reaches 90% of its threshold
Capacity reached and copy back cycles to continue until 60%

the capacity are reached. This allows lines of data to repeat |

modified before copying back to L2 / 3 and thereby the reverse; Copy traffic to L2 / 3 can be reduced. j

The machine equipment for journaling and copying back at level L2 / 3 is shown in FIG. Directory Page Lookup Table (DLAT) 60 consists of high speed technology relative to Main Storage Directory (MSD) 56, which is the same MSD as controller 22 and controller 24. The MSD is contained in memory L2 / 3. Except- ; there is also an L2 / 3 journal 88 of all modifications to be made at level L2 / 3 by copying back from L1, CBDS 18 or from j source / sink to L2 / 3. \

Finally, there are two lists of pages in L2 / 3 memory that
reserved for copyback purposes and free copyback list. [A and B are named. If the address of the modified data
If a BSM is in half A of the system, the return copy side is assigned by CBFL for the B half of the system and vice versa.

{Now assume that a copyback command from the L1 copyback controller is given to the L2 / 3 copy back controller 22. The of '

L1 CBDS 18A fetched virtual address is given to the L2 / 3 control>! 22B via the L1 CB address trunk and the DLAT 60 becomes
'searched. It is assumed that a match is not achieved in the DLAT. The MSD 56 is then searched and one must
Comparison situation, since everyone in the L2 / 3 level is

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is shown by the MSD 56 on the following pages. The real output address the page is indicated by the registration office in the MSD 56, if there is a comparison between the virtual address given by L1 CBDS and the virtual address field in the MSD. If the CBRA entries and the next free space pointer entry in the MSD are zero, it is assumed that the first update should be on a line of the page at L2 / 3 relative to its copy in L4. The virtual address and HRA are used by MSD read and placed in the DLAT 60 together with the content of the next free space counter 92 (NFS CTR). As it is the first modification a CBRA allocated before the CBRA table is also placed in the DLAT. At the same time, the virtual address and the CBRA is placed in the L2 / 3 journal 88 at the location pointed to by the NFS CTR 92 concatenated with the main storage address offset. Since the lines of modified data in L1 CBDS is 16 bytes and the page size on L2 / 3 is 2KB, the Lower seven bits (D16 to D1O24) are decoded to determine which 16 of the 128 bytes are modified in the 2K side. The result of this bit code is also entered in the L2 / 3 journal 88 written in the area designated as the restart bit directory.

The implied HRA in MSD and the associated CBRA are placed in the L2 / 3 copyback queue of the L2 / 3 copyback controller. ' When the copy back queue is serviced, the 16 bytes of modified data in L1 CBDS are written to L2 / 3 HRA and CBRA.

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It is assumed that a copy-back command in the stage L2 / 3 · and a DLAT error occurs, but a valid CBRA entry in the MSD 56. A valid CBRA entry means the ninth modification for a page in L2 / 3 relative to its copy in level L4. Since this is the ninth modification for one side, the CBRA has already been assigned. The virtual ad-> resse, CBRA, and the included HRA are transmitted from the MSD to DLAT. The CBRA and HRA are also put on the L2 / 3 copy back control queue set. When the copy back queue

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is operated, the modified data is written in L1 CBDS 18A in L2 / 3 from HRA and CBRA.

The next free space pointer field from the MSD is set in the journal SAR. The virtual address CBRA and the repetition bit map are fetched and saved. The validity bit is made invalid in the restore cycle. The virtual address CBRA and the repetition bit map are then stored back in the position in the L2 / 3 journal 88 to which the contents of the next free space counter 92 shows. The journal list has thus been rearranged. (It should be noted that the content of the next free space counter was also stored in the DLAT 60 when the virtual address CBRA and HRA were transferred from the MSD 56 to the DLAT 60)

In the case of subsequent modifications, the journal is rearranged in such a way that a certain filtering of the copying back from L2 / 3 to L4 takes place, which is a much slower device. An LRU copyback algorithm would provide the highest level of filtering in applications where the modification rates for a given page are high are. However, when slow memories are concerned, the implementation of LRU requires significantly more overall hardware effort and in time relative to the copy back algorithm to be described.

the latter case, the case in this section is considered in which a copy back command on L2 / 3 and a DLAT comparison exist. jA DLAT comparison always contains the ninth modification for a Page at level L2 / 3 since the last update from level L2 / 3 to level L4. The HRA and CBRA go into the L2 / 3 copy back control queue set. When the copy-back queue is serviced, the modified data in L1 CBDS written according to L2 / 3 HRA and CBRA.

The rearrangement of the journal entry according to the page to be copied back is carried out exactly as described above. the fourth and fifth levels of memory are magnetic and become

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referred to as the disk or tape archive level. The fourth stage! includes disk drives 38 with four actuators A, B, C and D: per drive, each of which controls an assigned group of cylinders.

The archive level or fifth level of storage is a cassette tape device 40 with a plurality of stations 164 for reading a tape 100 in cassette form. The drives 38 and 40 are connected to a controller 46 or 48 connected via a serial loop interface 42 or 44. Multiple disk and tape drives 38 and 40 are connected to each loop. The second loop 48 is for availability connected to the same disk and tape units as the first loop 46.

Data is recorded at the disk level in segments that contain one or more pages. If there is room for!

a given segment size is assigned, the physical j

Address of this allocated room as the output address of this ■ Segment denotes as long as this segment lies on the disk step j. The plate print copy area is on a barrel! factory 38, on which the output address is not recorded. There-!

This enables restart if the drive with the j output address fails. Fig. 1 shows how the output address data | and its copy back data on different drives [lie. All cylinders of actuator A of drive 38A are! and are designated as copy-back area B. Up here ^one plotted data are new and modified data for the training! Input address areas for the spindles of half B of the system. | The second copy-back area A is on the actuator A of the mechanism 38B.

All registrations that are down from level 3 of the memory! are either new or modified data for the disk level. Each writing on the disk is recorded twice. The page in the output address area is overlaid or assigned depending on whether it is new or modified. The same page is also recorded in the copy back area.

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The copyback actuator shown in Fig. 7 must have a write rate _; that is equal to the sum of all write rates on all other drives without losing performance. To meet this requirement, a buffer area 102 is provided for the CB memory. While the HA area 104 is being written, the pages are also buffered in main memory. Sufficient buffering is provided so that the CB actuator can write one data track at a time. In fact, two such buffers are provided. When the first buffer is unloaded (first disk revolution) the second can be loaded. The pages are placed in the buffers in the order in which they come from L2 / 3 to stage L4 as they are recorded at the home address. When the buffer is full, the L4 copy back memory begins recording data stored in the buffer | on track 1, cylinder 1, then track 2 of cylinder 1, track 3, etc. When the last track of cylinder 1 has been written, the actuator moves to cylinder 2, etc. Since this is the sequential type of writing, the physical address is where the 2K j page is written on the disk is predetermined when it is placed in the track buffer. As already mentioned, all data copied back to the disk come from the output address area L2 / 3. For the sake of ease of illustration, the capacity of the copy back cylinder is given as 60 pages. The example shows 3 tracks per cylinder and 2 pages per track. ^;

A bit map 106 is provided to provide space in the copy back area assign and reclaim. The bit map is in main memory and contains one bit for each page section in the Copy back area. Each cylinder (6 pages) is represented by 6 bits in the dictionary. The first bit line in the directory is for the cylinder 1, the first bit represents the track 1, record 1 and the last bit represents track 3, record 2. At the point in time at which a page is placed in the track buffer, the corresponding Bit in the bit map set to 1, indicating that it is being used.

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The two track buffers mentioned above therefore each contain two pages ! (Track buffers 1 and 2). In the example it is shown that 7 pages belong to 7 different segments which are copied back to the disk stage are. The pages are labeled with the letters A to G and represent the virtual address of these 7 pages.

When the L2 / 3 copyback control determines that a page is to be copied back to the disk, it issues a copyback command and sends the virtual address to the L4 / 5 control. This addresses the main memory directory (MSD) with the virtual Address. The status in the MSD indicates to the disk level whether this page is new or modified. If it is new, the L4 / 5 control must Allocate space for the entire segment. The size of the segment must be known in order to allocate enough space on the disk can be. The size information is available in the segment control block, which contains all information about this segment. Any room allocation facility on the plate is sufficient for this example. If the physical space (HA) for this Segment is now available, an entry is made in the disk directory, the position, size, etc. of this segment indicates.

If the MSD status indicates that the page is not new, only [is modified, the disk directory is searched to determine the starting address. The output address is activated and the 2K side is superimposed with the modified 2K block from level L2 / L3.

Any 2K block written in the home address space of the disk is also placed in the copy back buffer area in main memory. It is assumed that virtual addresses A and B contain the first modified pages to be copied back. The virtual Address A is placed in track buffer 1 and because it is recorded in cylinder 1, track 1, record 1, the first bit in the Cylinder bit directory set to a 1. The virtual address A can now be written to the disk output address.

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All enrollments that come down from level 3 of the store, is either new or modified data for the disk level. Each writing on the disk is recorded twice. The page in the output address area is overlaid or allocated depending on whether it is new or modified. Same Page is also recorded in the copy back area.

The copyback actuator shown in Figure 7 must maintain a write rate equal to the sum of all the write rates on all of the others Drives without sacrificing performance. To meet this requirement, a buffer area 102 is provided for the CB memory. While the HA area 104 is being written, the pages are also buffered in main memory. Sufficient buffering is provided so that the CB actuator is one data track at a time can write. In fact, two such buffers are provided. When the first buffer is unloaded (first disk revolution) it can the second to be loaded. The pages are placed in the buffers in the order in which they come from L2 / 3 to stage L4 while they are recorded at the home address. When the buffer is full, the L4 copy back memory starts recording of data that is stored in the buffer on track 1 cylinder 1, then track 2 of cylinder 1, track 3 etc. When the last track of cylinder 1 has been written, the actuator moves to the cylinder 2 etc. Because writing is done in this sequential fashion, it is the physical address where the 2K page is written on the disk is given when it is placed in the track buffer. As I said, all the data copied back to the disk comes from the output address area L2 / 3. For the sake of ease of illustration, the capacity of the copy back cylinder is given as 60 pages. The example shows 3 tracks per cylinder and 2 pages per track.

A bitmap 106 is provided to provide space in the copy back area to open and reclaim. The bit map is in main memory and contains one bit for each page section in the Copy back area. Each cylinder (6 pages) is represented by 6 bits in the dictionary. The first line of text in the directory is for

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cylinder 1. The first bit represents track 1, record 1 and the last bit represents track 3 Record 2. At the point in time at which a page is placed in the track buffer, the corresponding Bit in the bit map set to one, indicating that it is in use will.

The two track buffers mentioned above therefore each contain 2 pages (track buffers 1 and 2). In the example it is shown that 7 pages belong to 7 different segments that are to be copied back to the disk level. The sides are with the letters A through G. and represent the virtual address of these 7 pages.

When the L2 / 3 copyback control determines that a page is to be copied back to the disk, it issues a copyback command and sends the virtual address to the L4 / 5 control. These addresses the main memory directory (MSD) with the virtual address. The status in the MSD indicates to the disk level whether this

Page is new or modified. If it is new, the L4 / 5 control must allocate space for the entire segment. The size of the segment must be known so that sufficient space can be allocated on the disk. The size information is available in the segment control block, which contains all information about this segment. Any room allocation facility on the plate is sufficient for this example. If the physical space (HA) is now provided for this segment available disk directory an entry is made, the location, size, etc. of this segment ". Mentes indicates.

If the MSD status indicates that the page is not new but only modified, the disk directory is searched for the To determine the output address. The output address is am-controlled and the 2K side with the modified 2K block from level L2 / L3 superimposed.

Each 2K block written in the output address range of the disk is also placed in the copy back buffer area in main memory, j

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It is assumed that virtual addresses A and B contain the first modified pages to be copied back. The virtual Address A is placed in track buffer 1 and because it is recorded in cylinder 1, track 1, record 1, the first bit in the Cylinder bit map set to a one. The virtual; Address A can now be written to the disk output address will. When B is signaled to copy back, the same routine runs, but the second bit of the bit map of the

ι cylinder 1 set to one.

The track buffer 1 is full (contains A and B) at this time. The L4 / 5 controller initiates a write to the copy back actuator and records pages A and B on track 1 of cylinder 1. During this time, copy back commands for virtual addresses C and D are initiated and placed in track buffer 2 while . the buffer 1 is discharged. While C and D are described ^,! E and F are placed in buffer 1. After E and F have been written on the last i track of cylinder 1, the actuator moves to track 2. ί

Fig. 8 shows in detail the information contained in a block. Each data block (also in the copy back area) contains the physical address (cylinder number, track number, record number). ι The physical address and the subsequent data field are separated by a gap. The data field contains different information than that actual data bytes. The virtual address is followed by a pointer (3 bytes) to the other copy of this page in the L4 copy-back area designated. This copyback address was determined at the time the page was placed in the track buffer prior to ! Writing the output address. In Fig. 7, the content of the Zei-ί gers with the data for virtual address A on drive 5. The notation 1-1-1 denotes the physical address the other copy in the copy back memory (cylinder 1, track 1, record 1).

'These pointers are not used until more than one change is made the same side is carried out «During a cycle in reverse

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copy memory and the sequential movement of cylinders 1 through 334, a given page can be modified more than once. With every change or modification a new copy back address is assigned and therefore the previous change becomes invalid by changing the bit map accordingly. By changing the bit directory (switching the bit from 1 to 0), this change is not recorded on the next memory level when the copy-back area is passed through the next time. The directory bit is changed as follows. Assume that a read command to virtual address A follows its first modification to disk. The second time A is read into main memory, it is labeled ^{A 1.} A ¹ is assigned to an MSD entry and the copy back pointer (1-1-1) also becomes

registered in MSD. The next time A 'is modified, MSD is addressed and the pointer read out. This pointer gives the relevant bit in the directory, which is to be changed to zero. In this case it is the first bit of the cylinder's bitmap 1.

The copy-back actuator is now located on cylinder 2. If A ¹ is copied back, we want to assume that A ^{1 is written} to cylinder 2, track 1, record 2 and the initial address position is 2-1-2 in the pointer field. This pointer indicates the location of the last change to the block on the copy back drive. Fig. 7 also shows two modifications for block E. The first modification in the copy back was recorded on cylinder 1, track 3,! Record 1. The second modification is at 2-2-2. During sequential

is partially written through the copy back area, copies become '·. of blocks that have been changed more than once deleted from the previous ι cylinders. An automatic LRU algorithm is built into this technology.

Data to be recorded on the tape drive comes from the copy back area the plate. The LRU algorithm built into the disk copy back mechanism determines the side to be recorded on the tape is. The recording on the tape begins after it is created

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Cycle through the plate back-copy area (i.e., the copy-back actuator has written the last track of cylinder 334 and is returning to cylinder 1). When the actuator is on the cylinder 1, the first step is to determine which one 2K page is recorded by querying the bit map for cylinder 1. Those 2K pages, their associated Bits in the directory of cylinder 1 are at logical one, must be recorded. These pages are then starting at Track 1 read and placed in a tape buffer in main memory. The pages are written to the tape from the tape buffer area. Track 1 is now free for other pages to be written from L3. When each sequential track is unloaded into the tape buffer, it is filled again with data from L3.

All data recorded or copied back to the tape for a given segment is identified by an entry in the tape directory * nis that lies on the plate step. The cartridge that recorded the data is a different cartridge than the one on which the data are recorded at the HA. We therefore end the operation with two copies of the segments on the tape stage hike. Data to be extracted from the disk level exit address are determined by an LRü algorithm. Wear all segments a timestamp and the oldest pages (not attracted) diverted. Since the output address area is much larger than the copy-back area, data remains longer at the output address, resse than in the copy back area.

The tape device can have two or more read / write stations (we assume four). When data is directed onto the tape, it can be recorded on an inserted cassette, what as with the plate, it is most expediently done sequentially. If one of the two cassettes on which the segment is recorded if, fails, the segment can be reconstructed from the other cassette.

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Restart, reconfiguration and data reconstruction from a directory or memory failure take place via the recording and copy back. Error detection is a prerequisite for any troubleshooting routine. Every directory and every memory therefore have as a minimum one SEC / DED unit (single error correction, The use of powerful correction codes is a function of the types of errors of the completed storage technologies,

From Fig. 1 it can be seen that every detected error outside the: Correction possibility of the unit to this memory or directory is a trigger for the error repetition. Assuming first that the memory at level N is defective and the directory is in order, the incorrect memory address is fetched from the directory and the directory status bit is used to determine whether the data has been changed. If this is not the case, the directory entry is marked as invalid for the physical location in memory in order to prohibit its future use. Since the data has not been changed exi- | A running copy stares at level N-1 and can be passed up to level N. '

If the memory fails and the directory is fine, but the directory indicates that the data has been changed, the journal is searched at level N-1 with the virtual address (HD) by the requesting processor. A copy back of N-1 j after N is forced and thereby the copy on level N up; brought up to date. The reconstructed data at level N is then passed up to level N-1.

If the directory fails, the status of the addressed data is not known. The directory entry is for future Use is marked as invalid and the physical address of the faulty location is diverted. As in the previous paragraph the journal is searched, a copy back is forced and the reconstructed data is transferred from level N to a

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Place in level N-1.

The MSD is used to continue working after journal failures as follows. The MSD is searched sequentially. As soon a valid CBRA occurs, a copy back must be forced. However, since the journal retry bitmap has been lost can be, the copying back from L2 / 3 to L4 takes place from the output address L2 / 3 to the output address L4. Once everyone changed or modified data has been copied back, the copy-back control is switched off from the system as its journal is faulty.

In summary, the above embodiment of the invention represent as follows:

The copy back techniques are applied to the magnetic disk and tape stages of memory applied. The disk and tape drives are in series with one another through several independent access loops tied together. These loops are powered by two different power systems so that data transfers to the lowest Levels on one loop can continue to run in the event of a power failure on the other loop. The copy back algorithm will modified accordingly through the use of buffers. Changes to be copied back to the lower levels are stored in the buffer stored until the track value of a disk has been accumulated with changes. Then the copying back to the disk plane initiated. This is an order in which the write rate in the copy-back area of the disk matches the rate the other areas of the plates should be lifted.

At the higher levels of the hierarchy, the capacity of a copy-back data store becomes part of the corresponding data store reduced and made an ongoing check of the number of entries in this copy back memory that are still were not copied back. When the number of these entries approaches the capacity of the copy back memory, they all become

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Functions of the memory, the new entries in this copy-back memory promote, paused and the copy back of changes listed in this copy back store receives the top priority. This operation then continues until the number of uncopied return entries in the copyback data memory is reduced to an acceptable level.

From a further point of view, journaling and copy-back technology become applied to multiprocessor systems. In particular, the hierarchy memory of such systems is divided into two divided with powered availability axes, each serving a different set of processors. During the During normal operation, data will move independently up and down these axes, but will be copied back on one axis Duplicated data in a copy-back data store located on the other availability axis. With this arrangement One availability axis can serve all program processing units if the other availability axis fails.

The advantages of the facility described above are the creation of a memory hierarchy for processing systems and / or multiprocessor systems that ensure data integrity without the complications of direct duplication through copy-back and Journaling techniques as well as a new transmission technique is maintained for changes in the data down the hierarchical storage system. For this purpose, a new copy-back memory -chermechanismus created in which the copy-back memory only need to have a percentage of the capacity of the total memory. In addition, the data integrity is ensured by the described Copy-back and directory techniques are ensured at the disk and tape levels of the hierarchy.

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Claims (8)

PATENT CLAIMS Hierarchical memory arrangement in which a data memory and a copy-back memory for storage in each level of processed data and journal storage devices for storing addresses of the first time changed data are provided, characterized in that the capacity of the copy back memory (18) is smaller is than the capacity of the data memories (14) of this stage and that in the retransmission devices means (Fig. 2, Fig. 7) are provided to accommodate this reduced capacity. 2. A memory device according to claim 1, characterized in that the means _r counter (70, 76, 84) for counting the already occupied and the remaining available storage locations in the copy-back memory (18). 3. Memory arrangement according to claim 2, characterized by control devices for initiating a forced retransmission, if the number of memory spaces still available falls below a previously determined minimum and to terminate the forced retransmission if the number of memory spaces still available has reached a previous level fixed maximum reached. 4. Memory arrangement according to claim 2, characterized by first addressing devices for finding memory locations in the copy-back memory for entering changed data in the journal memory (20) and by second Addressing devices aum finding addresses of data to be transmitted back and by devices for Comparison of the addresses of the two addressing devices. 5. Storage arrangement according to claim 1, with a disk storage and a magnetic tape storage in the lowest PO 974 023/04 709827 / 060Θ Level of the hierarchy, characterized by two transmission loops that work independently of one another (42, 44), which each have individual disk storage and individual tape storage optionally with a first (46) or connect to a second (48) storage management facility. 6. Memory arrangement according to claim 5, characterized in that each transmission squint from a different power supply is fed. 7. Storage arrangement according to claim 6, characterized by two specific disk units, each of which changes data of the data stored in other disk units and with other transmission loops are connected than those which transmit data to the other disk storage units, so that in the event of failure one of the two power supply devices (dividing line 50) the return transmission to the magnetic tape and disk storage devices is not prevented. 8. Memory arrangement according to claim 5, characterized by buffer storage devices (Fig. 7) for intermediate storage of data to be retransmitted to disk storage until the amount of data equals the capacity of a disk track achieved. po 974 023/4 709827/0606