DE2650972A1 - MEDIATION SYSTEM FOR BUNDLED DATA FOR A NETWORKED NETWORK - Google Patents

Description

PATENT LAWYERS

H ¹ NZ-JOACHIM HUBER REiNiR PRiETSCH *

M ö N C H E N 2 1 *

GOTTHAROSTR. 81

9177 November 8, 1976

TELECOMMUNICATIONS RADIOELECTRIQUES ET TELEPHONIQÜES T.R.T. 88, rue Brillat Savarin

75013 - Paris / France

Switching system for bundled data for a meshed network.

Priority from French patent application No. 75 34087 of November 7, 1975

The invention relates to a system for the transmission of bundled data, in particular, but not exclusively, for the formation of networks for the remote transmission of data in binary form, for telecommunication purposes.

It is known that the exchange of messages between the

709819/0342

-r-

Users of the same network is done either in real time or with a time shift. The associated switching centers use two different switching techniques, in the first case line switching and circuit switching and, in the second case, can be referred to as message switching.

Both techniques have their advantages, for example the following:

- the line switching: faster call setup, none Format restriction, dialog, clarity of the network;

- the communication: maximum load capacity, compensation of traffic peaks, multiple transmission, transmission between incompatible devices;

they also have their own peculiar disadvantages.

In the message switching systems, the switching centers are provided with memories that allow the messages to be saved temporarily until the addressee is attainable.

The technique of relaying bundled data is similar to the technique of relaying messages. This in the United Technology that has already been introduced by countries (ARPA network) also makes use of the time segment procedure. she consists in that the message to be transmitted is divided into bundles or mini-messages that have a recipient address are provided, and that these bundles by means of a message header that characterizes them via a network be directed. The bundles belonging to the same message or data group can, depending on the current Availability of connections in different ways

709819/0342

ge use. In each center that is passed through, the bundle is recorded and processed in a rapid storage system and passed on immediately. It will be erased from memory as soon as the center it was assigned to is its Receipt confirmed.

Due to its adaptability, the bundle switching technology allows the network to be operated under optimal conditions to use.

The trunked switching networks carry information that is grouped together when it comes from one and the same Exit point and approach one and the same destination point. On the one connecting the network nodes Lines follow one another bundles with different starting and destination points. At the passage the bundles are temporarily stored, processed and routed through the nodes.

There are networks for bundle switching that are operated by the Make use of the method of so-called virtual lines, in which each bundle is assigned an exchange number is provided. This number can be used to enter a number in each memory of the switching centers Table determine the characteristics of the connection. This method is used to mediate between two users or participants with the same phases as in the line switching, namely:

- production (i.e. writing of the characteristic values in the memory),

- Conversation,

- Termination of the connection.

709819/0342

The simplicity of branching the bundle by simple Querying a table in direct access enables the connection to be established particularly quickly.

There is no problem restoring the order of the bundles in which they were sent. One therefore needs no special storage devices are to be provided at the exit in order to guarantee the transmission to the recipient.

The invention relates to a system for the bundle switching of data using the virtual method Addressing.

In such systems, which are implemented in special networks, the connection is made by remote switching computers produced, which at the same time the functions of an analysis of the information on the bundles and the transport take over.

The relatively inexpensive computers are arranged hierarchically so that they divide the telecommunications traffic and Exchange information. However, as the number of simultaneous connections increases, the number of Computer increase at least proportionally, which increases the costs of the plant and its operation considerably. at a limited number of computers very soon encounter difficult problems or public resource allocation. On the other hand, such a system cannot cope with the traffic peaks when there is a large number of subscribers at the same time are connected to a network.

The system forming the subject of the present invention is characterized in that the switching radio

709819/0342

tionentionen and the functions of the manufacture and the Supervision of conversations carried out by separate bodies. This separation of functions is common with direct dial telephone services known, but no data transmission network makes use of this thought.

Sr leads to a reduction in the material required and to make better use of it.

The invention is also based on the object of a switching system of the above-mentioned type to develop the formation of a network with a large number of participants should lead with a very high brokerage performance.

For this purpose, the technology is adapted at all levels to the problems to be solved. Frequently recurring tasks are taken over by wired logic circuits while using the more complicated operations can be executed by stored programs.

On the other hand, the system makes use of micro-programming as much as possible, with the micro-programs in large programmable read-only memories (French: ä structure eclatee) can be entered.

The present system should meet the following requirements:

- clarity of the network for the participants,

- Half real time: this means that the time it takes for the The transmission of the information on the lines must be so short that a direct dialogue is possible,

- Adaptation to the approach of the participants while at the well-known messaging systems

direct must necessarily have a certain format,

- Operational safety by having a reserve system ready,

- Adaptability, i.e. the possibility of gradually expanding the network without changing its basic structure .

Further features and advantages of the invention emerge from the following description of an exemplary embodiment below With the help of the drawings that show the following:

1 shows an intermediary and concentrator;

Fig. 2 shows a module or a switching center;

3 shows a switching network;

4 shows a synchronous line adapter (ALS);

5 shows a synchronous line unit (ULS);

6 shows a common data processing system for the synchronous line units ULS, the asynchronous processing units ULA and the bundle processing stage PP;

7 shows the execution element for the synchronous line unit ULS;

8 shows an organizational diagram of a data processing system for bundles;

9 shows the incoming and outgoing checker for the data processing system for bundle;

709819/0342

Figure 10 shows the memory adapter circuit;

11 shows the connector for connecting a data processing system for bundle PP to the time bus B.T ..

In the system according to the invention, the basic unit which carries out the connection and switching functions is used as an intermediary and concentrator. The purpose of a concentrator is to connect the synchronous or asynchronous lines establish and make the necessary adjustments before passing them on to the intermediary according to a predetermined procedure and with the required structure.

Every mediator and concentrator (Fig. 1) knows at least a switching module 1 and at least one control unit on.

The entirety of the switching modules 1 will be referred to as switching chain 3 in the following. In the case of synchronous lines these modules are connected to modulator-demodulator circuits (MODEMS).

The modules 1 and the control units 2 are connected to one another by a time busbar 4. As already mentioned, the switching modules are used to establish the connection between the subscribers depending on the commands carried out by the control unit can be given.

A control unit 2 consists of a data processing device in mini size (mini processor) 21, an expandable one Memory 22 and a peripheral device 23, which is used only for maintenance work.

709819/0342

The processing power of an exchange can be increased if a larger number of control units is used, as will be described below; the system is essentially modular.

Fig. 2 shows a small center containing a connection module and a control unit. According to the invention, everyone has Intermediaries and concentrators have the same structure, only the number of modules and the programs change as a function of the orders assigned to each center.

A switching module (Fig. 2) consists of:

- at least one synchronous line adapter ALS,

- at least one synchronous line unit ULA,

- A switching link, which consists of at least one synchronous line unit ULS and at least one bundle processor PP is composed.

The bundle processor PP consists of a data input and output stage ES, a mini processor PROC and a memory adapter skreis SAM.

The memory adaptation circuit SAM is connected via an interface AM to a main memory MM which can be considerably expanded. These stages are described in detail below.

The block diagram shown in FIG. 3 shows a fully equipped switching network in which all elements are available twice to be on the safe side.

The operator module is on. the Zeitsasniaelschiene iibsr the

^ 09819/0342

Time single rail connection stage CBT connected.

The control unit UC, which does not belong to the mesh, consists from a programmable computer similar to the universal mini-computer.

The same type of computer is used for maintenance at the local PCL control points and for operating the system. The structure of the control units depends on the number of connections to be established, while the structure of the switching modules depends on the one hand on the number of connections and on the other hand on the power to be sold.

Summary description of the stages of an intermediary (Fig. 3):

- A synchronous line adapter ALS allows the information coming from the modulator-demodulator circuits (MODEMS) in the T.T.L. to be coded in order to transmit them to the line units ULS and back. A The adapter can combine up to eight lines. On the one hand, it ensures electrical adaptation to the characteristics dee network, solves the multiplex of the information on the broadcast and carries out the processes opposite to reception - the synchronous line unit ULS takes binomial sequences from ALS to which it is connected. The ULS forms the characters, carries out the redundancy check and transmits them to the bundle processor PP after processing. In the opposite direction, ULS takes from the bundle processor, to which he is connected, signs on which he transforms into consecutive binomials that he on the ALS sends. These processes are controlled by a processor and specialized operators. As an an example it should be noted that a synchronous line unit is on

709819/0342

sixteen synchronous line adapters can be connected and thus can route up to 128 lines, so that one traffic that allows more than IM binomial data input and data output.

- The asynchronous line unit ULA allows production of exchanges with parallel connections JP and the processing of characters in such a way that the trunk processor PP is offered an interface that exactly matches that offered by the ULS unit.

- the bundle processor PP receives characters from the line units, it carries out the analysis and transmits the data bundles, restores the grids that were formed by a bundle group and sends the characters to the Management units.

Two subsets of bundle processors work in parallel:

- the inputs-outputs subgroup ES, which does the exchange conducts both with the line units and with another switching module; she performs the very common operations writing or reading characters into buffer memories;

- the actual processor that analyzes the grids and the bundles.

The two subgroups are used to access the main memory the memory access circuit SAM.

The memory adaptation interface AM conducts the exchange of words (in the length of 16 binons, for example) between the bundle processors PP and the main memory MM. It has

708810/0342

- i / L -

a device for securing the addressing and the messages.

The main memory MM consists, for example, of MOS memory slots.

A line coupling of the time bus allows the Exchange of messages between the bundle processor PP and the control unit inside a certain mesh or between different meshes.

According to a feature of the system according to the invention, the messages are exchanged by MIC-coded pulse modulation. A time bus with 40 channels corresponds to a transit capacity of 80 m binons / s.

Each line terminal allows all bundle processors and all control units to be connected to a time bus of the system, which means that all C.B.T. the same structure demonstrate.

The simple and frequently recurring functions, such as the repositioning of the sent signals, the stringing of the characters to be sent out is implemented by wired microprograms to ensure high processing power to achieve.

The simple functions that require parameters, such as the recognition of special characters, parity calculations, redundancy code calculations, are made in a wired logic circuit depending on a processor.

The special functions, such as the analysis of the grid, processing the bundle, are realized by special processors, which a program contained in a high-speed memory

7098 1 9/0342

run a program.

The more general functions, such as establishing the call connections, monitoring the system, the Administration of the network is carried out by universal computers.

The operating modes of the network, i.e. the lines and the intermediaries, are based on the following principles:

- presence of multi-line connections,

- method of virtual circuits,

- regulation of the flow in the area of connections and distribute circuits,

- semi-self-adapting search of the transmission path,

- Reservation of buffers.

A multi-line connection is a bundle of lines and connecting elements and is regarded as a data path which allows the data to travel through one available path when another path is blocked. The sending of Binons combined to form grids take place on the first free line. The message flow is reported in two areas.

In the area of the connections, a grid is only addressed from A to B if it can be accepted by B. the Deletions of grids resulting from the release of storage resources are due to the use of

709819/0342

Multi-wire networks faster.

In the area of virtual circuits, the network regulates the fastest rate of acceptance of the bundles as a function from the more or less rapid progression of the preceding Bunch.

The transmission path control is the mechanism that allows determine the path the data will use at the moment the connection is made.

The transmission path control is divided into thresholds. Starting from an intermediary, a participant can be reached in several ways.

The principle of route control is that a priority route is used if a threshold value of this route is below a certain threshold value, then the subsequent one Routes in decreasing order of precedence up to the same threshold value.

To determine the route costs, information is required, given by the adjacent intermediaries.

The degree of anticipation is the number of bundles that end B takes up before being forwarded on a designated line able. This level is thus defined as the availability of storage capacity in the area of the transition points.

The storage volume that is kept free allows a degree of availability of the buffer storage to be guaranteed. For reasons In terms of economy, the buffer memories that are actually used change during the handling of a call connection.

709819/0342

SYNC HR LINE ADAPTER.

Fig. 4 shows schematically a synchronous line adapter ALS, which allows to encode the information in the TTL area that comes from line connections such as those, which are standardized under the designation V 24 or V 35 (CCITT standard). The information is collected binonally in order to to be transmitted over the network or, in the reverse direction, are recovered binonally. the Concentration and the formation of the messages takes place progressively in the various stages.

The synchronous line adapter performs the electrical adaptation and the multiplexing or its return to the information off, depending on whether it is sending or receiving.

A certain number of adapters ALS, e.g. sixteen, are connected to a synchronous line unit ULS via a common busbar and each adapter individually connected via a call line.

In FIG. 4, stage 25 represents that stage which is sent to the clock generators of the MODEMS through connections 114 and connected. By counting the clock pulses one enters Decoder 25a, the number of the box, i.e. the number of the synchronous line adapter that is connected to the interface stage with the Line unit 26 is passed on. From stage 26, the messages on ULS are on a line of fourteen Wires forwarded, eight of which for data transmission and the other for transmission of service data are intended (two wires for the clock signals and four wires for the card number). Except for the card number or from ALS, ULS has yet to find out the number of the line to which it is connected. The transmission of the line number and the data is sent on the NOLI line.

709819/0342

-YYY-

The stage 25 sends synchronization pulses over the line H. off, which open the inputs of stages 24 or 27, depending on whether it is an entry (EC) in the modems, performed by stage 24 connected to the modems by lines 103, or a display (LE) performed by stage 27 connected to the modems by lines 104. The data are then on the lines connected to the NOLI line D transferred.

In stage 24 there is a circuit that reverses the multiplexing process and the information binon-by-bin to the modems, while in stage 27 a buffer memory is included, which is the temporary The recorded binons are saved before they are read by the ULS. The interface 26 also has a number of storage registers which allow waiting until the ULS is available without losing messages walk.

SYNCHRONOUS LINE UNIT.

Fig. 5 is the functional diagram of a synchronous line unit. During the synchronous line adapter ALS the transmission caused by information binons between the modems and the network, the synchronous line unit carries the binons so that characters are formed and supplies them to the bundle processor PP after processing. During the sending process conversely, receives the OLS characters that arrive from a subscriber via the processor PP from the network. the end Fig. 5 it can be seen that the ULS is composed of seven individual blocks and a transmission busbar 45 and a receiving bus 44 has.

709819/0342

In the figure, the blocks, seen from left to right, the following meaning:

an interface block 26 with the line adapters;

- a block 31 for restoring and sending the Sign;

an interface block 32 with the trunk processor;

a computer block 33 for parity redundancies;

a line memory block 34;

a sequence analyzer and recoding block 35;

- a processor block 36.

The processor block 36 is built into the system in order to sequence the successive operations of the various organs, clear up and analyze the events and perform arithmetic and logical operations on 8-bit bytes to undertake.

The processor block can execute four types of commands:

- arithmetic and logical operations;

- transfer between inner and / or outer registers;

- conditional or unconditional branches;

- special register controls.

Fig. 6 shows schematically the organization of the processor 36, which consists of two parts operating at the same time:

- The command reading device 37 takes from the program memory 38 the next command to be executed, which is in a Register 3 9 is entered and executed by an executive 40;

- the removal of the next command takes place while the executive organ executes the current command.

709819/0342

This organization is referred to in Anglo-Saxon literature as the "look-ahead program".

The instruction reading device 37 for its part has a program counter 41 which addresses the memory 38, the buffer register 39 which stores the command read in the memory, a command decoder 42 and a condition multiplex lexer 43, which causes a branch if the checked condition is fulfilled. In this case controls he changes the command in the program counter. The processor works in turn on each line, and a special one Connection 27 interconnects the register NOLI, which contains the number of the line, the line block memory 34, the parity block 33 and the block 31 for restoring and sending the characters.

Fig. 7 reproduces the executive element 40, which operates with a receive busbar and a transmit busbar.

In particular, the executive organ controls the transmission operations between the two busbars.

Between the receiving busbar 44 and the transmitting busbar 45 are connected in parallel:

a memory allocated to the processor 46, consisting of a register block which is addressed in this way by the instruction INS is that it outputs the contents of the register to the scanning busbar or data from the write busbar records. The capacity of this memory is, for example, thirty-two 8-bit bytes;

- A transfer operator 47, which the transfer of the Allows receiving busbar 44 to transmit busbar 45;

709819/0342

a working register 48 taken from the receive bus 44 is fed, if a corresponding instruction is present, and its content as a second operand in the stage 50 can be transferred;

an arithmetic operator 50 whose first operand is given from the receiving busbar and its second operand, if applicable, from the working register 48 can be found;

a PROM read-only memory, which contains the constants used in the processor, also the second Operand can move to level 50;

a memory 51 transfers the result to the transmission busbar at the end of the command.

Further elements are not shown. It is primarily a clock that sends signals to the condition multiplexer (43 in Fig. 6) and a monostable safety circuit that is periodically from the processor is switched on again. If this monostable circuit is not switched on again, a signal sent out on a fault line.

The executive 40 operates as follows:

the command read in the program memory 38 (FIG. 6) is decoded in the command reader 37;

- depending on the type of command, one of the transmission registers sends a message on the receiving bus 44;

- an operation (transfer or arithmetic operation)

709819/0342

is done either in stage 47 or in operator 50;

- The result appears in the following cycle (i.e. 50 ns later) on the send bus! rail 45, and a receive register takes this information into account.

At the same time the next instruction is taken over into the program memory 38, and the program counter 41 goes by one Unit further? advancement is usually one step; but if they are different Branches, the progress is determined by the instruction.

In a special embodiment there are seven types of commands, which in the first case involve arithmetic and logical operations on an 8-bit byte between a constant and the content of a register R of the memory 46.

The other types of commands allow the various operations required to be carried out.

The synchronous line unit described in FIGS. 5, 6 and 7 works as follows: at the entrance of each binon at the ALS, it generates a call signal for the ULS, which is sent by the interface block with the line adapter 26 and in particular by a call encoder is received, which as wired logic circuit is constructed. This block stores the number of the calling ALS and assigns it one Transfer release to. The binon then enters the ULS and goes to block 31 for recovery and broadcast guided by signs. The block 31 contains the line number corresponding to the transmission line which Line number in the interface 26 by chaining the

709819/0342

Number of the adapter and the line number of the adapter transmitted by the ALS is determined.

The zexchen recovery block 31 uses memory, which are addressed directly by calling line numbers that belong to block 31.

On the one hand to know what kind of processing is to be carried out and on the other hand to know the received character To save, the Zexchen recovery block has the following properties

- he can count the successive binons in state 1 so that he can recognize the errors;

- he can determine the synchronization characters;

- He can store the characters in the line memories during reception 34 store;

- he can determine the end of the character;

- if necessary, he can check the cross parity of the character and the processor the recovered characters and the line from which they come with the help of the "SiIo register" (entered first - brought out first).

The processor extracts the characters recorded in this register and puts the subsequent analyzer 35 into operation, by acting on a register which represents the input interface of the analyzer 35. This analyzer represents the special characters by addressing a read-only memory and encoding the identified character. This Code addressed along with one from the processor

T09819 / 0342

dt *

incoming line sequence signal another memory, which transmits to processor 36 the commands necessary to carry out the action to be taken.

The parity operator 33 operates, for example, on memory of two or three 8-bit bytes, which immediately go through the line number must be addressed. Each of these memories contains the cyclic redundancy character during the calculation. A sequence is triggered for each character, and each binon is introduced into the computational logic. The parity operator is loaded and checked by the processor. The messages processed in this way are then sent to the Bundle processor PP supplied.

In order to carry out this transfer, the ÜLS is equipped with a Interface stage 32 is provided, which has "silo registers" that accommodate the traffic peaks. The ULS is in charge the bundle processor to:

- information about the type of call;

- the calling line number;

- an indication of the content of the 8-bit byte at which there is can be an 8-bit byte with data (received character) or an operational 8-bit byte. To the Operational information includes the identification information, information about the start of the bundle, the redundancy calculation etc.

As for its structure, the ULS is in the shape of two simultaneous and parallel working arrangements, one of which is responsible for the exchange of binons with the ALS and the other, which consists of operators controlled by a special processor, processes and prepares the Messages that have been received or are being sent

709819/0342

should.

The bundle processor transmits in the opposite direction (transmission) 8-bit bytes and operating information of the above to be sent to the synchronous line unit on the lines listed type. The shipment of Binons to the ALS takes place by calling the ALS; the calls are picked up by the interface 26, which goes to the block 31 for restoration and sending characters works. The binons are sent to the ALS by removal from the line store the block 31. The characters were in the memories by the processor on their arrival in the order of their arrival by the bundle processor.

In a special embodiment of the invention can sixteen line adapters are connected to each ULS by the parity calculation block 33 and the sequence analyzer, i.e. 128 lines.

ASYNCHRONOUS LINE UNIT (ULA)

The asynchronous line units are used to establish the connection between parallel connecting lines and a bundle processor PP. The ULA have the same meaning for the asynchronous lines as the ULS for the synchronous lines, and their structure is practically the same. When receiving, they lead the parallel connecting wires that connected to them, they differentiate the procedural characters and the special characters of certain users from the data characters, they examine certain particular sequences, conduct the tests of longitudinal and Cross parity, convert the code of received characters, establish the connections and disconnect them when the idle

7098 19/0342

breaks exceed a certain time.

When sending, they lead the parallel connecting wires, connected to them determine the beginning and the end of messages and transmit the longitudinal parity. They have a processor block that exactly matches that used in connection with the synchronous line unit has been described. The ÜLA arrangement is comparable to the ÜLS arrangement, with the exception of that Interface of parallel connections on which the received characters and the number of the corresponding line are fed to the data processor of the ULA via a "silo register".

BUNDLE PROCESSOR.

A bundle processor PP contains synchronous and asynchronous line units for signs. He forms, analyzes, connects the bundles, restores the grids and sends the signs on the line units.

For this purpose, the bundle processor uses a main memory MM which, according to a special embodiment, has two bundle processors of the same design is common if an auxiliary processor is used for operational safety.

The switching of the bundles between line units belonging to different modules makes exchanges is required between the main memories of these modules, and these exchanges are handled by the trunk processor of the module concerned made via a time bus, which is also used for the exchange processes between the Bundle processors and the control units is used.

709819/0342

8 shows a bundle processor in a block diagram. It is essentially an entry and exit system 51, which is connected to the line units and the simplest and most frequently occurring processes to simplify the work of the processor 36, which exactly matches the processors described in FIG the synchronous and asynchronous line units are used.

The entry and exit system 51 takes the storage of the incoming words from the line units in a shared memory, the transmission of words from the shared memory to the line units / the allocation of an available buffer memory at the beginning of the reception a trunk and the assignment of the trunk to the memory, the generation of calls to the processor and the establishment the queue.

In addition to the input and output system 51 and the processor 36, the bundle processor has a program memory 52 and a memory access circuit 53. Not with the List of the functions of the incoming and outgoing auditor specified operations take place on control commands of the processor, which is free from time pressure with regard to answering the call is, loads that can be attributed to the fact that no incoming character may be lost and that there must be no delay in the transmission of the expiring characters.

The memory access circuit 53 consists of a group of Fast storage with assigned logic circuit. she can be turned on by both the processor 36 and the input and output checker 51. She allows direct addressing of the main memory MM

70981.9 / 0342

hold tables that are sorted by line numbers, by logic route numbers, are sorted by bundle numbers, by connection numbers, etc.

In Fig. 9, the entry and exit tester is shown schematically. It consists of three function blocks:

a register group 60, which enables the establishment of a connection between the exchange busbar 70 of the line units and the time bar connection CBT 71 with the memory bus 72 for data transmission permitted;

- A silo register 61, which acts as a buffer between the exchange rail UL and CBT and the processor 36 for the processing of bundles (busbar 73) is used;

- A time base 62, which develop several command sequences which control the memory access circuit, the sequences being stored in a read-only memory 63 are.

A stage 75 connects the processor to the time rail connector.

The incoming and outgoing auditor works as follows:

- if a call arrives at the test circuit, it detects it the two 8-bit bytes coming from the line unit and assigns them to registers 601 and 603 or, if mesh-wise, via the time rail connection is transferred to registers 602 and 604. These 8-bit bytes are assigned two binons that indicate the type of Specify the message in more detail. It can either be a message that is immediately put into a buffer

709819/0342

memory of the main memory must be arranged, or a message that must be fed to the processor 36 via the silo register 61, or a Message that a selection and the expiration of one of the clock sequences of the time base 62 of the input and output checker from the read-only memory 63 allows. These clock commands are executed by the memory access circuit and allow location allocation in main memory and queuing for analysis of occupied positions. The input and output checker assigned to the memory access circuit is therefore working like a channel broadcast by the line unit and reporting to the processor. It is note that the number of events it has to transmit to the processor compared to the number of messages which it processes directly, is limited.

Conversely, when a call originates from a line unit, the input and output checker sends two 8-bit bytes which it takes from a buffer memory with the help of registers 605 and 606.

If it is a call originating from the time bus, two 8-bit bytes are also included Using registers 607 and 608. Each time a character is sent on the time bus, a 8-bit byte counter 64 stepped down, whereby the incoming and outgoing checker recognizes the zero setting of a buffer counter and allows it to strive to queue the contents of the next in a send queue to search for the buffer to be sent.

The processor 36 of the bundle processor PP exactly matches the processors that are used in connection with the ULS (Synchronous Line Unit) have been described and

709819/0342

3ο

as part of the ULA (asynchronous line unit) has been described. In contrast, the number of total execution instructions that are directed to this processor are much larger and the tasks it has to perform are much more diverse. The processor 36 must namely for the organization of the grids, the analysis of the received bundles, the classification of the analyzed bundles in the queue towards the exit, the processing and the sending of the bundles that are "free to receive" the Clearance of the buffer memory are concerned.

The speed at which these functions can be carried out depends on the memory access circuit 53, which will be described below. The processor receives requests originating from the input and output stage 51 for work to be carried out via a silo register 54 which regulates the traffic. According to a feature of the invention, programs that are repeated very frequently are written into fast read-only memories, while the programs that are used less frequently ^{are stored in a read-write memory (Rt 1} M). On the other hand, the processor 36 is equipped with high-speed line memories which are addressed directly by calling line numbers in accordance with eight 8-bit bytes, for example for 512 lines. In an implemented switching system, a trunk processor can control 512 synchronous and asynchronous lines. The switching options are on the order of 2,000 baud.

FIG. 10 shows the memory access circuit designated by 53 in FIG. This circuit consists of a group of registers and associated logical operators, the Establishes connections on the one hand with one another and on the other hand with the memory through the information bus bars 80 and the memory 61 is addressed. The busbars

709819/0342

and 81 do not control the main memory MM directly but lead to a memory adapter interface stage AM. the The actual circuit 53 has a block 82 with marker groups. A marker is either by the time base level 62 of the input and output circuit 51 or by an instruction of the processor 36. A group becomes defined by the line number of stage 51 or by a register Pr loaded by processor 36. These markers contain, for example, the organization indices of the bundle per line or per connection. The block 83 is a Block containing the current address of the buffer memory, which can be addressed by the line number and which Enables sequential characters to be placed in or removed from the buffer memory. That gradually The increase in these current addresses is brought about directly in the circuit 53 by the adder 84. Of the Block 85 contains a certain number of markers (e.g. 128) which are either markers Sj that are addressed directly by the operand j of the command (e.g. marker in the table of free Buffer memory), or to markers Spr, which are defined by a register pr 86, which is loaded directly by the processor, or to markers Wj, which are directly are addressed by the operand j of the instruction and which are post-indexed by the operand d of the instruction can, or finally to markers Wpr, which can be subsequently indexed by the operand d of the instruction.

The stages 87 and 88 are multiplexers. Registers 89 and 94 allow processor 36 to do the direct Access to the memory. The registers 90 and 91 form a block that the logical OR operation between the contents of the register 80 and a memory word. The result is read into register 92 and addressed the memory. The assembly 90 and 91 allows

709819/0342

3 *

direct addressing of the tables sorted according to the number of the logic path.

A marker 93, one part AI of which is loaded with an input address originating from the memory, and the other part (91) of which is loaded by processor 36 is post-indexed by operand d of the instruction. This marker allows, for example, the addressing of the overflow tables or the tables with indirect Access. The enumerated blocks and registers are either by a special instruction of the processor or put into operation for some of them by commands of the input and output stage 51.

SPOKE ADAPTER

The storage adapters encode those from the bundle processors incoming calls and enable the use of the memory if it is available. They monitor them Memory cards by decoding the high address weights to identify the individual card selections. They generate the clock and cooling signals if the memories used are MOS tables acts; they calculate the data redundancy when writing and when reading according to a Hamming code; they check the parity address binons when reading and may generate an alarm signal when a card is in the memory is deficient.

ORDINARY STORAGE

In the case of the shared memories used, it is advisable to use MOS memory, channel N with 4 k / binon per slot

709819/0342

intended. The access time is approximately 200 ns at a cycle time of 400 ns. The operational reliability of this memory can be checked by using a detector code Increase simple mistakes with self-correction. Each memory word of 22 binons is broken down into 16 data binons, 5 self-correcting code binons and a parity binon of the address at which this word is located, which makes the path the commands to be executed can be monitored. In a particular embodiment, a memory card 88 includes: 10S memory housing and the integrated addressing and reading circuits. With inserts of 4 kg / binon the data capacity is one card 16,000 words per 22 binons.

TIMELINE RAIL CONNECTION.

The time bus enables the transmission of data and signals between two trunk processors of the same module for signaling exchange, more generally between a bundle processor of the modules and another bundle processor of another module for the exchange of Bundles, between a bundle processor and a control unit for the exchange of signaling bundles and Errors or for ordering between two control units UC.

This exchange of information bundles takes place according to a technique used in telephony, called modulation encoded pulses (MIC for short). Following this procedure, a common busbar sets sequentially related a receiver during a unit time interval. Two consecutive units sintervals generally correspond to two different ones Mediations. The establishment of these exchanges is brought about by a logical exploration circuit, which provides the necessary information on the connections of the

709819/0342

The transmitter and the receiver are distributed to a busbar called a connector, which is connected to the time busbar is. Each hexing time interval is brought to act on a bundle processor or a control unit, depending on the traffic as a sender or receiver to be viewed as.

The bundle processors of the modules are structurally connected with time collector rail connections, with a bundle processor in Operation is while the other should step in if the first one fails. The information that indicate that such malfunctions are present and the information that enables a module to correct errors, are summarized in the registers of the CBT and are transmitted via the time log.

The following table shows the structure of a grid, i.e. a scanning cycle. The time collection track is in essentially a loop to which the bundle processors continue with the help of time busbar connections described below are connected.

The only figure shows lines that correspond to concrete lines and columns, which represent the temporal structure of the Represent connections.

709819/0342

BO B1 B2 B3 B4 B5 B6 B7

news

CS. ο B. O EH O _r B. &H Q) W. U
O CD
D.

O
O
O

> Η

C-J

Γ- (NJ

Be / S raster synchr.

0 11111

111111

CBT clock CBT

HHHHHH

HHHHHH

UG recipient

ρρΟ ppi

ρρ4 ρρχ χ = O..η

Line Bp is the line of the parity bit, lines BO to B7 contain the 8-bit message bytes running in parallel. Lines B8 B9 are raster synchronization lines. The line CBT shows the timing of clock pulses, and the bottom line in the figure represents either the receive burst processor or a control unit.

Each channel is assigned to a bundle processor PPO to PPM. A channel contains three 8-bit bytes that appear one after the other on the time bus. The first contains 8-bit byte Identification binons of the send bundle processor or the Transmit control unit. The 8-bit bytes 1 and 2 carry the

709819/0342

mediating news.

Each time position has a length of 150 μs, for example, and enables an 8-bit byte to be transmitted. Fifteen trunk processors and a control unit are scanned in each grid, the traffic of a control unit Unity is statistically equal to about 1/16 of the traffic of the trunking processors. When arranging shows the first 8-bit byte transmitted is the number of the sender on the one hand on and on the other hand it can be seen on the binon BO whether the channel is free or owned, and on the binons B1 and B2 whether it is the beginning of a buffer memory X or an end of message Y is involved. The 8-bit bytes 1 and 2 are then transferred to the relevant PP transfer.

The temporal switching used here has considerable advantages over the spatial switching, which is carried out by a 'Crossbar ¹ switching. Namely, the traffic to be handled by the system can easily be increased by using several time buses.

11 shows a time bus connection CBT which is connected in parallel to the actual time bus 95 is. At 96 it receives the clock pulses from the time bus. The time bus bar crosses in the area of the connection 95 successively an amplifier 97, a receiving register 98, a multiplexer 100 and a second amplifier 97a.

A control station 99 which controls the operation of the overall arrangement is shown schematically as a memory 99; he is located anywhere on the loop formed by the busbar.

709819/0342

The clock pulses arriving at 96 reach a receiver channel 101 which determines the channel number KR. This stage consists, for example, of a shift register with 48 positions, which depends on the arrival the clock pulse advances. The output signal of the stage 101 is at the same time a code comparator 102 and a multiplexer 103 is supplied. The comparator 102 compares the recorded code with that in the stage 104 stored code, which is an identification level of the module, which is via the time rail connection connected. The comparator 102 opens the gates when the received code number is in a predetermined one Time corresponds to the number of the module. Otherwise the gates remain blocked and it splinted nothing; 104a is an amplifier.

The messages coming from the busbar 95 are processed with the code of the channel KR in the multiplexer 103, then fed into a silo register 105, which establishes the pre-chaining of the data with the type of call originating from a wired logic circuit 106 originates. The data is thus queued and sent to the trunk processor in the exchange busbar 107 via an amplifier 106 only when this is confirmed by 108 will. The transmission chain 95-103-105-106-107 only relates to the reception of incoming messages via the time bus Messages through a batch processor. In the opposite direction, the information is on the rail 107 recorded by two registers 109 and 110. The 8-bit bytes 1 and 2 are then transferred to memories 111 and 112, while the 8-bit byte 0 in 113 is multiplexed with the number of the channel KR. If the result of the 102 The code comparison made is positive, the content of the memories 111 and 112 in the multiplexer 100 and from there transferred to the time bus 95, where it is from

709819/0342

the receiver burst processor in that described above Way is recognized.

The SILO register 105 and the memories 111 and 112 become for the data representation in the receiving organ to be determined Times used; As in the other stages, they allow the asynchronous input and output of data.

The symmetrical auxiliary components are not shown been.

Every intermediary and concentrator are network monitoring and maintenance facilities assigned that are not described. The actual control units can be used as mini computers be designed, which are equipped with a suitable logic. Since such computers are already on the market they do not form part of the invention.

The switching system according to the invention allows full utilization of the technical possibilities of the Components.

Claims ;

709819/0342

Blank page

Claims (10)

Claims 1 / Switching system for bundled data for a meshed one Network with transmission lines and switching centers, the switching centers with storage units are equipped that allow virtual addressing to be carried out, characterized in that each switching center consists of at least one control center and at least a line switching unit composed, wherein the addressing memory to be brought about to the Control unit belonging connections determined. 2. Switching system according to claim 1, characterized in that a switching center is a group of matching Switching units and a group of matching control units, the Number of each type of unit is determined by the maximum processing power of the center, and that all Units of a center can be connected one after the other with the help of a time bus. 3. Switching system according to claim 1 or 2, characterized in that that each switching unit has means for progressively concentrating the messages between the line interface and the Zeitssnimelschieneninterface and that the line interface handles binons and the time bus interface Treated data bundles. 709819/0342 4. Switching system according to one of the preceding claims, characterized in that each switching unit has at least one line unit which when recording Binon's characters and vice versa, as well as a bundle processor that is used in the Recording of characters forms data bundles and vice versa. 5. Switching system according to one of the preceding claims, characterized in that there is a high-speed computer in each line unit and in each trunk processor the same design is included, the successive the recorded data or to be transmitted to a line treated. 6. Switching system according to one of the preceding claims, characterized in that a switching unit consists of a main memory, a bundle processor and at least one line unit, on the one hand is connected to the trunk processor and on the other hand to a trunk group. Switching system according to one of the preceding claims, characterized in that a synchronous line unit connected to a synchronous line adapter which in turn is connected to modems and which is responsible for multiplexing the messages received by the lines and vice versa. 8. Switching system according to one of the preceding 709819/0342 Proverbs, daduirh marked that the bundle processor is connected to main memory through a memory adapter circuit containing markers that directly to predetermined positions of the memory Allow addressing. 9. Switching system according to one of the preceding claims, characterized in that - the simple and frequently occurring functions exercised by wired logic circuits; - the simple, but malfunctioning functions through logic circuits as a function of exercised by a processor; - the special functions are performed by special processors; - the general functions for establishing connections are carried out by general-purpose computers. 10. Switching system according to one of the preceding claims, characterized in that all elementary circuits are duplicated, so that in the event of a circuit failure, the system is restored and simultaneously an alarm signal is given. 709819/0342