DE2649309B2 - Binary clocked sense amplifier - Google Patents

Description

The invention relates to a binary, clocked sense amplifier according to the generic term of the main claim. In a preferred embodiment, this is according to the silicon-on-sapphire technology manufactured.

A common arrangement of memory cells has a pair of data bus lines over which information signals are transmitted to be enrolled and read; it also has a row or address select line via which a specific memory cell to which access is to be established from the arrangement, is selected. Typically, a read / write circuit that corresponds to the arrangement of the memory cells connected, a sense amplifier and a memory input driver which are connected to each of the two data bus lines. A piece of information is made out each memory cell constituting the array is read by taking the difference, i. H. the differences which senses signals along the data bus lines.

Usual sense amplifiers are relatively insensitive to signals along the data bus lines appear. In order to do justice to this low sensitivity of the detector circuit, it was It has hitherto been customary to limit the number of memory cells in the overall arrangement in an undesirable manner or to increase the storage capacity of each memory cell, thereby increasing the ratio of the storage capacity to increase the capacity along the bus lines. However, this made it necessary to use the to charge larger storage capacity first when addressing a memory cell for the purpose of reading the data became. In this way, the reading process was slowed down in an undesirable manner

The invention is based on the object of avoiding the disadvantages of the known sense amplifiers.

This object is achieved according to the invention in accordance with the characterizing features of the main claim.

The invention thus relates to a differential memory read amplifier, which turns a relatively small input signal into a large digital output signal generated. The present detector is connected to a pair of data bus lines. These data bus lines or data collection lines are connected to an array of storage elements for the purpose of Delivery of information signals showing the binary state of selected memory elements of the Display arrangement. In a preferred embodiment, there is the circuit that controls the sense amplifier forms, from a large number of metal-oxide-semiconductor field effect transistors, which are embedded in a layer of silicon are made on a sapphire carrier (SOS / FETs). A body knot that is inherent under the canal region is formed by a pair of SOS / FETs, is connected to a corresponding data collection line of the Pair of data collection lines connected. The body nodes form a pair of differential input nodes for the present sense amplifier. A change in the potential between the data collection lines, which occurs when a selected memory element is read causes an inequality the carrier potential of the first pair of SOS / FETs through their body nodes. The pair of body node on the input side reflects a change in the differential potential falling above them, the more effective the threshold of one of the transistors of the first pair of SOS / FETs compared to that second transistor of this pair to increase. In this way the first SOS / FET becomes conductive before the second, depending on the state of the logic signal on each of the data collection lines. Of the second transistor of the first pair of SOS / FETs is below in view of an inadequate Threshold potential non-conductive controlled. A da-

t node connected to each transistor of the first pair of SOS / FETs assumes a voltage which indicates the logic level of the corresponding signals on the data collecting lines.

The body wrangles of a second couple from SOS / FETs are clamped to a source with a relatively low reference potential, such as ground The body nodes of a third pair of SOS / FETs can use a source of relatively low Be connected to reference potential or are independent of a potential, i. H. the potential can be free to adjust. The present detector circuit is controlled synchronously by applying clock signals Clock signals are applied to the gate or control electrodes of each of the transistors, the second and the third pair of transistors form a clock input terminal is to each of the gate electrodes of the third pair of Transistors connected via signal delaying and signal inverting means. Hence during certain Intervals of the clock signal the binary signal level of the clock signal at each of the gate electrodes of the third Pair of transistors in polarity opposite to those clock signals applied to each of the Gate electrodes of the second pair of transistors are received.

The invention is illustrated by the following description of the in the drawing Embodiment explained in more detail.

It shows

F i g. 1 is a schematic representation of the sense amplifier according to the invention, the increased sensitivity has and

FIG. 2 shows a pulse image with a representation of a clock control signal at a clock input connection and FIG a delayed and inverted signal at the output terminal of the sense amplifier according to Fig. 1.

The F i g. 1 schematically shows a single circuit for representing a differential memory sense amplifier with increased sensitivity. Such a sense amplifier is used for this purpose, for example used, from relatively small input signals, which the binary state of selected memory elements 20, which form a conventional memory arrangement 1, indicate a relatively large digital output signal produce. A conventional memory arrangement 1 has, in a known manner, a bit line or a bit data collection line 2, a bit line or bit data collection line having an opposite state 4 as well as columns and row address decoders not shown. Typically one is Sense circuit forming sense amplifiers connected to each of the data collection lines 2 and 4. the binary information corresponding to the logical state of a selected memory element of the arrangement is read by taking the signal difference along data collection lines 2 and 4 recorded

The circuit for the sense amplifier of the present invention consists of a plurality of transistors Qi-Qt. In a preferred embodiment, the transistors Qi-Qs are n-channel metal-oxide-semiconductor (NMOS) field effect transistors (FETs), which are in a silicon layer on a sapphire substrate or . Carrier (SOS) are produced. A potential source V _D d is connected via current limiting resistors R \ and Ri to a first of the electrodes of the conductivity path of each of the FETs Qi and Qi . Typically, the potential of the source Vod is in the range between 3 and 15 volts DC. The second of the electrodes of the conductivity path of each of the FETs Qi and Q ₂ is connected to a reference potential source, for example ground. The gate electrodes of the FETs Qi and Q ₂ are cross-connected. In particular, the gate electrode of FET Qi is connected to the opposite data node 10 in order to have a common electrical connection with the current limiting resistor R2

ίο and the first conductivity path electrode of FET Q ₂ . The gate electrode of FET Q ₂ is connected to the opposite data node 8 so as to establish a common electrical connection with the current limiting resistor R \ and the first conduction path electrode of FET Qi. A first conductivity gap electrodes of FET Qi is connected to the common electrical connection represented by the data nodes 8, connected a first conductivity gap electrodes of FET Q ^ is connected to the common electrical connection represented by the data nodes 10, interconnected, the respective second of the conduction path electrodes of each of the FETs Qs and Q ₄ is connected to a reference potential source, for example ground.

The sense amplifier is controlled synchronously by a suitable clock generator, not shown. The clock signal input terminal CL, to which the clock signals of the generator can be applied, is connected to the

jo gate electrode of FETs Q ₃ and Qt connected. The clock signal input terminal CL is further connected to the gate electrodes of the FETs Qs and Qfe via suitable inverter delay means. An example of such suitable inverter delay means, which can preferably be used in the present case, is the series connection of a conventional delay line 5 and a gate 6 which inverts the signal Gate electrodes of FETs Q ₅ and Qb are present, opposite to the binary state of those clock signals present at the gate electrodes of FETs Qi and Q ₄ , as a result of delay means 5 and inverter gate 6.

The bit data collection line 2 is connected to one of the conduction path electrodes of the FET Q ₅ . The bit data collection line 4 is connected to one of the conduction path electrodes of the FET Q 6. The second electrodes of the conductivity line electrodes of the FETs Q ₅ and Q ₆ are connected to a suitable reference potential source, for example ground.
In the manufacture of field effect transistors fabricated by the silicon-on-sapphire technique, it is common for a body node to be formed, for example within a lightly doped P-region between the conduction gap electrodes of an n-channel device. The carriers and the body nodes of SOS / FETs, which have conventional sense amplifiers, are potential-wise unbound, ie the potential is set free of any potential sources. According to the present invention, each Köi perknode 12 or 13 of the SOS / FETs Qi or Q _{2 is} connected to the data collecting line 2 or 4, so that they form a pair of differential input nodes to the present sense amplifier, so as will be explained in detail later. Each of the body

node 14 or 15 of the SOS / FETs Q ₃ or Q ₄ is connected to a source of relatively low reference potential, for example ground. The body nodes 16 or 17 of the SOS / FETs, Qs or Q ₆ can be connected to a reference potential source of relatively low potential (as shown in dashed lines), or can be unbound in terms of potential.

In a preferred embodiment, in which the sense amplifier has maximum sensitivity, the present sense amplifier is initially physically and electrically balanced. In other words, the electrical parameters such as resistance, threshold value, capacitance, etc. of the elements R \ - the FETs Qi, Qi and Qs, and the collective line 2, which forms one half of the sense amplifier, are matched with the corresponding elements A ₂ , the FETs Q ₂ , Qt, Q ₆ and the data collection line 4, which forms the adjacent half of the circle, balanced. Looking at the same time the F i g. 1 and 2, when the circuit is operating during a time interval of the clock signal, which is denoted by fi, the logic level of the clock signal at the input terminal CL is relatively high, that is to say true. The gate electrodes of the FETs Q ₃ and Q ₄ are applied with a switch-on signal with the logic level high.As a result, the FETs Q ₃ and Q _{4 are turned on} is clamped to this potential through the corresponding conductivity paths of the FETs Q ₃ and Q _4. FETs Qi and Q ₂ are non-conductive because their respective gate electrodes are cross-coupled to data nodes 10 and 8, as discussed above. As a result of the delay means 5 and inverter 6, during the fi clock interval a turn-on with a relatively high logic level from the output terminal of the inverter 6 also applied to each of gate electrodes of FETs Qs and Q. ₆ Therefore, the FETs Qs and Q _{6 are} controlled to be conductive. The body input nodes 12 and 13 of the FETs Qi and Q ₂ are clamped to ground via the corresponding conductivity paths of the FETs Q5 and Qs. The sense amplifier is cleared for any information sensed during previous clock cycles and is thus reset.

During the time interval of the clock signal, which is designated by / ₂ , the logic level of the clock signal at the input terminal CL continues to remain relatively high. As a result, the switch-on signal with the logic level high continues to be present at each of the gate electrodes of the FETs Q ₃ and Q _{4 and the FETs Q 3} and Q ₄ remain conductive. The sense amplifier data nodes 8 and 10 remain connected _{to ground via the corresponding conductivity paths of the FETs Q 3} and Q _4. The FETs Qi and Q ₂ therefore also remain non-conductive. From the output terminal of the inverter 6, however, a signal with the logic level is relatively low, ie incorrectly, applied to the gate electrodes of the FETs Q ₅ and Q _6. Therefore, the FETs Qs and Q _{6 are} now controlled to be non-conductive.

During a time interval of the clock signal, which is denoted by h , the logic level of the clock signal at the input terminal CL switches to the signal level relatively low. The gate electrodes of FETs Q ₃ and Q ₄ are then subjected to this signal having the logic low level & whereby both FETs Q ₃ and Q ₄ are controlled non-conductive. As a result of the delay means 5 and the inverter 6 continues to apply a relatively low logic level signal to the gate electrodes of the FETs Qs and Qe from the output terminal of the inverter 6 during the clock interval (3. This leaves the FETs Qs and Q ₆ non-conductive. The body input nodes 12 and 13 of the SOS / FETs Qi and Q ₂ , which are correspondingly connected to the BIT data collecting line 2 and the bit data collecting line 4, are no longer clamped to ground but now have a different potential, namely as a result of the corresponding potential change along the bus lines 2 and 4, caused by a selected memory cell to be read. As a result, the substrates of the FETs Qt and Q ₂ also assume different potential -Input nodes 12 and 13 effectively made the threshold potential _{of FET Qi less than the threshold potential of FET Q 2} or vice versa during the f _{3 cycle} At intervals, the potential of each of the sense amplifier data nodes 8 and 10 begins to rise up to the supply voltage Vdd, insofar as the conduction _{paths of the FETs Q 3} and Q _{4 are} not active at the moment. Depending on the logic level of the selected memory cell and the corresponding signals appearing along the data collector lines 2 and 4 and at the body input nodes 12 and 13, one pair of SOS / FETs Qi and Q _{2 become} conductive before the other controlled After one pair of FETs Qi and Q _{2 has been} turned on, the corresponding sense amplifier data node 8 or 10 is clamped to ground through its conduction path. The clamped data node assumes a voltage corresponding to the signal with a low logic level. In view of an insufficient threshold potential, the other pair of FETs Qi and Q ₂ , the gate electrode of which is connected to the first of the data nodes 8 and 10, remains non-conductive. In this way, the assigned other data node is charged until it assumes a voltage, ie Vdd, which corresponds to a high logic signal level.The detector circuit reflects the initial potential difference between the body input nodes 12 and 13 to the same extent as the data nodes 8 and 10 provide digital signals representative of either a logic high or low signal level. At the end of the t ₃ clock interval, the reading process for the selected memory element of the arrangement is completed.

During the time interval of the clock signal, which is denoted by U , the clock signal at the input terminal CL remains relatively false. A signal with a low logic level is still present at each of the gate electrodes of the FETs Q ₃ and Q _{4 and the FETs Q 3} and Q ₄ remain non-conductive. As a result of the delay means 5 and the inverter 6 of the inverter is applied 6, a turn-on signal with a high logic level to each of the gate electrodes of FETs Q ₅ and Q ₆ from the output terminal of the FETs Q ₅ and Q ₆ are then made conductive via the Leitfhäigkeitsstrecken the FETs Qs and Qe , the body nodes 12 and 13, respectively, are clamped to ground. In this way, the differential voltage signal between the body nodes 12 and 13 is removed. From the voltage supply Vdd , however, a sufficient threshold value potential is still applied to the gate electrode of the first of the pair of SOS / FETs Qi and Q _{2 via the second of the data nodes 8 and 10.}

sets in order to conductively control the first of the FETs. Simultaneously with this, the gate electrode of the second pair of SOS / FETs Qi and Q _{2 is} clamped to ground via the first of the data nodes 8 and 10, as a result of which the second of the FETs is controlled to be non-conductive.

As a result of the present invention, an improved differential sense amplifier with increased sensitivity can be used which generates relatively large digital output signals from relatively small input signals occurring on the data collector lines. A relatively small change in the potential along the bit and bit data collecting lines 2 and 4 is reflected as a relatively large logic signal at the data nodes 8 and 10. The signals with the relatively low level, which are applied by the memory cell arrangement via the bus lines 2 and 4, can be smaller than the threshold of one of the FETs Qi or Q ₂ . In accordance with the present invention, however, the body input nodes 12 and 13 reflect a potential difference across them to effectively raise the threshold of one of the SOS / FETs Qi and Q ₂ with respect to ground. In this way, the first of the FETs Q 1 and Q _{2 is turned on} more strongly, while the second of the FETs Qi and Q _{2 is} turned off. A regenerative current effect is maintained at the gate electrodes of the FETS Qi and Q ₂ , thereby forming a data lock.

It is understood that changes can be made to the illustrated embodiment without departing from the scope of the invention. For example, the FETs Q] -Qb can be realized not only from n-channel devices, but also by other suitable semiconductor devices. In addition, the FETs Qi -Qe cannot be fabricated from a layer of silicon on a sapphire substrate, as shown in the preferred embodiment but they can also be made of any other suitable semiconductor material other than an insulating support. It is' further understandable to the person skilled in the art that the

ι ο conductivity type of the FETs Qi - Q ₆ and which correspond to the logic level of the data nodes 8 and 10 on the type of device used and the logic level of the signals on the data collection lines 2 and 4 depend.

A single sense circuit has been described above, that of a differential memory sense amplifier with increased sensitivity for reading the binary state of selected memory elements that form an arrangement of storage elements realized. This sense amplifier has in a preferred Embodiment on a circuit comprising: a plurality of metal oxide semiconductor field effect transistors which are made in a layer of silicon on a sapphire base. The body knot each transistor of a pair of SOS / FETs isl with a corresponding data collector line dei Memory array connected so as to provide differential input nodes for the sense amplifier. Dei present sense amplifier supplies from relatively small input signals that are transmitted by the memory arrangement the data collection lines are supplied, relatively large digital output signals.

For this purpose 2 sheets of drawings

Claims (6)

Patent claims: 1. Binary, clocked sense amplifier, which is connected to two data bus lines of a binary memory cell arrangement for detecting the memory information signals on these bus lines and is made up of several multi-electrode semiconductor arrangements, some of which are connected to the data bus lines and that output amplified memory information signal, characterized in that at least two of the semiconductor arrangements (Qi, Q2) each have a body node (12, 13) between the electrodes of the conductivity path, which is each connected to one of the data bus lines (2, 4), whereby expresses the state of the information signals in a corresponding potential difference between the body nodes. 2. The sense amplifier of claim 1, wherein the two semiconductor devices are fed back via the cross, at which the two data nodes at which the feedback branch, a second ..Vielelektroden semiconductor element pair is turned on, characterized in that said second semiconductor element pair (Q 3, Q 4) also has a body node (14, 13) between the electrodes of the conductivity path, which is clamped to a relatively low reference potential, preferably ground 3. Sense amplifier according to claim 2, characterized in that a third pair of multi-electrode semiconductor elements (Q 5, <? 6) is provided, the conductivity paths of which are connected into the data bus lines. 4. Sense amplifier according to claim 3, characterized in that this third pair of semiconductor elements one body node (16, 17) between the electrodes of the conductivity path has, which is alternatively clamped to a relatively low reference potential, preferably ground is or is potentially unbound. 5. Sense amplifier according to claim 2 and 3 or 4, characterized in that the control electrodes of the multi-electrode semiconductor elements «? 3, <? 4) of the second pair with a first clock signal (A) and the control electrodes of the semiconductor elements (Q 5, Q 6 ) of the third pair are acted upon by a second clock signal fß>, which is inverted with respect to the first clock signal and phase shifted by a fraction of a half period. 6. Read amplifier according to claim 1 or one of the following, characterized in that the multi-electrode semiconductor elements are formed with a body node between the electrodes of the conductivity path by field effect transistors, which are made by a layer of silicon on a sapphire substrate.