DE2649186A1 - ELECTRONIC DIGITAL CLOCK - Google Patents

Abstract

1536001 Electronic alarm timepieces DAINI SEIKOSHA KK 27 Oct 1976 [28 Oct 1975] 44637/76 Heading G3T In an electronic alarm timepiece, having a 24- hour basis digital display and a plurality of memory circuits for memorizing respective alarm times which can be selectively displayed, in response to an output signal from a respective NOR circuit 1, Fig. 1, when a memory circuit Ml, M2 or M3 is reset the segment "g" only of each display device Fig. 2, is energized so that --:-- is displayed rather than 00:00, thereby distinguishing from a normal time indication. To display the contents of M1, an output from NOR1 causes gates 6, 8 to selectively open transmission gates 21-24 thereby to pass a 32Hz drive signal AC 1 directly or via an inverter 20 to a common display electrode 34 and to selected ones of segment electrodes S1 as determined by the outputs of memory Ml which controls AND gates 11, 12. To display actual time of day, outputs from minutes and hours decoders 35, 41 control AND gates 37, 38, 43, 44 to pass 32Hz drive signals to display electrodes S2, S3. When the memories M1, M2, M3 are set to zero, only the segments "g" corresponding to electrodes S2, S3 of the minutes and hours display devices are energized.

Description

DIPL.-PHYS. F. FINALLY ο-β _Ο3 4 unterpfaffenhofe _N 25.10. 1976 PATENT ADVERTISER P.O. Box _S / _es

(MUNICH) 84 36 38

D1PL.-PHYS. F. FINALLY. D - UNTERPFAFFENHOFEN. P.O. BOX

TELEX: S2 173Ο

My file: D-4084 Kabushiki Kaisha Daini Seikosha, Tokyo, Japan Electronic digital clock

The invention relates to an electronic digital watch according to the Preamble to the main claim.

Known clocks with a display for 24 hours use both for the time display, i.e. for the display of normal time, as well as for the display of the timer (alarm timer) the same display status, for OO: 00, whereby the timer is reset. The two left digits are used to display the hours and the two right digits for the Minutes display. It is therefore difficult with the known clocks to distinguish whether with regard to the timer or alarm timer the display status or the reset status is shown.

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The invention is based on the object of creating an electric digital watch which has the disadvantages of the known Eliminated clocks of this type. According to the invention, this object is achieved by the subject matter of the main claim.

The invention provides an electronic digital watch that a distinction between the display 00:00, which corresponds to an alarm time setting, and the reset state of the alarm timer. The reset or cleared state of the alarm timer is in accordance with the invention indicated by (-: -), as opposed to an alarm time setting for (00:00). The user can use These different representations immediately determine whether a time setting is being made when the alarm timer is displayed or there is a deferred or deleted state.

A preferred embodiment of the invention is described below with reference to drawings to explain further features. Show it:

Fig. 1 is a block diagram of an embodiment of the invention, and

2 shows the digits made up of several segments.

The electronic digital clock according to the invention has three memories Mi, M2, M3, each of which has the same structure, as shown in FIG. The following embodiments related to the memory MI are to be applied accordingly to storage tanks M2, M3 «

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If there is no memory content in the memory MI, a signal ¹¹ O "is applied to a NAND circuit by a NOR circuit 1, so that the NAND circuit 6 supplies a signal" 1 ". This" V 'output signal of the NAND- Circuit 6 is applied to a NAND circuit 8, which consequently ^{supplies a signal 11} O "at the output, as a result of which transmission gates 22, 24 are switched to the ON state. The input signal of an accumulator AC-I is connected to an AND via transmission gate 22 Circuit 11 and to a common electrode 34. An inverter 20, which receives the signal AC-I, supplies at its output a signal AC-2 which is applied to an AND circuit 12 via the transmission gate 24. The signal AC -2 is therefore a signal inverted to the signal AC-I.

The signal "I" of the memory Ml is fed to a NOR circuit 25, which ^{supplies a signal 11} O ", whereby the AND circuit 12 is closed and the channel display SI does not receive the signal AC-2. The signal" 0 "of the NOR circuit is ^{inverted into a signal" 1 M} by an inverter 28, so that the AND circuit 11 is opened. A NOR circuit 31 makes the input signal AC-I in. Signal AC-2 changed, whereby the channel display SI receives the signal AC-2.

The common electrode 34, however, receives the signal AC-I, thereby providing an indication representing the memory state, by which indication state the channel indication selectively represents the content of the memory Ml. If the memory MI is reset or cleared, which is due to of a signal "1" of the NOR circuit 1 occurs, the

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Time display OO: 00 is set whereby the two left digits represent the hour display and the two right digits the minute display. During this time, the signal "1" of the NOR circuit 1 is applied to the NAND circuit 6, which ^{supplies the signal 11} I "as an output signal to the NAND circuit 8, which in turn ^{generates an output signal 11} O", whereby the transmission -Gates 21,23 are brought into the ON state. The signal AC-I is applied to the AND circuit 12 and via the transmission gate 23 to the common electrode 34. After being inverted by the inverter 20, the signal AC-2 is fed to the AND circuit 11 via the transmission gate 21. The signal ¹¹ I ^{11 of} the memory NI generates a signal "0" at the output of the NOR circuit 25, as a result of which the AND gate 12 is closed.

The signal ¹¹ O "of the NOR circuit 25 is inverted into a signal" 1 "by the inverter 28, so that the AND circuit Π is opened and then the signal AC-2 is passed to the NOR circuit, whereby the Channel display SI receives or represents the signal AC-I, whereas the common electrode 34 receives the signal AC-2, so that the content of the memory Mi is displayed.

A minute decoder 35 and an hour decoder 41 supply an output signal "0" at this moment, as a result of which the output ¹¹ O "of segment g (FIG. 2) is converted into a signal" 1 "due to the inverter 36 and 42, respectively , ie the AND circuits 38, 44 receive a signal "1" at their one input from the associated inverter 36 or 42, so that these AND circuits 38, 44 are opened and the signal AC-2 is sent to the NOR circuits 39 , 45 is applied so that the. Signal

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AC-I is generated and applied to electrodes S2, S3. the common electrode 34- is thus kept at the value corresponding to the signal AC-2, so that only the segment g is a Ad supplies. Thus, when the signals from the minute and hour decoders 35, 41 are generated in this way, the display supplies a representation corresponding to the deferred state, namely (-: -), where on the segment g the signal "0" is present.

When the S _e g _rae nth α to f to the value "1" corresponding signal are held, AND circuits 37,43 are opened, whereby the signal AC-I passes; the signal AC-2 is applied to the other electrodes α to f via NOR circuits 39, 45. As a result, the common electrode receives the AC-2 signal, whereby the display area is not driven when the reset condition is established.

The memories M2, M3 are referred to in the same way above controlled on the memory MI described manner, each memory MI, M2, M3 a set input S and a Has reset input R.

Thus, in the invention, when a memory is reset, an indication (-: -) is shown so that it it is possible to distinguish this display corresponding to the deferred state from the normal display, which is given for 00 hours 00 minutes; this makes it clear when the deferred state is displayed. The display (00:00) provides a time display such as (12:15) or (8:05) etc. while in accordance with the invention the reset status is indicated by (-: -).

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Claims (1)

Electronic digital clock with alarm device, with a time control circuit, an oscillator circuit, a Contains divider circuit and a 24-hour counter, with a memory circuit for the alarm time, an alarm device for generating an alarm signal and with a display unit for displaying the content of the memory circuit, characterized in that in the reset state of the memory circuit (NI, M2, M3) the display unit (34, SI, S2, S3, etc.) provides a display without numbers. 709819/0943