DE2648149C2 - - Google Patents

Description

The invention relates to a control circuit arrangement for network-guided, Multi-pulse converters for the generation of quickly changeable Direct currents of very different sizes from a multi-phase AC network via firing angle controlled thyristors, which ignition pulses are supplied, their phase position for Mains AC voltage by control pulses depending on the comparison of a mains synchronous reference voltage with a control voltage is specified (DE-OS 22 13 612).

With such a direct current generation via ignition angle controlled Thyristors often encounter difficulties that lead to short-term very high currents, which both the Thyristors as well as consumers damage or destroy can. To avoid this, predominantly, be very quick acting fuses upstream. Protect these fuses generally sufficient from damage, but result in increased Susceptibility to failure. It is known to avoid this (see e.g. DE-OS 16 38 377), monitoring devices in the To provide control circuit for the power converter, which one Exclude firing of the thyristors in the firing angle ranges  in which too high currents could flow, or a Counter-firing of thyristors is possible. These monitoring devices However, with a strongly inductive load and in particular for generating supply voltages for reversing drives are not sufficient, or result in a too large narrowing of the ignition angle range especially when there are large changes in the load or load resistance are possible as z. B. in controllable DC drives is often the case.

It is also known to limit overcurrents (see e.g. B. DE-OS 20 42 107), via a target-actual value comparison Compensate for disturbances of the direct current. Because there are overflows by an appropriate ignition of a thyristor over a Current measurement, however, at the earliest to the following ones Ignitions can affect high peak currents individual half-waves of the AC mains voltage do not result from this avoid.

It is an object of the invention to control the power converter to enable which overcurrents also during the Runtime of individual half-waves of the AC mains voltage safely prevents even if the load resistance changes significantly, the setpoint control voltage is changed suddenly or z. B. Interference impulses are introduced via the control voltage supply will.

This object is achieved by the features characterized in claim 1. Advantageous embodiments of the invention are characterized in the subclaims.  

The control circuit is particularly advantageous Way for a converter with antiparallel connected Thyristors for the generation of direct currents, their size and Polarity can be changed via a control voltage - like this e.g. B. is common in a control of reversing drives - if both the thyristors to rectify the positive Half waves, as well as the thyristors for rectifying the negative half-waves of the AC mains voltage each have their own Timer for cycle time monitoring is assigned.

In all these cases, the duration of the invention arranged timing element a sudden increase in Prevents electricity, with an appropriate choice of Term of the timer the maximum current rise during a half-wave of the AC mains voltage the highest permissible Current can be adjusted. This can increase the current - as is generally desirable for drives - so limited  be that there is a targeted increase in current, whereby the new current setpoint, according to an optimal adjustment is only reached after 2 to n half waves. To be particularly advantageous has been used in the control of drives with DC motors a rating of the timing element has been proven, in which the smallest specified by this timer Cycle time corresponds to approximately 50 to 80% of the cycle time that one constant ignition angle setting results. Here results from a delayed maximum current rise - e.g. B. from zero current value to full load after 2 to 5 half-waves the AC line voltage - a largely independent of the motor EMF responsive yet impact-free control of the drive, a significantly reduced interference load of the AC network and for control in the particular critical phase of a sudden startup an absolute stability, because the controller then works in saturation.

A full effectiveness can be achieved with controls with faster Current turn - z. B. for reversing drives also with circulating current Power converter circuits - thereby achieve when the cycle time monitoring device has a device which if there is no control pulse, a follow-up pulse is prevented as soon as this starting from the rear zero crossing of the rectified Half waves of the alternating voltage a follow-up time would have, which is smaller than the predetermined smallest cycle time and a control pulse as soon as the Successor time corresponds to the smallest cycle time. This can be done reach when the input of the monostable multivibrator with the Output of a synchronous clock generator is connected, which at the end of each half cycle of the AC mains voltage Provides momentum and the monostable multivibrator in the astable Condition tilts, but the tilt level after being set by one  Control pulse remains unaffected.

This can prevent a thyristor, which - e.g. B. before turning the power - has not received an ignition pulse is suddenly turned on with an ignition or interference pulse, that could cause a large current spike.

This circuit can also be used with little additional effort be sure that even with highly inductive Load or large back emf where a current through one Thyristor for a long time after the voltage zero crossing the corresponding half-wave can flow, the counter-ignition over another thyristor is prevented. This becomes possible if for the control pulses to generate the direct currents the positive and negative half-waves of the AC mains voltage two similarly connected and constructed pulse monitoring devices each provided with a release device and these are two monitoring devices in one Are linked to each other in such a way that when released a control pulse through one of the release devices to at the end of the respective half-wave of the AC mains voltage other release device receives a lock signal. As release devices can use the provided AND gates each serve an additional separate input.

Based on the embodiments shown in the drawing the invention is described in more detail. It shows:

Fig. 1 shows the basic structure of a line-commutated polyphase converter according to the invention,

Fig. 2 shows the circuit principle of a cycle time monitoring device according to the invention

Fig. 3a to 3f voltage and current waveforms of the converter over several clock periods

Fig. 4 is a diagram for the dimensioning of the timing element according to the invention and

Fig. 5 shows the control circuit for a reversing converter.

In Fig. 1, the main circuits of a three-pulse thyristor converter are shown in simplified form, the three phase connections 1, 2 and 3 of a three-phase network in a known manner via a thyristor 4, 5 and 6 to a common connection point 7 of the load, which here is a DC motor 8 is the other end z. B. is located on the center conductor 9 of the three-phase network. The control circuit 10 for the converter consists, in a known manner (see, for example, DE-OS 22 13 612), of a network-synchronous clock generator 11 which clocks a reference voltage generator 12 , a control pulse logic 13 and an ignition pulse distributor stage 14 . In the reference voltage generator 12 a synchronous reference voltage z. B. sawtooth voltage is generated at three times the mains frequency, which is fed to a comparator 15 , which supplies control pulses, the phase position of which is changed in relation to the reference voltage as a function of a supplied control voltage 16 . These control pulses are supplied to the control pulse logic 13 and are forwarded from there to the ignition pulse distributor stage 14 when an external ignition pulse release signal 17 is present . The ignition pulses for the individual thyristors are then generated in this stage 14 , these being obtained from the control pulse logic 13 by selected control pulses. The control pulses are selected by synchronous pulse voltages from the clock generator 11 .

The control pulse logic 13 contains a clock monitoring device 18 according to the invention, which an analog timer such as. B. contains a blocking oscillator that prevents the transmission of follow-up pulses under a predetermined minimum cycle time and only passes this on after the smallest cycle time has elapsed. A cycle time monitoring device shown in FIG. 2 operates much more independently of external influences. There, the control pulses are fed to an input 20 of an AND gate 21 , at the second input 22 of which there is the output 23 of a first monostable multivibrator 24 , to which an enable signal for the AND gate 21 is present in the stable state. The output of the AND gate 21 is at the input of a second monostable multivibrator 25 , which passes control pulses with a constant pulse length to the next stage in a known manner. If the second flip-flop 25 is set via the leading edge of a control pulse from the AND gate 21 , it gives a pulse to the input of the first monostable flip-flop 24 via a further output 26 and tilts it into the astable state. As a result, the AND gate 21 is blocked, but this no longer has any influence on the second flip-flop 25 , which passes on this control pulse with a constant pulse width. The first flip-flop 23 is dimensioned such that it only tilts back into the stable state after a fixed or adjustable time, which corresponds to the smallest cycle time. If the leading edge of the next control pulse reaches the AND gate 21 during this time, this control pulse remains blocked until the first flip-flop tilts back, releases the AND-gate when a control pulse is applied, and sets the second flip-flop again. The cycle time of this next pulse then corresponds, irrespective of the arrival of the leading edge of the control pulse at input 20 , to the minimum cycle time which is fixed or can be set.

The effect of the cycle time monitoring is shown in FIG. 3. In Fig. 3a, the positive half waves 30 are shown of the mains alternating voltage, a network-synchronous sawtooth reference voltage 32 is generated by the rear zero crossing 31 of pulses of the clock. 11 In the comparator 15 , this is compared with a control voltage 33 ( 16 ) and a control pulse voltage FIG. 3c is generated, a front pulse edge 34 being formed as soon as the reference voltage 32 becomes smaller than the control voltage 33 and a rear pulse edge 35 being formed when it is larger again becomes. According to FIG. 3b, this takes place simultaneously with the steep rise of the sawtooth flank.

The two flip-flops 24 and 25 are set with the leading edge 34 (as already explained for FIG. 2), the first flip-flop 24 blocking the AND gate 21 by the output signal FIG. 3d for a predetermined time Tsp when the second flip-flop 25 is set . In Fig. 3e, the output pulse voltage of the second flip-flop 25 is shown, the pulses obtained by this stage, a constant pulse width. Due to the small control voltage 33 during the first three cycles shown, the corresponding thyristors receive firing pulses with an firing angle 36 , with firing only taking place shortly before the half-waves pass through zero. As a result, only small currents 37 flow in the gap operation. If the control voltage jumps high - as shown in Fig. 3b after the third cycle - the next leading edge 38 is generated in the comparator shortly after the leading edge of the previous pulse, as a result of which a control pulse 39 would be passed without the clock time monitoring device, which would transmit the corresponding thyristor with a Ignition angle 40 would ignite. This can be because e.g. B. the motor 8 could previously build up no or only a very small back EMF, lead to a very high current peak 41 , which can damage or destroy the thyristor, the motor, a response of a fuse and / or other faults.

However, since at the time of arrival of the leading edge 38 of the control pulse voltage at the AND gate, the blocking voltage 42 is present, it remains ineffective and only arises when the first flip-flop 24 tilts back 43 , which is then immediately set again by setting the second flip-flop 25 . As a result of this renewed blocking of the AND gate, the subsequent leading edge 44 cannot have an effect either. This process is repeated until the phase position is compensated for by the blocking time Tsp , which is shorter than the network-synchronous cycle time (T _N 120 °) and corresponds to the smallest cycle time. During this time, the respective firing angle changes in such a way that a larger current results according to FIG. 3f for each half-wave.

Depending on the choice of the ratios of the smallest cycle time Tsp to the network-synchronous cycle time T _N , the current rise can be limited to the maximum value even with the most unfavorable jump in the control voltage 33 such that, for. B. only the nominal current flows to the next half-wave or the nominal current is only reached after n half-waves. The curve in FIG. 4 can serve as an aid for dimensioning the smallest cycle time Tsp . The ratio of the slope time T _slope to T _{N is} specified there, which in a converter according to FIG. 1 with a DC motor corresponds approximately to the number of half-waves after which the nominal current is reached by an output current of zero. The curve corresponds to:

The larger the smallest cycle time is chosen - which, however, always has to be smaller than T _N - the softer and more stable the ramping up of the current, whereby interference pulses, which, for. B. introduced via the control voltage, largely hidden, or in the worst case can only cause disturbances that correspond to the limited current increase after a half-wave.

In Fig. 5, the control pulse logic ( 13 according to FIG. 1) for a reversing converter with anti-parallel connected thyristors is shown, the z. B. is used to control reversing drives for position control. This control pulse logic has two largely identical circuits. In each of these circuits, an AND gate 50 ( 51 ) provided with five separate inputs has its output routed to the one input of a flip-flop 52 ( 53 ), each of which has an output via a capacitor 54 ( 55 ) at the set input of one monostable multivibrator 56 ( 57 ) and with the second output at the input of a further AND gate 58 ( 59 ). The negated output of this AND gate lies via a resistor 60 ( 61 ) at the set input of a further monostable multivibrator 62 ( 63 ), which is connected with an output to one of the five inputs of the first AND gate 50 ( 51 ). To the other inputs is the connection for a network-synchronous clock signal 77 , the control pulse voltage from the associated comparator via a connection 66 ( 67 ), an external enable signal via a connection 68 ( 69 ), and the output of the flip-flop 53 ( 52 ) connected to the other circuit on which the capacitor 55 ( 54 ) is located.

The AND gate 50 ( 51 ) is then opened by the leading edge of a pulse of the control pulse voltage from the associated comparator 66 ( 67 ) when an enable signal is present at connection 68 ( 69 ) and at the other inputs there is no blocking signal. The flip-flop 52 ( 53 ) is then set by such a leading edge and a setting pulse is given to the monostable multivibrator 56 ( 57 ) via the capacitor 54 ( 55 ). The set input of this monostable multivibrator 56 ( 57 ) is connected across a parallel circuit 70 ( 71 ) of a resistor with a diode at a positive voltage, which prevents the monostable multivibrator 56 ( 57 ) from responding when the flip-flop 52 ( 53 ) is reset . This monostable multivibrator 56 ( 57 ) generates control pulses 74 of constant width, with which the ignition pulses for the corresponding thyristors are generated via an ignition pulse distributor stage ( 14 according to FIG. 1). These control pulses are simultaneously fed via a capacitor 72 ( 73 ) to the input of the monostable multivibrator 62 ( 63 ), which is connected to the output of the AND gate 58 ( 59 ) through the resistor 60 ( 61 ). The leading edges of the control pulses 74 set the monostable multivibrator 62 ( 63 ), whereas the trailing edge is deactivated by a diode ( 76 ) connected to the setting input. The monostable multivibrator 62 ( 63 ) is dimensioned such that it emits a blocking signal to the AND gate 50 ( 51 ) during a predefined or adjustable cycle time. This cycle time corresponds to the smallest cycle time Tsp . During this cycle time z. B. due to a rapid increase in the control voltage, an opening signal at the input of the AND gate 50 ( 51 ), this remains ineffective until the flip-flop 62 ( 63 ) automatically tilts back. The clock pulse 77 which arises at each rear zero crossing of the alternating voltage sets, bypassing the AND gate 50 ( 51 ) from the terminal 64 ( 65 ) via a capacitor 78 ( 79 ) to a reset input R of the flip-flop 52 ( 53 ), this regardless of this back to the initial state. The reset is carried out by the rear flank of pulse 77 , since the front flank is suppressed by means of a resistor 80 connected in parallel with a reset circuit ( 81 ) with a diode. The clock pulse 77 is simultaneously at the second input of the AND gate 58 ( 59 ), but cannot open it, since it only initiates a reset of the flip-flop 52 ( 53 ) with its trailing edge and only when the flip-flop 52 ( 53 ) an enable signal reaches the second input of the AND gate 58 ( 59 ).

Now arises z. B. by reversing the polarity of the control voltage on the comparator for a positive voltage ( 66 ) no more pulse voltage, but only on the comparator for a negative voltage ( 67 ), the AND gate 52 remains in its initial state. In this case, control pulses can then no longer occur at the output Zp , since the reverse-polarized thyristors are now fired via the control pulses at the output Z _{n of} the second circuit. Likewise now no settling takes place the flip-flop 62 more, while also disabling the AND gate is omitted by this flip-flop 62nd If the control voltage suddenly changes or an interference pulse arrives at input 66 , this can result in a very high current peak with all the disadvantages already mentioned. This is prevented in the circuit by means of the AND gate 58 which, when the flip-flop 52 is not set, always receives an enable signal therefrom, so that the clock pulses 77 set the flip-flop 62 via the second input of this AND gate. As a result, the AND gate 50 is always blocked in a range which corresponds to the firing angle range for high currents. The circuit for generating the control pulses Z _n for negative DC voltages is also protected in the same way. In order to prevent the thyristors from reigniting in the critical initial region, the clock pulses are routed to a blocking input 82 ( 83 ) of the AND gate 50 ( 51 ).

The clock pulses 77 are shifted in phase with respect to the clock pulses at the input 65 by an electrical angle of 60 ° (see also DT-OS 22 13 612), since the rear zero crossing of the corresponding half-waves ( FIG. 3a) with the front zero crossing of the half-waves opposite polarity. The same also applies to the pulse voltage from the corresponding comparators for the same ignition angle.

With a strongly inductive load or a very large back emf of the motor, it is possible that even if the control voltage does not change direction too quickly, the previously fired thyristor is still open when the firing of a oppositely directed thyristor occurs, which results in very high currents in the converter that can cause the fuse or destruction of a thyristor to respond immediately. Such counter-ignition is avoided in the control pulse logic according to FIG. 5 by linking the two circuits. For this purpose, the control pulse output 84 ( 85 ) of the flip-flops 52 ( 53 ) of one circuit is connected to a separate blocking input 87 ( 86 of the AND gate 51 ( 50 ) of the other circuit. Since the flip-flops 52 , 53 according to the Put by a front pulse edge from the associated comparator ( 66, 67 ) remain set until the arrival of the rear pulse edge of the associated clock pulse 77 , the AND gate 51 ( 50 ) is blocked for the reverse-polarized DC voltage up to a range in which a controlled counter-ignition of the thyristors is no longer possible.

The invention is particularly suitable for circuit circuits with converter circuits for responsive DC control drives, but can also offer the same advantages for other converter circuits. It is not limited to three-pulse, three-phase circuits, but in an equally advantageous manner, for. B. suitable for six-pulse or six-phase converter circuits. Especially with position control loops, it can be advantageous to let a smaller alternating current flow through the motor by alternately firing the thyristors at a control voltage zero, or likewise to allow a bias current to flow in one direction by setting the comparators appropriately at control voltage zero . B. to compensate for the weight of a system part. This means that at a control voltage of zero the converter is still working or thyristors are being fired. If the converter is to be de-energized via an external signal, this can be done via an external enable signal which is connected to the inputs 68, 69 of the AND gate 50, 51 . This safe blocking of the converter can also be advantageous for other cases, for. B. if the thyristors or other system components are to be protected by switching off via an error signal.

Claims (10)

1.Control circuit arrangement for line-guided, multi-pulse converters for generating rapidly changeable direct currents of widely differing sizes from a multi-phase AC network via ignition-angle-controlled thyristors, to which ignition pulses are supplied, the phase relationship of which to the line AC voltage is predetermined by control pulses as a function of the comparison of a line-synchronous reference voltage with a control voltage, characterized in that A device ( 18 ) for ensuring a minimum cycle time (Tsp) with an adjustable timing element ( 24; 62; 63 ) is provided, which at the beginning of a control pulse ( 39 , Fig. 3c) which triggers an ignition pulse ( Fig. 3e ) has the consequence that the triggering of the next ignition pulse ( Fig. 3e) due to the next control pulse ( 39, Fig. 3c) is delayed until the minimum cycle time (Tsp) that can be preselected with the timer ( 24; 62; 63 ) has expired. 2. Control circuit arrangement according to claim 1, characterized in that the device ( 18 ) for ensuring the minimum cycle time (Tsp) an AND gate ( 21; 50; 51 ) and - as a timing element - a monostable multivibrator ( 24; 62; 63 ) has that the control pulses ( 39 , Fig. 3e) are supplied to a first input ( 20 ) of the AND gate ( 21; 50; 51 ), that at the output of the AND gate ( 21; 50; 51 ) pulses for the Ignition pulse formation are available and that a second input of the AND gate ( 21; 50; 51 ) is connected to the output of the monostable multivibrator ( 24; 62; 63 ), the input of which is connected to the output of the AND gate ( 21; 50; 51 ) is linked in such a way that the monostable multivibrator - initially in the stable state and thereby providing an enable signal for the control pulse switching through the AND gate - tilts to the astable state with the occurrence of a control pulse and thereby the switching through of a subsequent control pulse through the UN D-link prevents the monostable multivibrator from tipping back into the stable state after the minimum cycle time (Tsp) has elapsed ( FIG. 2). 3. Control circuit arrangement according to claim 2, characterized in that the pulse voltage at the output of the AND gate ( 21; 50; 51 ) via a further monostable multivibrator ( 25; 56; 57 ) the output of the device ( 18 ) and the input of the monostable Flip-flop ( 24; 62; 63 ) is supplied ( Fig. 2, 5). 4. Control circuit arrangement according to one of claims 1 to 3, characterized in that the timing element ( 24; 62; 63 ) is dimensioned such that the smallest cycle time (Tsp) predetermined by this timing element is approximately 50 to 80% of the cycle time (120 °) corresponds, which results in a constant ignition angle setting. 5. Control circuit arrangement for a converter for generating direct currents, the size and polarity of which can be changed, according to one of claims 1 to 4, characterized in that both the thyristors for rectifying the negative half-waves, and also the thyristors for rectifying the positive half-waves of the mains AC voltage each has its own timer ( 62; 63 ) for cycle time monitoring. ( Fig. 5) 6. Control circuit arrangement for a converter according to claim 5, characterized in that the cycle time monitoring device has a device which, in the absence of a control pulse, prevents a follow-up pulse if, starting from the rear zero crossing of the half-waves of the AC voltage to be rectified, has a follow-up time which is less than the predetermined one smallest cycle time (Tsp) and a control pulse as soon as the successor time corresponds to the smallest cycle time ( Fig. 5). 7. Control circuit arrangement according to claim 3 and 6, characterized in that the input of the monostable multivibrator ( 62, 63 ) is connected to the output of a synchronous clock generator which supplies a pulse ( 77 ) at the end of each half-wave of the AC mains voltage and the monostable multivibrator ( 62; 63 ) tilts to the unstable state, but leaves it unaffected by a control pulse after setting. 8. Control circuit arrangement according to one of claims 5 to 7, characterized in that the control pulses for generating the direct currents from the positive half-waves of the mains AC voltage via a first AND gate ( 50 ) are fed to the first input of a flip-flop ( 52 ), the second input for resetting the flip-flop ( 52 ) from a synchronous clock (via connection 64 ) pulse 77 are supplied at the end of each half-wave of the mains AC voltage, that at a first output of the flip-flop ( 52 ) a connection (Zp) for Control of the corresponding thyristors and the input of the monostable multivibrator ( 62 ) are such that an input of a second AND gate ( 58 ) is connected to a second output of the flip-flop ( 52 ), and an output of the synchronous clock ( is connected via connection 64 ) and the output of this AND gate ( 58 ) is also connected to the input of the monostable multivibrator ( 62 ), whose output is connected to a further input of the first AND gate ( 50 ). 9. Control circuit arrangement according to one of claims 5 to 8, characterized in that for the control pulses for generating the direct currents from the positive and the negative half-waves of the AC mains voltage two similarly connected and constructed pulse monitoring devices are linked together in such a way that when a control pulse is released by one of the AND gates ( 50 ) until the end of the respective half-wave of the AC mains voltage, the other AND gate ( 51 ) receives a blocking signal. 10. Control circuit arrangement according to claim 9, characterized in that the AND gates ( 50, 51 ) each have a plurality of separate inputs, that the outputs of the AND gates ( 50, 51 ) each at the input of a flip-flop ( 52; 53 ) lie and an input ( 87, 86 ) of the AND gates ( 50, 51 ) is connected to an output of the flip-flop ( 52, 53 ) for pulse monitoring of the half-waves with opposite polarity.