DE2647146C2 - Voltage regulator - Google Patents

Description

The invention relates to a voltage regulator, the regulated output voltage of which as an actual value is dependent on the control is fed from a clock standing pulse width modulator, its antiphase Outputs connected to the ends of a center-tapped primary winding of a transformer are, with two switching transistors switching an unregulated input voltage, the bases of which each have one The secondary winding of the transformer is controlled by connecting it to the first winding connections are, the winding direction is designed so that the switching transistor alternately let through or block, and with a filter, at the output of which the regulated Output voltage is present.

Such a voltage regulator is known from US Pat. No. 3,670,234. This voltage regulator controls a pulse width modulated voltage a control element that consists of a pair of driver transistors, which are conductive during the switch-on period of the modulated voltage. This becomes the primary side of the "current mode" transformer short-circuited, which completely switches off the power amplifier and the one in the primary winding of the "current mode" transformer stored energy can be broken down and thus prevents the in the Secondary winding stored energy can be discharged. When the stored in the secondary winding If energy were to be discharged, this would lead to a distortion of the waveform and thus the power switching stage Partially switch on during the switch-on period and thus a drop in efficiency cause. Besides, the turns ratio of the positive feedback winding and the secondary winding, which are connected to each power transistor are chosen as the reverse current gain, so that the switching transistors have a fixed current gain in their saturation state. Another The advantage of this circuit is the reduced storage time in and associated with the power transistors an increase in efficiency. To a certain extent, this circuit also eliminates crosstalk reduced and the adaptation of the power transistors less critical, since the current gain is more depends on the external circuit parameters than on the transistor parameters.

Thus solves the »SliOinmodett transformer noise the IIS-PS 3b 70 234 many problems of the earlier switching voltage regulator. Nevertheless, the arrangement according to the US-PS also leaves unsolved problems. The majority of electronic systems operate from an electrical outlet with a voltage of 100 volts effectively supplied up to 235 volts. In the past it was

it is common to have these voltages at 50 or 60 H /. to step down with transformers on whose Sskundärseite series regulators were arranged. In some Cases, secondary switching regulators with filters were used to convert the input voltage to a voltage to reduce the z. B. could be used in a switching regulator according to US-PS 36 70 234. But even in stationary electronic systems, transformers cause size, weight and cost problems. In the arrangement according to US-PS 36 70 234 is through the use of the transformer the overall efficiency deteriorates again. Of course, the arrangement according to the US-PS cooperates Input voltages up to approximately 150 volts, which is approximately correspond to an effective voltage of 106 volts. However, there is a need for switched regulator-converters, which not only work effectively up to 106 volts, but also with the same degree of efficiency Process voltages up to 283 volts effective, corresponding to an input voltage of up to 400 volts!; Önncn.

The improvements brought about by the invention can best be seen by explaining the disadvantages of the arrangement according to US-PS 36 70 234 be understood. The US-PS 36 70 234 describes power transistors, An auxiliary circuit is provided so that the »Strommodew transformer is magnetically symmetrical equal volt-second products of the two primary partial windings from the center tap to the ends of the primary

winding causes. While this known circuit allows a symmetrical operation of the »Stromommodew-Transformer causes and is able. Process input voltages that meet the limit voltage values come close to today's power switching transistors.

ίο this is still at the expense of the size of the output voltage. This is because of the magnetic reset of the transformer and its saturation Avoid a short time of a quarter of the period of the switching voltage is necessary accordingly

the filtered output voltage could only be 75% of the input voltage of the smoothing filter.

The invention is based on the object of pulse-width modulated voltage regulators and voltage regulators to be improved with »Strommodett transformers.

scm that they deliver higher output voltages and higher output currents and are capable of higher Process input voltages than the previously known arrangements. The voltage regulator according to the invention and voltage regulator converters

which feed an output transformer in push-pull. 25 has the advantage that compared to known devices

First of all, it must be mentioned that this circuit does not in itself mean a limitation, but the limitation lies in the load limits of today's power switching transistors. If power switching transistors are to be used in switching regulators of the type jo described here, then Ve / · ») (the open base collector-emitter voltage) is the critical parameter regardless of current gain, switching speeds, etc. A Vcvo on the order of 300 to 400 volts is e.g. Currently common. Assuming that a modern power switching transistor is used in the arrangement according to US Pat. No. 3,670,234, then the upper limit of the input voltage can be approximately 150 volts. This is due to the fact that the polarities require fewer switching elements and are therefore more reliable than these.

This object is achieved by the features characterized in claim 1.

One embodiment of the voltage regulator according to the invention has one operated in "current mode" Transformer with secondary windings in common mode with two power switching transistors connected is. The primary windings of the transformer are push-pull from pulse width modulated Pulses driven by a control circuit. This control circuit receives signals from a clock generator and an error signal from the output of a filter, so that switching

th on the output transformer are such that the w signals appear that represent the magnetic operating point

Voltage at one of the power switching transistors when switched off 2 to 3ma! can be as large as the input voltage. In addition, other influences, such as B. stray inductances, voltage transitions, etc. increase the voltage between the collector and emitter of the switched-off transistor even more, so that the critical voltage rises to 400 volts, the limit voltage of today's common power switching transistors. At these ratios, a 400 volt input voltage would have a cutoff voltage of approximately 1200 volts; H. 3 times the maximum allowable voltage of today's power switching transistors. There is therefore a need for switching regulators which have the advantages of the arrangement according to US Pat. No. 3,670,234 and can operate with input voltages which approximately correspond to the Vn-o of today's power switching transistors.

Another arrangement, described in IBM Technical Disclosure Bulletin, Volume 17, No. 6, November 1974, pages 1670 to 1671 appears to solve the problem of operating at higher input voltages by providing a switching regulator that is directly connected to the collector of a single power switching transistor the input voltage is supplied. The "current mode" transformer according to US Pat. No. 3,670,234 will balance the transformer used as a coupling between the pulse width modulator and the single switching transistor mentioned above and control the switching transistors so that a high regulated output voltage can be generated. Another feature of this embodiment of the invention is that the collectors of the power sound transistors, which are connected in common mode, can be acted upon directly with the input voltage, which can correspond to the maximum value of V _C i: o of the switching transistors. Since this circuit works as a frequency multiplier , the pulse width modulated pulses with a frequency Φ for optimal switching of the power transistors at the input of the filter are increased to a frequency 2Φ, whereby the inductance of the filter can be made smaller and costs and weight can be saved.

Another advantage of this embodiment is that the voltage VVeo (the voltage between emitter and base with an open base) of the power transistors is limited to a small value, whereby voltage stresses the associated circuit parts are reduced.

Another advantage of this arrangement is that the pulse width modulator and clock are from the Single voltage decoupled by a transformer are.

In another example, a voltage regulator converter the output voltage of the first example example will push-pull a line

stungstransformator supplied. The in the first embodiment mentioned signals from the clock and the error signal are now from the output of to the Power transformer connected power filter and control the pulse width modulator as mentioned above. In addition, additional, from Clock generated signals, the power transformer synchronized with the voltage regulator converter in such a way, that the output voltage can be lowered and the output power can be increased. This embodiment has all the advantages mentioned above plus the additional advantage of having different input voltages up to the magnitude of the voltage Vc; ο the Can handle switching transistors by changing the output voltage so that it is less than the maximum operating voltage of the power transformer, d. H. about 150 volts.

Another advantage of this exemplary embodiment is the additional transformer decoupling that is provided by the power transformer is achieved.

In the solution according to the invention, the “current mode” transformer is alternately magnetized to the same extent in opposite directions, the input voltages reaching the value of the voltage Va,> of the switching transistors used. The only limitations in the switch-on and switch-off times of the switching transistors are the parameters of the switching device and the parasitic parameters of the other switching elements. With a voltage regulator according to the present invention it is possible to achieve an output voltage at the output of the filter which is 97.6% of the input voltage.

Exemplary embodiments of the invention will be explained in more detail below with reference to the drawings.

1 shows an exemplary embodiment as a block diagram a voltage regulator.

2 shows a block diagram of a voltage regulator converter with a downstream power transformer.

Fig. 3 shows the signals used in the exemplary embodiments the figure! and 2 occur.

F i g. 4 shows a hamlet of the exemplary embodiment Fi g. 2.

The essential components of the embodiment according to FIG. 1 are a switching part 10 with a transformer 18, a pulse width modulator 12, which generates pulses, the width of which depends on the magnitude of the voltage fluctuations of a regulated output voltage Vi on an output lcitcr 30. a filter 28 and a clock generator 32 which supplies the clock pulses Φ \, ^ ,, Φ ₂ and 5 & 2 to the pulse width modulator 12. The pulse width modulator 12 contains a first driver transistor 14, the collector of which is connected to a primary winding Ni of the transformer 18 and a second driver transistor 16, the collector of which is connected to a primary winding N _{2 of} the transformer 18. Between a central tap of the primary winding Ni, N2 of the transformer 18 and a bias voltage source which _{supplies the voltage V 2} , a limiting resistor 20 is connected to limit the current flowing through the primary winding Ni, N2 so that the driver transistors 14 and 16 are not overloaded. The diodes D \ and Di are connected to the collectors of the two driver transistors 14 and 16 and ground in order to establish a current path when the driver transistors 14 and 16 are switched off and to avoid the large voltage fluctuations that can be generated by the inductance of the transformer 18, to keep roughly on bulk.

An input voltage V 1 is fed to the collector of a first switching transistor 22. This switching transistor is controlled by the secondary windings Ns, N _{4 of} the transformer 18. The outer end of the winding N ₁ is connected to the base of the first switching transistor 22 and the inner ends of the windings Nj and / V ₄ , which form a tap, are connected to the emitter of this switching transistor. The outer end of the winding N ₄ is connected to an input 26 of a filter 28. The input voltage Vi is also fed to the collector of a second switching transistor 24. A second secondary winding N ₅ , N _{b of} the transformer 18 controls the switching transistor 24. The outer end of the winding Ni is connected to the base and the inner ends of the windings N? and Nb. which form a tap on the secondary winding are connected to the emitter of this switching transistor. The outer end of the winding N _b is connected to the input 26 of the filter 28.

The above-described secondary windings of the transformer 18 form a »current mode common mode circuit. The circuit components mentioned above are explained in more detail in the section entitled "Mode of Operation".

The filter 28 consists of an inductance L \, a capacitor Ci and a feedback diode Dj. The values of the inductance U and the capacitor Ci are chosen so that the switching frequency is filtered out. The filter 28 is dimensioned such that there is still a certain fluctuation in the regulated voltage V ₁ at its output 30. The feedback diode Dj is used to create a closed path for the current that flows through the inductance L \ when the two y, switching transistors 22 and 24 are switched off. It is known that very large voltage jumps can occur at the input 26 of the filter 28 as a result of the switchings due to the inductance in the circuit. The consumer Z \ can be ohmic, inductive or capacitive or a combination of these resistances. It is limited only by the values of the regulated output voltage Vi and the average current which the switching transistors 22 and 24 can deliver without overloading.

Tests have shown that the regulated output voltage Vi is approximately 97.6% of the input voltage Vi. The voltage Vj, which still contains a small voltage fluctuation due to the influence of the filter 28, is fed to a negative, inverting input of an error amplifier 46 via the output 30. _{In addition, a reference voltage V 4 is} applied to a positive, non-inverting input of the signal amplifier 46. A suitable voltage for V is, for example, 5 volts. The error amplifier 46 is a differential amplifier which converts a difference between the fluctuating voltage V3 and the voltage V ₄ into an error signal at its output 48. A clock generator 32 generates several sequences of clock pulses, such as 10 kHz clock pulses on conductors 34 and 36 Φ \ and ^ i and on the conductors 38 and 42 20 kHz clock pulses Φι and ~ Φι appear. The clock generator 32 contains a 40 kHz /? C generator and two circuits which divide by a factor of 2, so that 20 kHz and 10 kHz clock pulses are generated from the 40 kHz. In addition, inverters are also provided which generate the clock pulses ^ i and ^ 2 in antiphase.

The clock pulse sequence Φ2 on the conductor 38 controls a sawtooth generator 42. The sawtooth voltage au

the output 44 of the sawtooth generator 42 is fed to a negative, inverting input of a comparator 50. The output 48 of the error amplifier 46 is connected to the positive, non-inverting input of the comparator 50. Instead of a sawtooth voltage, the comparator 50 could also be supplied with other voltages such as /. B. in the above-mentioned US-PS 3b 70,234 is the case. The output of the comparator 50 is at high or low potential, depending on whether the error signal Vj at the positive input or the sawtooth signal at the negative input is greater. The output signal of the comparator 50 at an output 52 is fed to a first NAND element 54 and a second NAND element 56. The second input of the NAND element 54 is fed the 10 kHz clock pulse sequence Φ \ on the line 34 and the second input of the NAND element 56 is fed the inverting 10 kHz clock pulse sequence Φ \ on the conductor 36. Finally, the outputs of the first N AN D element 54 and of the second NAND element 56 are connected to driver transistors 14 and 16. In a manner known per se, the NAND gates generate a low output signal when both inputs are supplied with a high input signal and a high output signal when at least one of the inputs receives a low signal. Thus, the driver transistors 14 and 16 are switched on alternately and connected to the primary windings of the transformer 18 in push-pull. It should be mentioned again here that the secondary windings of the transformer 18 are connected to the switching transistors 22 and 24 in a common mode circuit.

In the circuit according to FIG. 2 are in addition to the Circuit parts of FIG. 1, a power driver 58, a power converter 68 and a power filter 76 are provided. These circuit parts, apart from modifications that will be explained later, are in the U.S. Patent 3,670,234.

The clock 32 supplies the 20 kHz clock pulse sequence Φι via the line 38 and the inverted 20 kHz clock pulse sequence Y'i via a line 40 to power driver transistors 60 and 62. The collector of the first power driver transistor 60 is connected to a primary winding / Vi of a power transformer 66 and the collector of the second power driver transistor 62 are connected to the primary winding N _{2 of} this transformer. Resistor 64 is connected between the center tap of the primary winding of power transformer 66 and a source of bias voltage V ₂ . Clamping diodes D ₄ and Ds are connected to the collectors of the power driver transistors 60 and 62 and to ground in order to produce a current path when the aforementioned power driver transistors are switched off so that voltage jumps that can be generated by the inductance of the power transformer 66 are held approximately at ground level. This part of the embodiment of FIG. 2 essentially corresponds to the exemplary embodiment of US Pat. No. 3,670,234, except that there is no modulation of the clock control pulses Φ2 and ~ Φ ₂ .

The secondary windings of power transformer 66 are connected to power converter transistors 70 and 72 in push-pull "current mode". A secondary winding Λ / 9 is connected between the base and the emitter of a first power converter transistor 70. Between the emitter of this transistor and ground there is a secondary winding / W A secondary winding Λ / 12 is connected between the base and the emitter of the power converter transistor 72 and also there is a secondary winding / Vn between the emitter and ground. The secondary part windings N _m and Nw are regenerative feedback

^r ) windings. which generate positive feedback in the secondary part windings N> and N-.

The collector of the first power converter transistor 70 is connected to one end of the primary winding of the Power converter transformer 74 and the collector of the second LcisUingstransisiors 72 with the other End of the primary winding of the power transformer 66 connected. The regulated output voltage Vj becomes the middle grip of the power converter transformer 74 is supplied via line 30. This part of the embodiment of FIG. 2 is similar to the embodiment according to US-PS 36 70 234, except that the feedback windings / Vm and / Vn with the emitters of the power converter transistors 70 and 72, rather than being connected to their collectors as in the U.S. Patent are. As will be explained in the section "Mode of Operation", there is a small one in this modification Advantage.

One end of the secondary winding of the power converter transformer 74 is connected to the anode of a rectifying diode D _b and the other end of the secondary winding is connected to the anode of a rectifying diode Dy . The cathodes of the rectifier diodes Dt, and Di are connected to one another and to one end of an inductance L ₂ , the other end of which is connected to a capacitor

jo tor C _{2 is} connected. The second terminal of the capacitor C ₂ is connected to ground. The values of the inductance L 1 and the capacitor Q are chosen so that the switched waveform is filtered at the operating frequency, but only to the extent that certain fluctuations in the output voltage V ₅ and on a conductor 78 are still present. These voltage fluctuations are fed to the negative, inverting input of the Fchler amplifier 46, which is part of the pulse width modulator (see FIG. 1). The resistance of the consumer Z ₂ can be ohmic, inductive or capacitive or a combination thereof. It is limited only by the values of the regulated output voltage Vj and the mean current which can be passed through the power converter transistors 70 and 72 without overloading.

The mode of operation of the exemplary embodiment according to FIG. 1 based on FIG. 3 explained. At a time shortly before 70 (FIG. 3), the switching transistors 22 and 24 are switched off. As a result, the voltage at the input 26 of the filter 28 is at a low value. In addition, at this time the 20 kHz clock pulse train Φ ₂ on conductor 38 is low, the 20 kHz clock pulse train ~ Φ ₂ on conductor 40 is high, and the 10 kHz clock pulse train Φ \ is on the Conductor 34 low and the inverted 10 kHz clock pulse train s5 | on conductor 36 at a high value. As mentioned above, these clock pulses are generated in the clock generator 32 Since the 20 kHz clock pulse sequence Φι on the conductor

bo is at a low value, the ramp voltage reaches a maximum value of the sawtooth generator 42 on the output 44. The error amplifier senses the voltage fluctuations of the regulated voltage V ₁ to the output 30 and compares this with the reference voltage V _4, so that on the output 48 an error signal is generated. Since this error signal is smaller than the sawtooth voltage, the output signal of the comparator 50 is also on the output 52

ίο

low value. This signal is fed to the first inputs of the two NAND elements 54 and 56 and since the clock pulse sequence Φ \ is fed via the conductor 34 to the / wide input of the NAND element 54 and the clock pulse sequence Φι is fed to the second input of the NAND element 56 via the conductor 36 are, the output signals of the NAND gates 54 and 56 at the bases of the driver transistors 14 and 16 are at a high value. With these input conditions described, the collector voltages at the two driver transistors 14 and 16 are at a low value, so that the primary windings N \ and Ni of the transformer 18 are short-circuited. Since no voltage is generated on the primary windings / Vi or / V ₂ , no voltage can be coupled over into the secondary windings N ₁ , Na and Ns, Nt, of the transformer iS. As a result, the switching transistors 22 and 24 are also switched off. The limiting resistor 20 is used to limit the current through the primary winding N \, N2 so that the driver transistors 14 and 16 are not overloaded. Shortly after T ₀ , the voltage at the output 44 of the sawtooth generator 42 is less than the error voltage at the output 48 of the Fchler amplifier 46. Accordingly, the output signal of the comparator 50 on the output 42 is at a high value. Since at this point in time the clock pulse sequence Φ \ is at a high value and the clock pulse sequence <P \ is at a low value, the output signal of the first NAND gate 54 is at the base of the second driver transistor 16 and at a low value, whereby this transistor is switched off . However, since the clock pulse sequence ~ Φ \ at the second input of the NAND gate 56 is at a low value, the output signal of the second NAND gate 46 at the base of the first driver transistor 14 remains at a high value and accordingly this transistor is switched on.

Since the first driver transistor 14 is switched on and the second driver transistor 16 is switched off, current flows from between the times 71) and 7Ϊ, the voltage at the output 30 rises slightly until, as shown in FIG. 3, it reaches the value of the sawtooth voltage corresponds to the output 44. During this crossing, the ·> is performed at time T _1, the output signal of the Verglcichers 50 on the output 52 is at a low value. If the error signal on output 48 is greater than the sawtooth voltage on output 44, the output signal of comparator 50 will have a high value and vice versa, if the error signal on output 48 is less than the sawtooth voltage on output 44, the output signal will be of the comparator 50 on the output 52 assume a low value. A low output signal of the comparator 50 switches the NAND gate 54 and thus the wide driver transistor 16 on. At the same time, the output of the second NAND gate 56 at the base of the first driver transistor 40 is still high and thus the transistor 14 is still on. During the time that both transistors 14 and 16 are on, both primary windings / Vi and / V ₂ of transformer 18 are short-circuited so that residual magnetization is removed and magnetic equilibrium is maintained. The short-circuiting of the primary partial windings / Vi and Nj of the transformer 18 practically also short-circuits the secondary windings, as a result of which the first switching transistor 22 is switched off. The second switching transistor 24 is already switched off and remains in this state, what

jo results from the base emitter voltages in Fig. 3. The voltage at the input 26 of the filter 28 is therefore at a low value. During this switch-off time T \ to T ₂ , the error voltage at the output 48 of the error amplifier 46 drops and the saw

j ^r > tooth tension on output 44 rises to a maximum value at time T ₂ .

At time Z ₂ , the clock pulse sequence Φ2 on conductor 38 is at a high value. Since the sawtooth voltage on output 44 is smaller than the error

Limiting resistor 20 via the primary winding 40 voltage at the output 48, the comparator ZV, through the first driver transistor 14 to ground, 50 supplies a high signal at its output 52. As a result of which a voltage drop across the primary winding / Vi results from the previous description, is then generated, the positive polarity of which in this case is at the output voltage of the second NAND element 56 at the end of the base of the first driver transistor 14 not marked with a dot on a winding N \ . Since the voltage at this point 45 is low, as a result of which this transistor is switched off minus, in the secondary winding N ₁ becomes a plus. In addition, the conditions are such that the second

Driver transistor 16 is turned on. In this case becomes, like the base emitter voltages in FIG. 1-3 show the switching transistor 22 and the reverse biased second switching transistor 24 forward biased. As above in connection with switching on the first Switching transistor 22 described, the second switching transistor 24 is now switched on and in a similar manner then as a result of the regenerative interaction of the

agreed proportion to the emitter current are, indepen- 55 secondary part windings / V ₅ and / V _b of the transformer dependent on the load of the switching transistor 22, inlet 18 more strongly turned on, the voltage at the input 26 additionally, the winding / V ₄ with respect to the winding of the Filter 28 is now positively coupled to a high value / V3 so that the feedback current and will remain there until time Tj.
- In this case one fifth of the emitter current is the mode of operation _{during times T3 to T 4}

the current in the winding N) combined, so that the t> o is the same as between the times T \ and T ₂ . While switching transistor 22 is turned on more strongly. As the period is the output of the comparator

voltage from the base to the emitter of the first switching transistor 22 is generated. Thus, a small current flows through the base, which causes a collector and thus also an emitter current, which flows through the first secondary partial winding Na. In the present case, the turns ratio of the windings / V ₄ to / Vj is 1: 5. In this way, a residual drive signal is generated at the base and consequently the base current is always

Point polarities are chosen so that a negative voltage at the point polarity of the winding / V, and so that occurs at the base of the second switching transistor 24, the switching transistor 24 is switched off. the The voltage on the input 26 of the filter 28 is at a high value and remains at this value until briefly before Ti, as in FIG. 3 shown.

50 on a low value. As a result, the output signals c of the two NAND gates 54 and at the bases of the two driver transistors 16 and 16 are at a high value, as a result of which the driver transistor 14 is switched on and the driver transistor 16 remains switched on. In this state, the primary part windings are Λ / | and / V ₂ of transformer 18 short-circuited,

whereby the two secondary windings are also short-circuited are. Accordingly, the voltage at the input 26 of the filter 28 is also at a low value. During this time, as mentioned above, the Switching transistors 14 and 16 turned on, whereby the ■> Primary windings of the transformer are short-circuited and any magnesia current removed from them will. Thus, during a complete cycle, the transformer 18 becomes equal and opposite Directions operated, whereby the magnetic working point is centered. In this mode of operation the transformer can no longer reach saturation. As a result, the first and second Switching transistor 22 and 24 operated in the linear range.

The mode of operation of the embodiment in FIG. 2 is essentially the same except that conductor 30 is now connected to the center tap of power transformer 74. In addition, the 20 kHz clock pulse trains Φ ₂ and Φ> on conductors 38 and 40 are fed to the bases of power driver transistors 60 and 62. The mode of operation of the power driver transistors 60 and 62 is essentially the same as that of the driver transistors 14 and 16. The power transformer 66 is connected in the "current commodity" phase. This circuit corresponds essentially to that of US Pat. No. 3,670,234. The main difference is that the power driver 58 is not operated with a pulse-width modulated voltage, but with an unmodulated voltage, so that it is in synchronism with the voltage in the arrangement according to FIG. 1 is located. The power driver 68 has feedback windings / Vio and / Vi i which are here in the emitter circuits instead of in the collector circuits as in the exemplary embodiment of the US Pat. The circuit according to the present invention is able to operate at higher voltages than the circuit according to the US-PS because the emitter feedback mentioned above reduces undesirable oscillations at the higher voltage. The power converter 68 includes power converter transistors 70 and 72 which are turned on by the above-mentioned clock pulse trains so that they switch the power converter transformer 74. In the present case, the power converter transformer 74 transforms down because it has a turns ratio of 20: 1. It should be mentioned here that there is no regulation in the power converter. After rectification by means of two rectifier diodes D _n and Dj and filtering in the power smoothing filter 76, the output voltage V on the conductor 78 is fed back to the negative, inverting input of the error amplifier 46 in the pulse width modulator 12. The positive, non-inverting input of the error amplifier 46 has, as in FIG. 1, a reference voltage V4 which is set so that there is an error signal at the output 48 of the error amplifier 46, as shown in FIG. 3 shown

The voltage regulator in FIG. 2 is used as a pre-regulator to generate a regulated voltage on the conductor 30, while the actual power conversion takes place in the power converter 68. Since the regulated voltage V3 on the conductor 30 is only significantly lower than the input voltage Vi, the total output of the arrangement, according to FIG. 2 increased. In addition, the voltage regulator converter according to b5 F i g. 2 able to process input voltages of a wide range with high efficiency. For input voltages below 150 volts, the arrangement works as described above. For input voltages above 150 volts, the reference voltage V ₄ (see FIG. I) is adjusted so that the voltage on conductor 30 is 150 full or lower. A change in the value of the Bc / .ug voltage V ₄ changes the period of the voltage at the input of the smoothing filter 28 and consequently changes the regulated voltage Vj.

The feedback of the voltage Vj, as it is shown in FIG 76 are connected in cascade with the switching elements LiCi-L ₂ C _2. This circuit becomes less stable when the control gain increases, since the two-pole circuit consisting of the inductance Li and the capacitor Ci moves into the right half of the S-plane.

Attempts have been made to improve this type of feedback by increasing the value of the capacitor Ci in the filter 28 in order to attenuate the feedback gain and achieve zero gain at the frequency transition before the resonance frequency of the inductance L ₂ and the capacitor Q Phase reversal occurs. This technique has generally been successful. Nevertheless, undesirable vibrations have made this solution useful in applications where high quality such as e.g. B. arrives in computers, limited. In addition, the impedance of the consumer Z ₂ generally contains additional decoupling capacitances which lower the resonance frequency of the power filter 76 and thus cause a phase reversal at a lower frequency.

In Fig. 4 is a further development of the circuit according to FIG F i g. 2 shown with two cascaded LC filters, in which the instabilities described above are eliminated. The voltage regulator converter according to Fig. 4 combines the excellent filter properties a four-pole closed control loop with the stability properties of a two-pole closed Control loop.

The voltage control converter according to Fig. 4 differs only through the somewhat more drawn out circuit parts of the voltage-regulator-converter according to FIG. 2. For this reason, the reference numbers of the parts that have remained unchanged have been retained. One Description of these parts of the circuit of FIG. 4 is unnecessary.

The inductance L \ in F i g. 2 is in FIG. 4 replaced by a transinductor 80. A transinductor is understood here to mean an inductance / Vu with a coupled secondary winding / Vi ₄ . The primary winding Μ j of the transinductor supplies the inductance necessary for filtering, while the secondary winding Nu of the transinductor 80 supplies a feedforward voltage to the input of the line filter 76.

The feedforward voltage is applied directly to the power filter 76 via the secondary winding N _{u of} the transinductor 80. One end of the secondary winding Λ / η is connected to one end of the inductance L _{2 of} the transinductor 80 via the conductor 78. The other end of the winding / Vh is connected via conductor 77 to the cathode of the rectifier diode D _b and Dj.

The winding sense of the secondary winding Nu of the transinductor is like this. that the voltage at the secondary winding Ni _{4 of} the power converter transformer during the switched-on part of the imDulsbreit-

13th

modulated duty cycle is supported and that the voltage at the secondary winding of the power converter transformer 74 is balanced during the cut-out part thus provides stable closed-loop control. The DC bias voltage introduced by the secondary winding of the transinductor 80 also improves the operating point of its hysteresis loop and thus generates a significantly higher inductance than without the secondary winding / V _u .

The turns ratios of the primary winding N ₁ and the secondary winding / Vu of the transinductor 80 are not critical. In the present exemplary embodiment, the primary winding Nm has 80 turns in which a current of approximately 3 amperes flows, and the secondary winding .Vh has two turns in which a current of approximately 50 amperes flows under normal operating conditions. It was found that the above-mentioned turns ratio and the associated currents have an influence on the magnetic operating point in the hysteresis loop of the transinductor 80, which leads to a significantly higher inductance than without the winding / V | 4l. This improvement allows the use of a smaller inductance , which is represented by the primary winding Λ / π of the transinductor 80.

Although the in Figs. 1, 2 and 4 shown Ausfüh- jo Approximation examples each have two switching transistors 22 and 24, further transistors can be used in parallel with these transistors Transistors are switched in order to be able to switch larger currents. This can be done in practice that in the emitter circuits of the transistors resistors are switched on to the operating voltages to adjust.

For this purpose 4 sheets of drawings

S5

W)

Claims (6)

Patent claims: 1.Voltage regulator, the regulated output voltage of which is fed as an actual value to a pulse width modulator which is controlled by a clock and whose antiphase outputs are connected to the ends of a primary winding of a transformer with a central tap, with two switching transistors that switch an unregulated input voltage and whose bases each have a secondary winding of the transformer are controlled by connection to the first winding connections, the winding direction of which is designed so that the switching transistors alternately let through or block, and with a filter, at the output of which the regulated output voltage is available, as characterized by the fact that the collectors of the push-pull switching transistors ( 22, 24) are connected directly to the input voltage source (Vl) and their emitters are each connected to a tap of the two secondary windings (Ni, Ny, / V5. / V _h ), while the third connections of the secondary windings (Ni, / V ₄ ; Ni, N _b ) are connected to the input of the filter (28). 2. Voltage regulator according to claim 1, characterized in that the taps of the secondary windings (N4, / Vj; Ni, Nb) connected to the emitters of the switching transistors (22, 24) are closer to the filter (18) than the bases, in particular in the Share ratio 1: 5. 3. Voltage regulator according to claim I or 2, characterized in that the filter (28) filters out vibrations of a first clock frequency Φι of the clock generator (32). 4. Voltage regulator according to one of claims 1 to 3, characterized in that a clocked voltage converter (58,68, 76) is provided with a constant Taklimpulsfrequenz- and width, the control inputs are connected to the clock (32), the supply DC voltage on the Filter (28) is the regulated output voltage (V3 ) on the output side and which generates a further output voltage (V5) which is fed to the pulse width modulator (12) as an actual value. 5. Voltage regulator according to claim 4, characterized in that the control inputs of the clocked voltage converter are the bases of two push-pull connected power driver transistors (60, 62), the collectors of which are connected to the ends of a primary winding provided with a center tap (N 7, Λ / 8) of a power transformer (66) are connected and whose emitters are through diodes (D 4, D 5) connected to reference potential, in that the ends of the secondary winding (N9, Λ / 10 / VIL / V 12) of the Leistungsfor- Y, mators (66) with the bases of two power converter transistors ( 70, 72), a center tap of the secondary winding (N 9, Λ / 10; / VIl, N 12) with reference potential, the emitters of the power converter transistors (70, 72) with taps on the secondary winding ( N 9, wi N 10; / V 11, N 12) of the power transformer (66), the collectors of the l.eishingswamller transistors (70, 72) with the ends of the primary winding of a l.eistungswandler-transformer (74) and the mutel tap this primary winding with the output μ of the filter (28) are connected that to the secondary winding of the LeiMungswandlcr Trunsformialors (74) rectifier (Db. D7) and a l.eisiungsfilter (76) are switched on and that the further output voltage (V 5) is present at the output of the power filter (76). 6. Voltage regulator according to claim 5, characterized in that the filter (28) and the power filter (76) each have a series inductance (N 13; L 2) , that the filter (28) one with the associated series inductance (N 13) is magnetic coupled secondary winding (N 14) and that this secondary winding (N 14) is connected in series between the rectifier (D6, D7) and the series inductance (L 2) of the power filter (76).