DE2638867A1 - Self-commutating MOS FET prodn. - uses insulating film for control contact through which ions are implanted to form high ohmic layer in substrate - Google Patents

Self-commutating MOS FET prodn. - uses insulating film for control contact through which ions are implanted to form high ohmic layer in substrate

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Publication number
DE2638867A1
DE2638867A1 DE19762638867 DE2638867A DE2638867A1 DE 2638867 A1 DE2638867 A1 DE 2638867A1 DE 19762638867 DE19762638867 DE 19762638867 DE 2638867 A DE2638867 A DE 2638867A DE 2638867 A1 DE2638867 A1 DE 2638867A1
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Germany
Prior art keywords
ions
ohmic layer
self
high ohmic
implanted
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19762638867
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German (de)
Inventor
Guenter Dipl Phys Ott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
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Licentia Patent Verwaltungs GmbH
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Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Priority to DE19762638867 priority Critical patent/DE2638867A1/en
Publication of DE2638867A1 publication Critical patent/DE2638867A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The self-commutating MOs field-effect transistor is produced by implanting non-doped, or compensating, ions into the semiconductor substrate, in order to produce a high ohmic layer. This implanting is carried out after the formation of a thin insulating film for retention of the control contact. After this implantation a second ion implantation is carried out, using doped ions, in order to form a channel whose penetration depth in the semiconductor substrate is smaller than that of the high ohmic layer. Preferably neon or silicon ions are implanted into the semiconductor substrate for the formation of the high ohmic layer.

Description

Verfahren @m Herstellen eines Method @m making a

selbstleitenden ;40S-Feideffektrans istors Die Erfindung betrifft ein Verfahren zum erstellen eines selbstleitenden MÜS-Feldeffekttransistors. Derartige Feldeffekt transistoren vom sogenannten "Verarmungstyp" weisen bereits ohne Steuerspannung einen leitenden Kanal auf. self-conducting; 40S field effect transistors The invention relates to a method for creating a self-conducting MÜS field effect transistor. Such Field effect transistors of the so-called "depletion type" already have no control voltage a conductive channel.

Er entsteht beispielsweise dadurch, daß man die in der Oxydschicht über dem Kanalbereich stets bereits vorhandenen Ladungen wirksam werden läßt. Sie verursachen schon bei einer Spannung O an der Steuerelektrode gegenüber der Sourceelektrode eine Inversion des p-leitenden Substrats unmittelbar unter der Oxydschicht, so daß ein n-leitender Kanal zwischen den gleichfalls n-leitenden Drain- und Sourcezonen zustandekommt. Man kann aber einen Feldeffekttransistor vom Verarmungstyp auch dadurch herstellen, daß man den anal in Form einer schwach dotierten Zone unterhalb der Steuirelektrode durch einen zusätzlichen Diffusionsprozeß erzeugt.It arises, for example, that one in the oxide layer Allows already existing charges to take effect over the channel area. she cause even at a voltage O at the control electrode opposite the source electrode an inversion of the p-type substrate immediately below the oxide layer, so that an n-conducting channel between the likewise n-conducting drain and source zones comes about. But you can also use a depletion type field effect transistor by doing this produce that the anal in the form of a weakly doped zone below the Control electrode generated by an additional diffusion process.

Es hat sich nun bei logischen Verknüpfungsschaltungen mit MOS-Pelde£rekttransistoren gezeigt, daß sich in diesen Transistoren eine Substratvorspannung einstellt, wenn über sie die Lastkapazitat geladen wird. Diese unerT,/.inschte Substratvorspannung erhö'-lt die Schwellenspannung des Feldeffe#:ttransistors, was zu einer Abnahme des Stromes durch den Lasttransistor und damit zu einer Vergrößerung der Scltzeit führt. Der Erfindung liegt daher die Aufgabe zugrunde, ein Verfahren zum Herstellen von selbstleitenden MOS-Fe3deffekttransistoren anzugeben, bei denen die Abhängigkeit der Schwellenspannung von einer Substratvorspannung geringer oder überhaupt nicht vorhanden ist. Diese Aufgabe wird erfindungsgemäß dadurch gelöst, daß nach der Herstellung der für die Aufnahme des Steuerkontaktes vorgesehenen dünnen Isoliersicht durch diese Isolierschicht in den Halbleiterkörper zur Erzeugung einer hochohmigen Schicht Ionen einer nichtdotierenden oder kompensierenden Ionensorte eingebracht werden und daß danach durch eine zweite Ionenimplantation mit dotierenden Ionen der Kanal erzeugt wird, dessen Eindringtiefe im Halbleiterkörper geringer ist als die der hochohmigen Schicht.It has now been found in the case of logic gating circuits with MOS-Pelde £ recttransistors shown that in these transistors a substrate bias sets when the load capacity is charged via it. This undesired substrate bias increases the threshold voltage of the field transistor, which leads to a decrease of the current through the load transistor and thus to an increase in the switching time leads. The invention is therefore based on the object of a method for manufacturing of self-conducting MOS Fe3deffekttransistorsen specify, in which the dependency the threshold voltage from a substrate bias is less or not at all is available. According to the invention, this object is achieved in that, after production through the thin insulating layer provided for receiving the control contact this insulating layer in the semiconductor body to produce a high-resistance layer Ions of a non-doping or compensating ion type are introduced and that afterwards the channel is formed by a second ion implantation with doping ions is generated, the depth of penetration in the semiconductor body is less than that of high resistance layer.

Die hochohmige Schicht isoliert den Kanal vom Substrat, so daß bei diesem Aufbau der Feldeffekttransistoren die Substratvorspannung keinen Einfluß auf die Schwellenspannung mehr hat. Zur Erzeugung der hochohmigen Schicht unter dem Kanalgebiet haben sich insbesondere Neon- oder Siliziumionen als geeignet erwiesen.The high-resistance layer isolates the channel from the substrate, so that at The substrate bias has no influence on this structure of the field effect transistors has more on the threshold voltage. To generate the high-resistance layer below In particular, neon or silicon ions have proven to be suitable for the channel region.

Die Erfindung und ihre weitere vorteilhafte Ausgestaltung wird noch anhand eines Ausführungsbeispieles näher erläutert.The invention and its further advantageous embodiment will still be explained in more detail using an exemplary embodiment.

In der Figur 1 ist im Schnitt ein Halbielterkörper 1 daigestellt, dessen Ausgangskörper 2 beispielsweise n-dotiert ist.In the figure 1, a half-end body 1 is shown in section, whose output body 2 is, for example, n-doped.

Der Halbleiterkörper, der vorzugsweise aus einkristallinem Silizium besteht, ist an seiner Oberfläche mit einer Oxydschicht 2 bedeckt. In diese Oxydschicht wurde ein Fenster 8 eingebracht, das den Abmessungen des herzustellenden Feldeffekttransistors entspricht. Dieses Fenster 8 wird wiederum mit einer dünnen Oxydschicht 4 bedeckt, die nur über dem Kanalbereicji auf der Halbleiteroberfläche belassen wird.The semiconductor body, which is preferably made of monocrystalline silicon exists, is covered with an oxide layer 2 on its surface. In this oxide layer a window 8 was introduced, which corresponds to the dimensions of the field effect transistor to be produced is equivalent to. This window 8 is in turn covered with a thin oxide layer 4, which is left only over the channel area on the semiconductor surface.

Diese dünne Oxydschicht ist beispielsweise 0,1 bis 0,3 /um dick. Danach wird die Halbleiteroberfläche einer Ionenstrahlung 5 ausgesetzt, die aus nicht dotierenden oder kompensierenden Ionen, beispielsweise Silizium- oder Neonionen, besteht. Diese Ionen treffen beispielsweise mit einer Dosis von 100 keV auf die ISalbleiteroberfläche auf und verursachen im Halbleiterkörper eine extrem schwach dotierte und damit hochohmige Halbleiterzone 6, die beispielsweise eine Eindringtiefe von 1 bis 2 /um aufweist.This thin oxide layer is, for example, 0.1 to 0.3 μm thick. Thereafter the semiconductor surface is exposed to ion radiation 5 consisting of non-doping or compensating ions, for example silicon or neon ions. These Ions hit the semiconductor surface with a dose of 100 keV, for example and cause an extremely weakly doped and thus high resistance in the semiconductor body Semiconductor zone 6 which, for example, has a penetration depth of 1 to 2 μm.

Danach wird die Halbleiteroberfläche einer zweiten Ionenstrahlung ausgesetzt, die nun allerdings dotierende im Halbleiterkörper beispielsweise den p-Leitungstyp erzeugende Ionen enthält. Bei einem n-leitenden Crundkörper werden so beispielsweise Borionen in den Haibleiterkörper implantiert. Die Strahlungsenergie dieser Borionen bet beispielsweise 20 bis 50 keV bei einer Dosis von ca. 1012 Borionen/cm3. Auf diese Weise erhält man ein p-leitendes Kanalgebiet 7 mit einer Störstellenkonzentration von ca.After that, the semiconductor surface is subjected to a second ion beam exposed, which is now, however, doping im Semiconductor bodies, for example contains ions generating the p conductivity type. In the case of an n-conducting basic body for example boron ions are implanted in the semiconductor body. The radiant energy these boron ions are, for example, 20 to 50 keV at a dose of approx. 1012 boron ions / cm3. In this way, a p-conducting channel region 7 with an impurity concentration is obtained from approx.

1017 Atomen/cm3 und einer Eindringtiefe von einigen Zellntel um Wie sich aus der Figur 2 ergibt, werden nun noch die Zonen 9 und 10 in den Halbleiterkörper eindiffundiert. Hierbei wirkt die Oxydschicht 4 über dem Kanalgebiet als Diffusionsmaske. Die Sourcezone 9 ist somit über das Kanalgebiet 7 mit der Drainzone 10 bei der Steuerspannung 0 verbunden.1017 atoms / cm3 and a penetration depth of a few cells around Wie 2, the zones 9 and 10 are now also in the semiconductor body diffused. Here, the oxide layer 4 acts as a diffusion mask over the channel region. The source zone 9 is thus at the control voltage via the channel region 7 with the drain zone 10 0 connected.

An die Sourcezone 9 und an die Drainzone 10 werden schließlich noch die zugehörigen Anschlußkontakte 11 und 12 angebracht, während auf der Oxydschicht 4 der Steuer- oder Gatekontakt 13 angeordnet ist.Finally, the source zone 9 and the drain zone 10 are also the associated terminal contacts 11 and 12 attached while on the oxide layer 4 the control or gate contact 13 is arranged.

Es hat sich gezeigt, daß nach dem geschilderten Verfahren hergestellte Feldeffekttransistoren eine Schwellenspannung aufweisen, die von einer sich einstellenden Substratvorspannung fast völlig unabhängig ist.It has been shown that produced by the method described Field effect transistors have a threshold voltage that is determined by a setting Substrate bias is almost completely independent.

Claims (2)

P a t e n t a n s p r ü c h e O Verfahren zum Herstellen eines seibstieltenden MOS-Peldeffekttransistors, dadurch gekennzeichnet, daß nach der Herstellung der für die Aufnahme des Steuerkontaktes vorgesehenen dünnen Isolierschicht durch diese Isolierschicht in den Halbleiterkörper zur Erzeugung einer hochohmigen Schicht Ionen einer nichtdotierenden oder kompensierenden lonensorte eingebracht werden und daß danach durch eine zweite Ionenimplantation mit dotierenden Ionen ein Kanal erzeugt wird, dessen Eindringtiefe im Halbleiterkörper geringer ist als die der hochohmigen Schicht. P a t e n t a n s p r ü c h e O Method for producing a self-contained MOS pelde effect transistor, characterized in that after the production of the for the reception of the control contact provided through this thin insulating layer Insulating layer in the semiconductor body to generate a high-resistance layer of ions a non-doping or compensating ion species are introduced and that then a channel is generated by a second ion implantation with doping ions whose penetration depth in the semiconductor body is less than that of the high-resistance Layer. 2) Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zur Erzeugung der hochohmigen Schicht Neon- oder Siliziumionen in den Halbleiterkörper eingebracht werden. 2) Method according to claim 1, characterized in that for generating of the high-resistance layer, neon or silicon ions are introduced into the semiconductor body will.
DE19762638867 1976-08-28 1976-08-28 Self-commutating MOS FET prodn. - uses insulating film for control contact through which ions are implanted to form high ohmic layer in substrate Pending DE2638867A1 (en)

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DE19762638867 DE2638867A1 (en) 1976-08-28 1976-08-28 Self-commutating MOS FET prodn. - uses insulating film for control contact through which ions are implanted to form high ohmic layer in substrate

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DE19762638867 DE2638867A1 (en) 1976-08-28 1976-08-28 Self-commutating MOS FET prodn. - uses insulating film for control contact through which ions are implanted to form high ohmic layer in substrate

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012889A2 (en) * 1978-12-29 1980-07-09 International Business Machines Corporation Device for diminishing the sensitivity of the threshold voltage of a MOSFET or a MISFET to variations of the voltage applied to the substrate
FR2616271A1 (en) * 1987-06-03 1988-12-09 Mitsubishi Electric Corp INTEGRATED CIRCUIT INCLUDING IN PARTICULAR A MESFET PROTECTED AGAINST LEAKAGE CURRENTS, ON A SEMI-INSULATING SUBSTRATE
US6714712B2 (en) 2001-01-11 2004-03-30 Dsm N.V. Radiation curable coating composition

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012889A2 (en) * 1978-12-29 1980-07-09 International Business Machines Corporation Device for diminishing the sensitivity of the threshold voltage of a MOSFET or a MISFET to variations of the voltage applied to the substrate
EP0012889A3 (en) * 1978-12-29 1981-12-30 International Business Machines Corporation Device for diminishing the sensitivity of the threshold voltage of a mosfet or a misfet to variations of the voltage applied to the substrate
FR2616271A1 (en) * 1987-06-03 1988-12-09 Mitsubishi Electric Corp INTEGRATED CIRCUIT INCLUDING IN PARTICULAR A MESFET PROTECTED AGAINST LEAKAGE CURRENTS, ON A SEMI-INSULATING SUBSTRATE
US6714712B2 (en) 2001-01-11 2004-03-30 Dsm N.V. Radiation curable coating composition
US6838515B2 (en) 2001-01-11 2005-01-04 Dsm Ip Assets B.V. Process for the preparation of esters of (meth)acrylic acid

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