DE2637019B2 - Switching device - Google Patents

Description

The invention relates to a connection device for establishing a connection between a transmission and / or receiving unit and a line for transmitting data, with signal generating devices, on the line an electrical signal with a dependent on the usage state of the line Generate parameters.

There are numerous data processing systems in which several terminals or sub-connections are used a common central unit for data storage and processing are connected. In such Systems, it is desirable that the individual sub-connections and the central unit as economical as possible Way can be connected to each other. The worst possible solution to this problem is arguably therein, between each individual sub-connection and the central unit, a special cable or data line to be provided. Namely, if the sub-connections are at a considerable distance from the central unit are arranged, then the costs for separate data lines alone can be a decisive factor Represent factor. In addition, the cost and labor for installation are also more numerous Data lines quite considerably, especially if the sub-connections and / or the central unit are retrofitted be installed in an existing building or the like. With systems, with where the central unit only ever has to be in connection with one sub-connection, it is extreme advantageous if each of the sub-connections are connected to a single common data line can. Such a system has been proposed before.

However, if several sub-connectors need to be connected to the same line, then it is required to ensure that only one sub-connection is on the line at any one time is switched on and is in connection with the central unit. With dialing systems in which a sub-connection is only switched to the line if it receives a specific from the central unit Receiving dial signal, this requirement is relatively simple to meet. In systems without dialers, where each sub-line is to any At the time the attempt can be made to connect to the line, the circumstances are, however much more difficult. In this case, switching devices must be provided which ensure that when a sub-connection is connected to the line, there is no further sub-connection on the Line can intrude. In addition, switching devices must be provided which ensure that when two or more sub-ports are attempting to connect to the line at substantially the same time to connect, only one of them is actually connected to the line.

Problems of the type set out above have already been addressed in the field of telex typing deals. If a number of teleprinters are connected in parallel to one another on a single data line, it is of course desirable that only one teleprinter can operate at a time. At one far The most common system is therefore a holding relay at each connection between the wires of the data line switched, which must be closed so that the teleprinter can work, with a potential source in series with a push button and the relay winding. Lies between the wires of the data line also a power source. The circuit arrangement is designed so that if no teleprinter with the line is connected and the switch on a teleprinter is closed, the relay this Teletypewriter is closed and kept in the closed state in order to connect to the Establish line. The closed state of the relay of a teleprinter now has the consequence that the potential on the data line drops below the value for the hold circuit of the relays of the other Teletypewriters would be required if their switches were closed. So if a teleprinter is connected to the data line, it is prevented that any other teleprinter on the data line can be switched on. If a subscriber tries to access the teletype device To activate the line and this is already busy, then he must press the button or the switch on his Operate the teletypewriter again and again until the line is interrupted perhaps once free is.

In other previously known systems, only the data on the data line is monitored. That The presence of invalid data is interpreted as an indication that more than one sub-connection is on the Line is connected, whereupon all sub-connections are disconnected from the line. the Both attempts to solve the problem described above have disadvantages, which without further can be seen. The disadvantage of the system considered in the first place is that the A sub-unit is not automatically connected when the line becomes free. In addition, there is in the known system, the risk that it is not fully used, especially when the to messages to be transmitted are relatively short. The main disadvantage of the second considered System consists in the fact that initially several sub-connections can intrude on the line and that then the connection to all sub-connections is interrupted, which leads to the interruption of a existing connection leads.

Based on the prior art described above, the invention is based on the object to propose a connection device for a system with several sub-units or connections which the fact that a sub-unit is connected to the line prevents another Sub-unit can be switched to the line and in which also when terminating a an existing connection automatically activates a previously prepared subunit to the Management takes place. In addition, it should be achieved according to the invention that when two subunits essentially simultaneously trying to intrude on the line, automatically an interruption both intrusion processes is brought about.

This object is achieved by a switching device of the type described at the outset, which according to of the invention is characterized in that connecting devices for connecting the switching device to the line are provided that the first the parameter responsive detector devices are provided which at an output a first generate electrical signal if the value of the parameter differs from that given for the free line The nominal value of the parameter differs by a first predetermined amount that the second on the parameter responsive detector devices are provided which are connected to the comparison devices and generate a second electrical signal at an output when the value of the parameter reaches the Connection devices from the nominal value of the parameter specified for the free line by one second predetermined amount differs, which is greater. than the first predetermined amount that first switching means are provided to repeatedly generate a third electrical signal at an output, the second Switching means are provided to generate a fourth electrical signal at an output when a Connection to the line is desirable that third switching means are provided to the connection devices effective impedance, in particular the impedance of the connection devices as a function of to change from a fifth electrical signal at an input that fourth switching means is provided are connected to the output of the first detector device, to the output of the first switching means, with the output of the second switching means and to the input of the third switching means are connected to the fifth electrical signal when the first, third and fourth electrical signals occur simultaneously

bo to apply the input of the third switching means, unless the second electrical signal is present at the same time is.

It is an advantage of the connection device according to the invention that the connection of a prepared

h> subunit on the line takes place automatically as soon as the line becomes free. It is a further advantage of the Aufschalteinrichlung according to the invention that the Connection of all other sub-units to the

Line is automatically prevented if a sub-unit is connected to the line.

It is also an advantage of the intrusion device according to the invention that interruption devices can be provided which, when attempting several subunits at the same time, relate to the Connect the line, interrupt the connection process and postpone the connection attempts ensure that one of the waiting sub-units is automatically connected to the line will. This also has the advantage that for all waiting sub-units essentially the there is an equal chance of being connected to the line first.

Another decisive advantage that the switching device according to the invention brings with it, is that with their help it is possible to build an existing system without making changes to the sub-units or expand the central unit with additional connections. In all of this, the switching device is according to the invention simply and economically constructed and very easy to use.

In a preferred embodiment of the invention, a current source is located between the wires of the line, and when a subunit is connected to the line, a resistor is placed between the wires of the same, whereby the voltage on the line is lowered below a first voltage level. This reduced voltage is now detected on the other subunits, and this prevents them from being connected to the line. Each sub-unit also contains an oscillator and can only lock onto the line when an output pulse from the oscillator is present. If now two sub-units try essentially simultaneously to lock into the line, then the voltage across the line is lowered to a second and lower voltage level, as a result of which both sub-connections are again separated from the line. Thereafter then attempts ao each sub-terminal repeated to lock onto the line, namely at each output pulse of its oscillator to due to the different frequencies of the individual oscillators one of the subsidiary ports is switched in time by as much earlier than the next to the line that the next sub-connection already determines the conditions for a busy line and thus cannot be connected to this line.

The invention is explained in more detail below with reference to drawings in connection with a monitoring system, which comprises a central unit and several monitored connections or monitoring connections, each having a connection device according to the invention, which in the following in y> with regard to the fact that in connection attempts several Sub-connections automatically ensures a balance of interests in the sense of an optimal use of the capacity of the system, is referred to as a balancing circuit. It shows M>

1 shows a schematic Bjock circuit diagram of a monitoring connection a monitoring system according to the invention,

F i g. 2 is a schematic block diagram of the central processing unit of the monitoring system with Übcrwachungs- <■ connections according to FIG. 1,

Fig. 3 shows an identifier for use in connection with an overriding extension according to Fig. I, F i g. 4 shows a table to explain the function of the monitoring connections and the central unit according to FIG F i g. 1 and 2,

F i g. 5 is a schematic block diagram of a compensation circuit for a monitoring connection according to FIG. 1 and

Fig. 6 is a series of timing diagrams for explaining the operation of the compensation circuit according to FIG. 5.

In the individual figures of the drawing is a Monitoring system shown, which is particularly suitable for use in conjunction with multiple photocopiers suitable is. The monitoring system for controlling the use of each copier consists of monitoring connections 10, as shown in FIG. 1 and a central unit 12 as shown in FIG is shown. A monitoring connection is assigned to each copier to be monitored. At a Monitoring system according to the invention, it is also advantageous to have a plurality of monitoring connections assign a common central unit, so that with the help of the central unit a corresponding number of Copy machines can be monitored.

First of all, the mode of operation of the monitoring system according to the invention should be seen from the perspective of a user explained. Each authorized user receives an identification element 14 or an identification card, as shown in Fig. 3 is shown. The identification element has several perforations in a matrix with ten columns and ten rows can be arranged, the columns and rows of the matrix, as shown in FIG. 3 shows by Rectangles on the identification element is marked. Each hole punched in a column corresponds to a decimal number. The coded numbers on the identification element of each individual user contain the information for Identification of this user and offer security against the production of forged identification elements. at In the monitoring system under consideration, there are two columns of the identification element for the department number provided by the user, three columns are provided for the individual identification of the individual user ir of the department, a column is provided for the identification of the rank of the user and the remaining four columns are for safety information. The security adviser can contain, for example, an identification number of the monitoring system for which the identification element may be used. The remaining security numbers can then be calculated check digits be. The security numbers can also be a combination of an identification number and a check digit be. The ranking number opens up the possibility of designing the monitoring system in such a way that certain Copier machines connected to the system can only be used by certain people.

Each monitoring connection 10 contains a reader 16 for reading the identification cards or identification cards If a user wants to make copies, he inserts his identification element 14 into the reader 16. Thereupon a yellow lamp 18, which is provided on the control panel of the monitoring connection 10, lights up thus informing the user that the monitoring port 10 is operational and that he must wait, bi> a green lamp 20 illuminates before attempting copies. After that, a Connection line between the monitoring connection 10 and the central unit 12, and the information of the Kcnnclcmcnts is read out and added

Central unit. At the same time, a port number is transmitted that corresponds to the relevant Monitoring connection 10 is assigned. The central unit 12 records the connection number, the department number, the user number, the date and the time on a punched tape. The Central unit 12 the validity of the information on the identification element and the authorization of the user to use the copier in question. If verification of the information reveals that the User is authorized, a signal is transmitted to the monitoring connection through which the assigned copier is released so that the user can now make his copies. this will indicated by the green lamp 20 lighting up. The connection between the monitoring port 10 and the central unit 12 is now interrupted. If the information is on an identification element, which entered into a reader is invalid or if the user does not rank the correct for the Use of the copier concerned, lights up on the control panel of the monitoring connection a red lamp 22 will come on to indicate that the copier will not be released. If the user makes its copies, two counts are made at the monitoring terminal. First of all, the The total number of copies made by the user is determined, and a special one is also determined Multiple copy counting performed as will be explained below. If the user finished copying, he briefly closes a switch 24 on the control panel, whereupon his identification element is ejected from the reader. The user can then take his identification element and walk. The green lamp 20 goes out and the copier is locked. Now there will be another Connection between the monitoring connection 10 and the central unit 12 established, and the monitoring connection transmits its connection number, the count of the total number of copies and that Counting result of the multiple copies to the central unit, where these numbers are on the punched tape to be recorded. Thereafter, the connection between the central unit 12 and the monitoring connection 10 interrupted again.

The basic operation of the monitoring system is described below in connection with the Table according to Fig. 4 explained in more detail. In the first column of this table are the request numbers specified, which are transmitted from the central unit to the monitoring connection. In the The second column shows the response numbers that are sent from the monitoring connection to the central unit are transmitted when there is an identification element in the reader. In the third column are the Response numbers specified, which are transmitted after the identification element has been removed from the reader. If there is an identifier in the reader, the monitoring port responds with a number 1. If there is no identification element in the reader, answer number 2 is used. The central unit then sequentially transmits the request numbers t to 15. The answers to the Inquiry numbers 1 and 2, whether an identification element is in the reader or not, are two numbers that Identify the monitoring connection in use. If there is an identifier in the reader then the answers to query numbers 3 to 12 are the ten digits on the identifier. the Inquiry numbers 13-15 do not elicit a response. Rather, the request number 14 is a signal to the Monitoring connection that its associated copier should be released while the request number 15 is a signal to the monitoring connection that the connection between the central unit and the monitoring port is terminated. If the identifier has been removed from the reader, then the answers to inquiry numbers 4 to 6 correspond to the total number of copies and the answers to the request numbers 8 to 10 correspond to the result of the count of the multiple copies. The inquiry numbers 3, 7 and 11-15 do not elicit an answer. Instead of this the request number 15 is again a signal to the monitoring connection that the connection between the central unit and the monitoring connection is terminated.

The structure of the monitoring connection 10 will now be described in greater detail below with reference to FIG. 1 explained. There is a two-wire line 23 is provided to the monitoring connection 10 with the Central unit 12 to connect. The data on line 23 are two-phase four-bit serial signals. The data are transmitted from line 23 via a compensation circuit 25 to a two-phase encoder-decoder 26 supplied. The compensation circuit 25 is used to the line 23 in more detail below illustrative way to connect to the encoder-decoder 26 at suitable times. Advance should be accepted that the line 23 is directly connected to the encoder-decoder 26. The coder-decoder 26 serves to convert the two-phase four-bit serial data on line 23 into four-bit parallel data at its Output convert and convert four-bit parallel data at its input into two-phase four-bit serial data to convert, which are given to the line 23. The serial transmission of two-phase data is possible also known as the so-called Manchester coding. This type of coding is in the document "Reference Data for Radio Engineers", 5th edition, pages 32 ff, published by International Telephone and Telegraph, New-York, USA. An example of a circuit which can be used as a coder-decoder 26 can be used is in "EDN Magazine", September 15, 1972, page 43 in the Article “Exclusive OR-Gates simplified modem designs” described by A I f k e.

The encoder-decoder 26 have four output lines which are connected to the inputs of a converter 28 which converts the signals on its four input lines into signals on sixteen output lines implements. A 0 output of the converter 28 is connected to a control input of a memory circuit 30. The outputs the memory circuit 30 are connected to a four-wire bus line 32, which in turn with the Input of the encoder-decoder 26 is connected. If the memory circuit 30 is indicated by a logical "1" its control input is set, it delivers, if there is an identifier in the reader 16, a binary-coded 1 on the bus 32. If there is no identification element in the reader 16, delivers the memory circuit 30, however, a binary-coded c 2. The reading device 16 has a switch 34 whose one terminal is connected to a positive voltage (+) through a resistor 36 and its other connection with the (^ output of a flip-flop 35 is connected, which is caused by positive voltage

Jumps is triggered. The switch 34 is closed when an identifier is entered into the reader 16 and opened when the identifier is removed therefrom. The connection point of the switch 34 to the resistor 36 is denoted by the reference symbol A , while the (^ output of the flip-flop 35 is denoted by the reference symbol B. The connection point A is connected to an input of the memory circuit 30 and controls in a suitable manner the output of the corresponding binary-coded number by the memory circuit 30 to the bus 32. The outputs 1 and 2 of the converter 28 are connected to the control inputs of a second and third memory circuit 38 and 40. The outputs of the memory circuits 38 and 40 are connected to connected to the bus 32 and supply it with four-digit binary numbers that correspond to the first and second digits of the connection number if a logical "1" is present at their control inputs.

The outputs 3 to 12 of the converter 28 are connected to the ten inputs of the reader 16. In Fig. 1, outputs 3 to 5 and 8 to 10 are denoted by Cl to Ci and M 1 to M 3 for reasons that will be explained in more detail below.

The reading device 16 has ten outputs which are connected to the inputs of a second converter 42 that converts the signals on its ten input lines into signals on four output lines. That Reading device 16 is designed in such a way that when a logical "1" is applied to its first input, the first column of the identification element is read, whereupon a logical "1" is sent to that output of the reader 16 appears which corresponds to the line in which the perforation occurs in the first column. The 2nd to 9th columns of the identification element are read in the same way if a logical "1" is sent to one of the inputs 2 to 10 of the reader 16 is applied. The second converter 42 sets the in the form of a decimal number to the Outputs of the reader 16 present information in a binary information at its outputs. the Outputs of the second converter 42 are connected to the bus 32 via a set of gates 44 tied together. The gate circuits 44 each have a control input, so that the output signals of the Converter 42 only get on the bus 32 if a logical one at the control inputs »1« is present. The output 13 of the first converter 28 is not used.

The output 14 of the first converter 28 is denoted by the reference symbol ^ and serves as a set (enable) output. This output is connected to the set input of a second flip-flop 46. The connection point A is connected to the reset input of this second flip-flop 46 via an inverter 47. The Q output of the second flip-flop 46 is connected to a circuit point C. The circuit point C is connected via a resistor 48 to the anode of a green light emitting diode, the cathode of which is connected to earth and which forms the green lamp 20. The circuit point C is also connected to a ω control input of a copier 50 assigned to the monitoring connection 10. The copier 50 is enabled by a logical "1" at this control input. The output 15 of the first converter 28 is designated with the reference symbol EC as an abbreviation for “Endc-der-Communication”. This input 15 is connected via an inverter 51 to the reset input of a third flip-flop 52, which is triggered by negative edges and whose set input is connected to circuit point A. (The set input of the various flip-flops is marked with "S" , while the reset input is marked with "R" ). The (^ output of the third flip-flop 52 is connected to a circuit point D , which in turn is connected via a resistor 54 to the anode of a yellow light emitting diode, the cathode of which is connected to earth and which forms the yellow lamp 18. Finally, is the output 15 or FC of the first converter 28 is also connected to the reset input of the first flip-flop 35, the set input of which is connected to the connection point A.

The connection point A is also connected to a first input of a NOR gate 56 with three inputs, the second input of which is connected to the circuit point C and the third input of which is connected to the circuit point D and whose output is connected via a resistor 58 to the anode of a red light emitting device Light-emitting diode is connected, the cathode of which is connected to earth and which serves as a red lamp 22. Each of the outputs of the reading device 16 is also connected to an input of an OR gate 62 via a respective switch of a switch arrangement 60. The output of the OR gate 62 is connected to a first input of a NAND gate 64 with two inputs, the second input of which is connected to the 8th output M 1 of the first converter 28. The output of the NAND gate 64 is connected to a circuit point E , which in turn is connected to a first input of an AND gate 66 with two inputs, the second input of which is connected to the circuit point D and the output of which is connected to the control input of the gate circuits 44. The circuit points Sund D are connected to the two inputs of an OR gate 68, the output of which is connected to a circuit point F, which in turn is connected to a first control input of the compensation circuit 25. The output 15 or EC of the first converter 28 is connected to a second control input of the compensation circuit 25. As will be explained in more detail below, a logic "1" at the first control input of the compensation circuit 25 results in the establishment of a connection between the monitoring connection 10 and the central unit 12, while a logic "1" at the second control input interrupts this connection.

The circuit according to FIG. 1 serves, as far as it has been described so far, to implement the sequence of steps which was explained above in connection with column 2 of the table according to FIG. Before an identification element is inserted into the reader 16 for the first time, the first flip-flop 35 is in the reset state, and a logic “0” is present at the circuit point B. If an identification element is inserted in the reader 16 and the switch 34 is closed, the third flip-flop 22 is set, and a logic "1" results at circuit point D , whereby the light-emitting diode of the yellow lamp 18 is switched on. If a "1" appears at circuit point D , there is also a "1" at the first control input of the compensation circuit 24, so that a connection with the central unit is established. If the request numbers 0 to 12 are received one after the other on the line 23, signals in the form of a logical "1" are successively sent to the outputs 0 to 12 of the first converter 28.

generated. The “1” signals at the outputs 0 to 2 of the first converter 28 cause the memory circuit 30, 38 and 40 to apply their corresponding response numbers to the bus 32. Since if a logic "1" is present at the circuit point D , there is also a logical "1" at the circuit point, a logic "1" is also applied to the control inputs of the gate circuits 44, so that the outputs of the second converter 42 with the bus 32, while the logical "1" signals at the converter outputs 3 to

13 have the consequence that the numbers on the identification element located in the reader appear one after the other the manifold 32 can be given. If the request number 14 is received, the output will be

14 or E of the first converter generates a logic "1", which sets the second flip-flop 46. If the second flip-flop 46 is set, a logic "1" results at node C, and the copier 50 is enabled while the green lamp 20 is switched on at the same time. The user can now make the desired number of copies. The arrival of the request number 15 causes a logical "1" to be generated at the output 15 of the first converter 28, which causes the third flip-flop 52 to be reset and the yellow lamp 18 to be extinguished. In addition, the logical "1" is applied to the second control input of the equalization circuit 25, whereby the connection with the central unit is interrupted. It should be pointed out that the red lamp 22 is not switched on unless the request number 15 is received before a request number 14 has arrived, since only in this case there is a logical "0" at the switching points A, C and D at the same time. J5

The copier 50 has an output at which a logical "1" is generated when each copy is made. This output of the copier 50 is connected to the counting input of a first counter with three counting decades 70, 72 and 74. Said output of the copier 50 is also connected to the inputs of a timer 76 and a second counter 78. The timer 78 is constructed in such a way that its output signal is a logic "0", except when a logic "0" has been applied to its input for a predetermined time. In this case, a logic “1” is generated at the output of the timer 76 at the end of the specified time interval. The second counter is designed so that it can count up to a maximum of 10. When this count is reached, it generates a logical "1" signal at its output and stops counting the pulses fed to its input. The output of the timer 76 is connected to a reset input of the second counter 78, via which this counter can be reset. The output of the second counter 78 is connected to the counting input of a third counter with three counting decades 80, 82 and 84. The outputs of the counting decades 70, 72, 74, 80, 82 and 84 are connected to the bus line via inverter gate circuits 90, 92, 94, 100, 102 and 104, respectively. Each of the inverter gate circuits 90, 92, 94, 100, 102 and 104 has a control input. The circuits mentioned are designed so that when a logical "1" is applied to their control input, the counter reading in the assigned counting decade is inverted and sent to the bus 32. Each counting decade 70, 72, 74, 80, 82 and 84 has a reset input via which it can be reset to zero by applying a logical "1". The reset inputs are connected to circuit point D.

The reader has an input which, when activated with a logical "1", causes the identification element in the reader to be ejected. This ejection input is connected to a circuit point G , which in turn is connected via a switch 27 to a source of positive potential and via a resistor 112 to earth. Those outputs of the counting decade 74 which correspond to the binary 1 or the binary 8 are individually connected to the two inputs of an AND gate 114, the output of which is connected to the circuit point C. The outputs 4 to 6 and 8 to 10 of the first converter 28 are connected to the control inputs of the inverter gate circuits 90, 92, 94, 100, 102 and 104, respectively.

It can be seen that the counting decades 70, 72 and 74 the total number of during a duty cycle of one Copies made by users on copier 50 are counted. The counting decades 80, 82 and 84 deliver a Counting result that corresponds to the number of multiple copies made from a single original is linked. In detail, the count in the third counter is increased by 1 each time from ten or more copies can be made from a single original. The timer 76 is set so that the second counter 78 is reset after a predetermined time interval, which on the The point in time at which the last copy was made follows. The length of the time interval is considerable longer than the time between copier duty cycles when making multiple copies of one; single original, but considerably shorter than the time it takes to change the original in the Copier is required.

When the user of copier 50 finishes making copies, he closes briefly the switch 24, whereupon its identification element is ejected. This turns the switch 34 open that; second flip-flop 46 reset and the green lamp 20 extinguished. Also, the first will Flip-flop 35 is set and a logic "1" is sent to the first control input of the via the OR gate 68 Compensation circuit 25 placed so that a connection with the central unit is established. If then the Inquiry numbers 0 through 2 are received, the memory circuits 30, 38 and 34 set their respective ones binary-coded numbers to the bus 32. In addition, if the request numbers 4 to 6 and 8 to 10 are received, the counts of the counting decades 70, 72, 74, 80, 82 and 84 via the assigned inverter gate circuits successively applied to the bus 32. If then the Request number 15 is received, the first flip-flop 35 is reset and a "!" Pulse is generated applied to the second control input of the compensation circuit 25, whereby the connection to the central unit is interrupted. If an identification element is then inserted into the reader 16 again, will the flip-flop 52 is reset again and the logical "1" signal that then occurs on his The output causes the counter decades 70, 72, 74, 80, 82 and 84 to be reset to zero. Be on it should be noted that when the count decades are reset in this way, the inverter gate circuits 90, 92, 94, 100, 102 and 104 apply logical "!" Signals to bus 32 via all of their outputs, when an identification element is inserted into the reader 16

will. If the numbers of the identification element are then read out and appear on the bus line 32, the gate circuits 44 can still open the corresponding cores of the bus line 32. ^r draw a logical "0". The count of the counting decades 70, 7?, 74, 80, 82 and 84 is inverted before it is sent to the bus 32. If the case occurs that an identifier is inserted into the reader 16 before the count from all counting decades 70, 72, 74, 80, 82 and 84 has been transmitted to the central unit, ie before the request number 15 arrives, the first flip remains -Flop 35 in the set state, and the logic "1" at its output prevents the node A from assuming the potential "0", which prevents the third flip-flop 52 from being set and the count in the counting decades from being lost, namely up to the point in time at which the entire information has been transmitted to the central unit.

The AND gate 114 prevents the counting decades 70, 72 and 74 from overflowing. Without this AND gate the first counter would return to zero if more than 999 copies were made, and the central unit could not detect the previously completed copies. At the output of the AND gate 114, however, the logical "1" appears when the nine hundredth copy is made, which causes is that the identification element is ejected from the reader 16. The signals at the monitoring connection 10 The collected data are now transmitted to the central unit, whereupon the user uses his identification element insert it again and make more copies. It goes without saying that instead of counting and Recording of only six decimal digits at the monitoring port 10 as shown in FIG. 1 without further ado an extension could be made to include four more decimal numbers.

The elements 60 to 66 serve to generate the rank information which was mentioned above. That The output signal of the NAND gate 64 is normally a logical "1", through which the gate circuits 44 can be set as described above. However, when the output of OR gate 62 is a logical "1" is when the 6th column of the identifier 14 is read by the reader 16 at the same time, then there is a logical "0" at the output of the NAND gate 64, so that the gate circuits 44 prevent the rank number or the rank bit from being transmitted to the central unit. The switches of the Switch arrangement 60 can be set so that a transmission is only carried out with certain rank numbers to the central unit. If it is desired that the actuation of the monitoring port 10 associated copier is prevented at any particular rank number, it is only required to close that switch of the switch arrangement 60, which the corresponding output of the reader 16 connects to the OR gate 62. As mentioned, the security numbers of the Identification element 14 generated by mathematical permutations of the remaining numbers of the identification element Be check digits. If this is the case and if the transmission of the rank number is suppressed, then the circuit of the central unit in which the permutations are carried out does not receive a corresponding one Digit so that the permutation leads to an incorrect result. The central unit reacts to this as the identifier would have contained invalid data so that the copier in question would not be released will. The monitoring connection 10 can thus be programmed so that it is the associated copier 50 does not release if the identification element of the user has certain rank numbers. the Programming takes place here simply by closing the relevant switches of the switch arrangement 60.

F i g. FIG. 2 shows a preferred embodiment of a central unit for a monitoring system according to FIG Invention. The central unit 12 contains a strip punch 140 with associated switching devices. Of the Strip punch 140 has inputs that are connected to a manifold 142, as well as one Control input. If a positive voltage jump is applied to its control input, then takes over the strip punch 140 the information from the bus 142. encodes this information in suitable for the punching operation and then performs the recording of the information. The strip punch 140 has an output to which a logical "1" is normally present, but which is a logical one "0" appears when the strip punch 140 has a positive voltage jump at its control input is set. The output remains at the logical "1" long enough until the information is received from the Bus 142 is recorded.

The central unit 12 also has a two-phase coder-decoder 150, which is connected to the line 23 and which is constructed similarly to the coder-decoder 26 in the monitoring connection 10. The coder-decoder 150 serves on the one hand to control the two- To convert phase four-bit series data from line 23 into four-bit parallel data and to convert the four-bit parallel data at its input into two-phase four-bit series data on line 23 . The coder-decoder 150 also has a first and a second control input EN and ST! For the coder-decoder 150 to work, a logical "0" must first be applied to the first control input EN in order to set the coder-decoder 150, and a positive voltage jump must also occur at the second control input ST so that the coder- Decoder 150 starts to work. By switching off the logical "1" at the first control input EN , the coder-decoder 150 is then switched off again. The line 23 is also connected to the input of a threshold value detector 152, which operates with a relatively high voltage. The threshold value detector 152 has an output at which a logical "1" appears only when the voltage on the line 23 is below a predetermined, relatively high voltage level. The output voltage of the threshold value detector 152 is connected to a first input of an AND gate 154 with two inputs and also to the input of a monostable multivibrator 156. An output Q of the multivibrator 156 is connected to the second input of the AND gate 154. Multivibrator 156 is designed in such a way that the signal at its output Q is normally a logic "0", but assumes the value "1" for a predetermined period of time if a logic "1" is applied to its input. The output of the AND gate 154 is connected to an input of an OR gate 158, the output of which is connected to the set input of a flip-flop 160.

The (^ output of flip-flop 160 is with the first Input of an AND gate 162 connected to two inputs. The output of this AND gate 162 is with the first input of a NAND gate 163 with

two inputs connected, the output of which is connected to the first control input EN of the encoder-decoder 150. The second input of the AND gate 162 is connected to the output of the strip punch 140. The output of the AND gate 162 is also connected to the control inputs of a two-phase clock oscillator 164 and a four-bit binary counter 160. The oscillator has two outputs Oa and Ob. If a logic "1" is present at a control input, it delivers a series of logic "1" pulses at its output Oa and a corresponding series of pulses at its output Ob. The pulses at output Ob are slightly delayed compared to those at output Oa. The output Oa of the oscillator 164 is connected to the control input of the strip punch 140. A counter 166 is designed so that when a logic "1" is applied to its control input, it counts the pulses applied to its counter input CL , a counting step being triggered by a negative voltage jump. The output Ob of the oscillator 164 is connected to the counting input CL of the counter 166, so that the counter 166 is incremented by the trailing edges of the "1" pulses from the output Ob of the oscillator 164. The outputs of the counter 166 are connected on the one hand to the inputs of a converter 168 with four inputs and 16 outputs and on the other hand to the input of the encoder-decoder 150 via a set of gate circuits 170. The gate circuits 170 have a control input and are designed in such a way that they let the count of the counter 166 through to the input of the encoder-decoder 150 when there is a logical "1" at the control input.

The devices of the central unit described up to now serve to generate the request numbers 0 to 13 and 15 and to put them on the line 23. For the central processing unit 12 to work, the flip-flop 160 must be set. If this flip-flop is set and if a logical "1" is present at the output of the strip punch 140, the coder-decoder 150, the oscillator 164 and the counter 166 are set. The oscillator 165 then generates a "!" Signal at its output Oa, which causes the strip punch 140 to record the data on the bus 142 at this point in time, whereupon the logic "0" appears at the output of the strip punch 140 and the oscillator 164 is switched off. Immediately after the "1" pulse occurs at output Oa , a similar pulse is generated at output Ob ;!. The leading edge of this pulse initiates the operation of the encoder-decoder 150. The counter reading of the counter 166 is increased by one by the trailing edge of this pulse. At the output of the strip punch 140, the logical “0” is retained for a predetermined period of time. During this period, three things happen. First of all, the data previously present on the bus line 42 are recorded through the strip punch 140. Second, the data at the input of the coder-decoder 150 are converted into serial data and transmitted as a request number over the line 23. Thirdly, the response number received via line 23 is output at the output of coder-decoder 150 after conversion. When the tape punch has completed its recording process, its output goes to the state "1", the oscillator 164 is set again and the processes are repeated. It should be noted that the period of time which the strip punch 140 needs to record the information at its input is longer than the period which the encoder-decoder 150 needs to send a request number to the monitoring connection 10 and to send the corresponding response number receive. It should also be pointed out that in the time intervals between successive "1" pulses at output Oa, the central unit records data which are already present on data bus 142, but at the same time requests and receives further data from monitoring connection 10.

The devices with the aid of which the data reach the bus line 142 will now be described below. In detail, the output signals of the encoder-decoder 150 are applied to the inputs of a blocking circuit 172, a set of gate circuits 174 and a security circuit 176. The blocking circuit 172 has a control input. If a logical "1" is present at the control input, the blocking circuit 172 lets the data present at its inputs through to its outputs. However, if there is a logical "0" at the control input, the outputs of the blocking circuit 172 remain in the state in which they were when the signal at the control input changed to "0" the last time. The converter 168 has 16 outputs 0 to 15, of which output 1 is connected to the control input of the blocking circuit 172. The 16 outputs of the converter 168 and the outputs of the blocking circuit 172 are connected to the inputs of a read-only memory 178. Read only memory 178 has seven outputs labeled SEC, SECCL, TC, DA, IN 1, IN2, and FM . These symbols mean abbreviations for "Security", "Security-clear", "Time code", "Data", "Connection number 1 (installation digit 1)", »Connection number 2 (installation digit 2)« or »Karteimarke (file mark)«. In the 4th column of the table according to FIG. 4 indicates the 16 possible states of the counter 166, while the 5th to 7th columns indicate which outputs of the read-only memory 178 deliver a logical "1" when the counter is in the relevant state, depending on this whether the output of the interlock circuit 172 is a binary 0, a 1, or a 2.

The outputs of the gate circuits 174 are connected to the bus line 142 and are designed in such a way that the signals from the output of the coder-decoder 150 are applied to the bus line 142 when a logic "1" is applied to their control input. The control input of the gate circuits 174 is connected to the output DA of the read-only memory 178. There are three further memories 180, 182 and 184, each of which has a control input and is designed in such a way that it applies a digit in binary form to the bus line 142 when a logic "1" is applied to its control input. The digit stored in the memory 180 is a card mark which is recorded by the tape punch along with the data. The control input of the memory 180 is connected to the output FM of the read-only memory 178. The digits stored in memories 182 and 184 constitute a number which is the port number for a particular monitoring port associated with the monitoring port associated with the monitoring system. A single system can have more than one central processing unit, so that the same port number has more than one

ι:

Central unit can be assigned. The control inputs of memories 182 and 184 are connected to outputs INi and / A / 2 of read-only memory 178. An electronic clock 186 with a calendar is provided which can generate a 7-digit binary-coded decimal number representing the date and time. The clock has a control input and generates an output signal for a selected digit of the seven digits at one of its outputs when a logical "1" is applied to its control input will. In detail, the address inputs are connected to the outputs 8 to 15 of the converter 168. The control input of the clock 186 is connected to the output TC of the read only memory 178 and its outputs are connected to the bus 142.

The safety circuit 176 contains suitable devices for carrying out a safety check of the data supplied to it. As mentioned above, the identification element 14 has four digits leading to Data backup can be used. The safety circuit 168 has a control input and is can be set by a logical "1" at this control input. The safety circuit works with the Security digits and other digits of the identification element that are required for the security check. The safety circuit 176 can also be connected to the outputs of the clock 164 and the converter 168 be connected so that the correct clock signals can be fed to it. The safety circuit 176 can be structured differently depending on the particular applied Backup procedure. As mentioned above, the ranking number can also be included in the security check when permutations of all data of the identification element are performed. In particular, can proceed in such a way that in the event that the central processing unit does not receive the priority number, Due to the permutations, no result is obtained which satisfies the security check, so that the Central unit just reacts as if the identification element were invalid. In the circuit according to FIG. 2 the safety circuit works with all ten digits or numbers of the identification element 14.

The control input of the safety circuit 176 is connected to the SEC output of the read-only memory 178. An output of the safety circuit 176 normally supplies the logical "0", but changes to "1" if an invalid identifier is detected. The output of the safety circuit 176 is coupled to the set input of a flip-flop 188. The reset input of this flip-flop is connected to the SECCL output of the read-only memory 178. The (^ output of the flip-flop 188 is connected to a first input of a NAND gate 190, to whose second input the output 14 of the converter 168 is connected. The output of the NAND gate 190 is connected to the control input of the gate circuits 170 .

The following is the mode of operation of the central unit according to FIG. 2 will be explained. In the Column of the table according to FIG. 4 is the status of the counter 166 when the data in the 1st column is transmitted specified request number to the monitoring connection 10 and when receiving the corresponding There is data from the monitoring port. It can be seen that when transmitting the request number

0 and for the digit 1 or 2 received thereupon, depending on whether or not there is an identification element in the reader, the counter 166 has the counter reading 1. In the 9th and 10th columns of the table according to FIG. 4, the information is given which is recorded by the strip punch 140 during the individual counter settings of the counter 166. The 9th column indicates the information that is recorded when the signals at the outputs of the interlock circuit 172 represent a 1, while the 10th column shows the information that is recorded when the signals at the outputs of the interlock circuit 172 represent the number 2 represent. Before starting a connection to any monitoring connection 10, the counter 166 is at the count 0 and the memory is set and provides on the bus 142 a binary number which corresponds to a card token. At the beginning of a connection, the flip-flop 160 is set, and the oscillator 164 is set, provided that a logic "1" is present at the output of the strip punch 140. A "1" pulse is then generated at the output of the oscillator 164, with the result that the strip punch 140 records a card mark. Immediately thereafter, a "1" pulse is generated at the output O _{B of the oscillator 164.} The leading edge of this pulse causes the count 0 at the output of the counter 164 to be transmitted to the monitoring connection 10; the trailing edge of the pulse causes the counter 164 to increment to count 1. During the time that the tape punch 140 is working to record the card mark, its output has a logic "0" and the oscillator 164 is thus blocked. While the counter 164 has the counter reading 1, the strip punch 140 ends the recording of the card mark, and the response to the query number 0 is received, this response being either a 1 or a 2, depending on whether there is of the monitoring connection is an identification element or not. While the counter 164 has the counter reading 1, the output DA of the read-only memory 178 has a "1", the gate circuits 174 are set and the answer to the request number 0 is given to the bus 142 via the gate circuits 174. In addition, when the counter 164 has the counter reading 1, there is a logical "1" at output 1 of converter 168, so that the response to query number 0 appears at the output of blocking circuit 172.

When the strip punch 140 has finished recording the card mark, a logical "1" appears at its output, the oscillator 164 is set again and "!" Pulses appear one after the other at its outputs Oa and Ob. The ΟΛ pulses cause the punch 140 to begin recording the information on the bus 142, ie, recording the response to query number 0, while the leading edge of the Os pulse causes the count 1 of counter 166 to go to the monitor port 10 is transmitted. The trailing edge of the Os pulse causes the counter 166 to advance to the count 2. While the counter 164 has the count 2, the strip picker 140 ends the recording of the response to the request number 0, and the response to the request number 1 is received, namely the first digit of the connection number. While the counter 164 has the count 2, the output remains the

Blocking circuit 172 in the state which is predetermined by the response to the request number 0. In addition, there is a logical "1" at the output DA of the read memory 168, the gates 174 are set, and the response to query number 1 is forwarded to the bus 142 via these gates.

When the tape punch 140 has finished recording the response to the request number 0, the process is repeated, and the tape punch 140 records the response to the request number 1, while the request number 2 is sent to the monitoring terminal 10 and received the response from there is applied to the manifold 142. If the outputs of the blocking circuit 172 correspond to a binary 1, this process is repeated for the counts 3 to 8 of the counter 166. While the counter 166 has the counts 4 to 8, the responses to the request numbers 3 to 7 , ie the department number, are received and the user number indicated on the identification element in the reader. While the counter 166 has one of the counts 5 to 9, the responses to the query numbers 3 to 7 are recorded by the strip punch 140. While the counter 166 has one of the counter readings 9 to 14, the digits are received which form the ranking number or the security number. Usually there is no need for the strip punch to do this; Records numbers. Instead, the clock 186 provides a time code which contains the date and time. The output ¹ TC of the read-only memory 178 supplies a logical "1" during the counts 9 to 15 of the counter 166, and the seven digits from the output of the clock 186 are consequently recorded while the counter 166 has the counts 10 to 15 and 0.

If one also assumes that the output signal of the blocking circuit 172 is a binary 1, then at the output SEC of the read-only memory 178 for the counter readings 4 to 13 of the counter 166 there is a logical "1". The digits which are received by the monitoring connection 10 while the counter 166 has one of the counter readings 4 to 13, that is to say all digits which are read from the identification element, are thus fed to the safety circuit 176. If a logical "1" appears at the output of the safety circuit 176 and indicates that an invalid identifier has been used, then the central unit must not transmit the request number 14 to the monitoring connection 10. Elements 188 and 190 are provided for this purpose. Normally there is a logic "0" at the Q output of the flip-flop 188 that forms one element. A logic “1” is thus generated at the output of the NAND gate 190, which forms the second element, and is applied to the control inputs of the gate circuits 170, so that the output signal of the counter 166 is applied to the input of the encoder-decoder 150. If, however, data is received that indicates the use of an invalid identifier, then a logic "1" appears at the output of the safety circuit 176, which sets the flip-flop 188 and now at its output C? returns a logical "1". If in this situation a logical "1" occurs at the output 14 of the counter 166, a logical "0" results at the output of the NAND gate 190 and the gate circuits 170 are blocked, whereby the connection between the output of the counter 166 and the input of the coder-decoder 150 is interrupted and the transmission of the request number 14 is prevented. If the flip-flop 188 has been set, it will be necessary to reset it when the time information read from another identifier is received. This is achieved by providing the output SECCL of the read-only memory 17d, at which a logical "1" is present when the counter 166 has the counter reading 9 and by feeding the output signal from said output to the reset input of the flip-flop 188.

To interrupt the operation of the central unit after receiving all information from the identification element and after completion of the recording of the time code, the output 0 of the converter 168 is with the Reset input of flip-flop 160 connected. If the counter 166 has run through all counter readings 1 until 15 returns to 0, the request number 15 becomes the monitoring connection 10 sent out, thereby setting the memory 180 to enable the recording of a card mark, as soon as the next connection to a monitoring port is made. In summary one can plso determine that when an identification element is inserted into the reader, the Strip punch 140 records a card mark followed by the digit 1 and the five digits that the user and identify the seven digits that represent the date and time.

If the output of interlock circuit 172 is a binary 2, then the central processing unit is operating similar to that described in the three immediately preceding paragraphs with the exception, that the time code is not recorded and the security circuit 176 is not set. Instead, will the total number of copies made and the number of multiple copies from the monitoring port transmitted and recorded. In this case, the tape punch 140 records a card mark containing the Number 2 follows. Three digits are available for the total number of copies and three digits are for the Number of multiple copies available.

The central processing unit 12 also includes means for recording a two-digit port number and the date and time at the beginning of each duty cycle. These facilities include a Flip-flop 192, its set input with the output of a supply voltage detector 194 and its reset input is connected via a switch 196 to a positive voltage source. The supply voltage detector is connected to the circuit for supplying the supply voltage for the central unit and its output signal is a logical "0" if the output voltage of the supply voltage source falls below the voltage required to operate the central unit. Otherwise, the output of the Supply voltage detector 194 a logic "1". The switch 196 is located on the control panel of the Central unit and must be closed briefly every time the central unit is in operation is set, d. H. either when the supply voltage for the central unit is switched on or when a new supply of paper has been inserted into the strip punch 140. The (^ output of flip-flop 192 is connected to the reset inputs of flip-flops 160 and 188 and ensures that these two flip-flops must first be reset when the central unit is switched on. In addition, the (^ output

of the flip-flop 192 is connected to the clear input of the counter 166 and sets it to zero when the supply voltage is switched on. The output Q of the flip-flop 192 is connected to the input of a monostable multivibrator 198. The output Q of the monostable multivibrator 198 is connected to the second input of the OR circuit 158 and is normally at "0", except during a predetermined period of time after a logic "1" has been applied to its input. The output Q of the monostable multivibrator 198 is fed to a circuit point C, which in turn is connected to the second input of the NAND gate 163. Each time switch 196 is closed, the monostable multivibrator applies a logic "1" to the set input of flip-flop 160 via gate 158 applied so that a logic "1" is applied to the second control input EN of the coder-decoder 150, which blocks this circuit. The central processing unit begins to operate when the flip-flop 160 is set. However, since the encoder-decoder 150 is locked, no query numbers are sent to the monitoring ports and no responses are received from them. As a result, the output of interlock circuit 172 is held at state zero. The states of the outputs of the read-only memory 178 and the numbers recorded by the strip punch 40 are shown for this situation in the 5th and 8th columns of the table according to FIG.

While the counter 166 is counting 1 and 2, a card token and the number 0 are recorded. If the counter 166 has the counter readings 2 and 3, then there is a logical "1" at the outputs IN 1 and IN2 of the read-only memory 178. This sets memories 182 and 184 so that the signals corresponding to the first and second digits of the port number are placed on bus 142. When the counter 166 becomes 3 and 4, the first and second digits of the port number are recorded. When the counter 166 shows 10-15 and 0, the seven digits of the time code are recorded. The period of the monostable multivibrator 198 should be slightly longer than the time required for the strip punch 140 to record the card mark. Each time the operation of the central unit 12 is initiated by closing the 1% switch, the strip punch records a card mark as well as the number 0 and a two-digit connection number assigned to the central unit in question and also the seven digits of the time code, which contain the date and time display the time. As mentioned above, the monitoring connection 10 contains a compensation circuit 25. The purpose of this circuit is to provide the possibility of using a central unit to monitor and record the use of several copiers, each of which is assigned a monitoring connection 10. In particular, the compensation circuit 25 ensures that a single two-wire line 23 can be used to connect all the monitoring connections to the central unit, the individual monitoring connections being connected to the line in parallel. The compensation circuit ensures that there is only a connection between one monitoring connection and the central unit.

The compensation circuit or connection device is described below with reference to FIGS. 5 explained in more detail. Each monitoring connection 10, which is connected to the central unit 12, has such a compensation circuit 25, which is connected to line 23 via suitable connecting devices 398, 398/4.

A first compensation circuit 25, which is connected to a first monitoring terminal 10, is shown in FIG. 5, while a second compensation circuit 25A associated with a second monitoring port 10/4 is partially shown. In fact, equalization circuits 25 and 25/4 can be identical. One wire of the line 23 is connected to earth or to the reference potential of the circuit, while the other wire is connected to an input of a threshold value detector 400 for a relatively high voltage and to an input of a threshold value detector 402 for a relatively low voltage. The output signal of the threshold value detector 400 is a logical "1" when the voltage on the line 23 has a first voltage level! and otherwise a logic "0", while the output signal of the threshold value detector 402 is a logic "1" if the voltage on the line 23 exceeds a second voltage level and otherwise a logic "0", the first voltage level being higher than that second is. The output signal of the threshold value detector 400 is fed to a first input of an AND gate 404 with two inputs. A / - / (- flip-flop 406 has its / input connected to the output of AND gate 404, while its / (- input is connected to ground. The clock input of flip-flop 40 ^ 5 is connected to the output an oscillator 408. The (^ output of the flip-flop 406 is connected to a load switch 410, one terminal of which is connected to the ungrounded side of the line 23 via a resistor 412. The load switch 410 serves to connect the ungrounded wire on line 23 through resistor 412 to ground when its input has a logic "1." The Q output of flip-flop 406 is also connected to the input of a timer 414. An output of timer 414 is normally present "1", but goes to "0" if the signal at its input was a logical "1" for a specified time interval. The output of the timer 414 is connected to the first input of an AND gate 416 with two inputs, its output with a first entrance of an OR gate 418 is connected to two inputs. The output of the threshold value detector 402 is connected to the second input of the AND gate 416 via an inverter 420. The second input of the OR gate 418 is connected to the output 15 or EC of the first converter 28 of the monitoring connection IC. The second input of the AND gate 404 is connected to the circuit point F of the monitoring connection 10. As mentioned, the compensation circuit 25A is constructed similarly to the compensation circuit 25 and contains in particular a load switch 410/4 and a resistor 412/4, these elements being connected in the same way as the corresponding elements of the compensation circuit 25. Derr oscillator 408 of the compensation circuit 25 correspond to the oscillator of the compensation circuit 25A, but work with a slightly different frequency than the oscillator 408. The central unit 12 contains a current source 430 which is connected between the wires of the line 2. '

lies. This power source and elements 152,154 and 156 of the central unit cooperate with the compensation circuit 25 to achieve the desired function bring about.

The data transmitted over line 23 consists of zero volt pulses. The compensation circuit 25 also includes a data switch 422 which is located between the ungrounded wire of line 23 and ground. If a logical "1" is applied to the input of data switch 422, this switch 1 closes and causes a zero volt signal to appear on line 23. The input of the data switch 422 is with the output of a NOR gate 424 connected to two inputs, the first input of which is connected to the Connection point of the circuit breaker 410 and the resistor 412 is connected. The ones to be transferred Data is applied from the coder-decoder 26 to the second input of the NOR gate 424, while the received data is from the output of the threshold detector 402 for the low voltage can be applied to the coder-decoder 26.

In short, the compensation circuit 25 operates as follows: The power source 430 of the central processing unit 12 supplies a relatively constant current between the wires of the line 23, so that the voltage between these two Cores at least when no data is being transmitted, a function of what lies between them Resistance is. When the connection between any monitoring port 10 and the Central unit 12 is produced, then the j « Load switch 410 of this monitoring connection is closed and the resistor 412 is connected between the Cores of line 23 laid. If the load switches 410 of all monitoring connections 10 that have a Central processing unit are connected, then j5 the voltage across line 23 is a relatively high one Voltage, which is primarily caused by the internal resistance of the generator or of the current source 430 is determined. If the load switch 410 of one of the monitoring connections 10 is closed, then leads the presence of the resistor 412 between the wires of the line 23 leads to a voltage drop, which is too leads to a drop in voltage below a first voltage level. The threshold detector 400 determines whether the voltage across line 23 is above or below the first voltage level. if ever two load switches 410 in two or more monitoring connections 10 are closed at the same time are, then two or more resistors 412 are placed between the wires of the line 23, resulting in As a result, the voltage falls below a second voltage level which is lower than the first Voltage level, drops. Accordingly, the second threshold value detector 402 determines whether the voltage across the line is above or below the second voltage. If at the output of the threshold value detector 400 a logical "1" is present, then between the monitoring connection 10 and the central unit 12 a connection can be established and the load switch 410 is closed. If at the exit of the threshold value detector 400, on the other hand, a logic “0” is present, then a connection already exists between another monitoring connection and the central unit, so that the connection between the new monitoring connection and the central unit can only be established if the previous one Connection is interrupted. If the case should occur that the load switches 410 and 410/4 both Monitoring connections 10 and 10/4 are closed, then the voltage across line 23 falls below the second voltage level. The threshold value detector 402 determines this and interrupts the connection between both monitoring connections and the central unit. A pseudo-random system with oscillator 408 is then effective in the monitoring connections to a connection of one of the monitoring connections with the central unit.

Specifically, when an identification element 14 is inserted into the reader 16, the switch 34 is closed, the flip-flop 52 is set and a logical "1" is generated at the node Feine. When the output of the Threshold detector 400 is a "1", then the flip-flop 406 is set by the next time pulse, which is from Oscillator 408 is applied to its clock input. In addition, the load switch 410 is closed. A logical “0” is now applied to the first input of the NOR gate 424, and the data switch 422 is opened or closed, depending on the signal at the second input of the NOR gate 424, thereby establishing a connection between the monitoring connection 10 and the central processing unit 12 is produced. If, on the other hand, a logical “0” is present at the output of the threshold value detector 400 is, then such a connection is only established when this output signal changes to "1", i.e., if there is a previously existing connection between another monitoring connection and the central unit was interrupted. In a corresponding manner, if the identification element is from the reader 16 is removed, the switch 34 is opened, the flip-flop 35 is set and at node F a logical "1" is generated. If the output signal of the threshold value detector 400 at this point in time is logical "1", then flip-flop 406 is set, and the load switch 410 is closed in order to establish a connection between the monitoring connection 10 and the central processing unit 12. If, on the other hand, the output signal of the threshold value detector 400 is is a logical "0", then no connection is made until this output signal becomes a logical "1". If the request number 15 is received from the monitoring connection 10, which is the end of the Connection indicates, then from the output 15 of the converter 28 to the reset input of the flip-flop 406 a logic "1" is applied, which causes the load switch 410 to open and the connection between the monitoring connection and the central processing unit.

Various exemplary pulse diagrams are shown in FIG. The pulse train A represents the output signal of the oscillator 408, the pulse train B represents the output signal at the node F when it is desired to establish a connection between the monitoring connection 10 and the central processing unit 12; the pulse train C represents the output signal of the flip-flop 406. The pulse trains D, E and F correspond to the pulse trains A ₁ ß and C, but apply to the compensation circuit 25A F in the compensation circuit 25 becomes a logical "I" earlier than the signal at the corresponding circuit point F of the second compensation circuit 24/4, so that it can be seen that the monitoring connection 10 is making an attempt earlier

attempted to establish a connection with the central unit than the other monitoring connection 10/4. The output signal of the flip-flop 406/4 thus remains a logical "0" until the Connection between the monitoring connection 10 and the central unit is ended.

The pulse diagrams G to K according to FIG. 6 show the mode of operation of the compensation circuit when both monitoring connections 10 and 10A try to establish a connection with the central unit 12 at the same time, the pulse sequences C and J being the output signal of the oscillator 408 and the signal at node F. the compensation circuit 25, as well as the output signal of the corresponding oscillator 408, 4 and the signal at the corresponding r> node F in the other compensation circuit 25/4 and the pulse train K representing the corresponding voltage on the line 23. The situation under consideration arises when the oscillators 408 and 408/4 of the monitoring connections 10 and 10A happen to work approximately in phase and when the circuit points F in both monitoring connections 10 and 10A in the time interval between the corresponding output pulses of the oscillators 408 and 408/4 assume the state "1", the time at which the two pulses occur is denoted by fi and t _{2 in FIG.} If the case under consideration occurs, the load switches 410 and 410.4 in the two equalization circuits 25 and 25Λ are closed simultaneously at approximately time t2 , and the voltage across jo of line 23 then falls below the second , as the pulse sequence K shows Voltage level V2 . If the voltage on the line 23 falls below the level V2, a logic "1" J5 is present at the output of the timer 414 via the AND gate 416 and a logic "1" via the OR gate 418 to the The reset input of the flip-flop 406 is applied and the load switch 410 is thus opened. Load switch 410/4 is also opened in a corresponding manner. As mentioned, the oscillators in the 4C equalization circuits 25 and 25/4 operate at different frequencies. Like F i g. 6 shows, the frequency of the oscillator of the compensation circuit 25 is slightly lower than the frequency of the oscillator of the further compensation circuit 25/4. The next time an output pulse from oscillator 408 occurs - this pulse occurs at time fa - the pulses from oscillators 408 and 408/4 are a little out of phase, and the logical "!" Pulse from oscillator 408 begins slightly earlier than the "1" -Pulse of the ^r > n oscillator 408A. However, the arrangement of the load switch 410/4, the threshold detector 400 and the AND gate 404 has a response time that must elapse after the closing of the load switch 410A, to close the circuit breaker to prevent 410 i ^r>. If the leading edges of the "!" Pulses of oscillators 408 and 4084 are not shifted by at least this response time, then load switch 410 also closes again, although load switch 4I0A was previously closed, which again results in the voltage falls below the voltage level V2 via line 23, so that both switches 410 and 410/4 are opened again. As FIG. 6 shows, the time interval between the pulses of the *> ^r > oscillator 408 starting at the times I ₃ , U, / 5 and / ₆ from the leading edges of the output pulses of the oscillator 408/4 is shorter than the required response time. The output pulse of oscillator 408 beginning at time / 7 is, however, shifted sufficiently in time compared to the corresponding output pulse of oscillator 408, 4, so that closing of load switch 410 is now prevented. In this case, the voltage across the line 23 remains above the voltage level V2, so that the load switch 410A remains closed and enables a connection to be established between the further monitoring connection 10A and the central unit 12.

The drop in the voltage across the line 23 below the first voltage level is later detected by the threshold value detector 152 for the higher voltage in the central unit 12, whereupon the flip-flop 160 initiates the operation of the central unit in the manner previously described. The monostable multivibrator 156 provides a delay between the drop in the voltage across line 23 below the first voltage level and the start of operation of the central unit. This ensures that neither low-voltage noise pulses from line 23 nor low-voltage pulses according to the pulse sequence K in FIG. 6 trigger the operation of the central unit due to the operation of the equalization circuits 25, 25A.

The timer 414 of the equalization circuit 25 is designed so that data pulses from the monitoring circuit 10 do not reset the flip-flop 406 and do not open the load switch 410. The output signal of the timer 414 thus goes after the output of the flip-flop 406 for a predetermined Time interval was a logical "1", after "0", so that the output signal of the threshold value detector 402 via the Gate 416 can no longer be applied to the reset input of flip-flop 406. The threshold detector 402 for the lower voltage is then used to transmit the data pulses on line 23 ascertain.

The output Q of the flip-flop 406 is connected to a first input of an AND gate 426 with two inputs, while the output of the timer 414 is connected to the second input of the AND gate 426 via an inverter 428. The output signal of the AND gate 426 can then be used to indicate to the remaining circuit parts of the monitoring connection 10 that this monitoring connection 10 is connected to the line 23 and should now receive and transmit data, for example by enabling the coder-decoder 26.

In a monitoring system according to the invention, the oscillators 408, 408A of FIG Equalizer circuits with frequencies of about 10 Hz, and their output pulses were about 0.5 msec. The timers 414 operated with a delay time of about 6 msec, and the one-shot Multivibrator 156 provided output pulses with a duration of approximately 40 msec. It is of course desirable ensure that the operating frequencies of the oscillators 408 for all with a central unit 12 cooperating monitoring connections are slightly shifted from one another.

From the above description it is clear that a switching device was created which all requirements made at the beginning are met. In particular, the invention enables connection device the use of a single data line by several remote ones from a central processing unit Unteranschlüssc and ensures that the data line

is only used by one sub-connection at a time. The connection device preferably has interruption devices, which prevent a connection from being established if the two sub-connections are essentially simultaneously the An attempt is made to intrude on the data line. In addition, facilities are foreseen which ensure that a sub-connection that is ready for connection is immediately available on the data line is activated when its use is terminated by a 1 »other sub-connection. The interruption devices make sure that when the data line comes from two or more sub-ports is required, there is essentially the same probability for each of the sub-connections as first to be connected to the data line. This differs from the one according to the invention System of the data transmission systems, in which all sub-connections in a given order with connected to the data line. In these systems, the sub-connectors that appear at the end of the Are in order of precedence, always wait a long time until they are connected to the data line so that this Sub-ports, when the system is very busy, become practically useless. The description above also makes it clear that when using the switching device according to the invention at any time more Sub-connections can be connected to the data line. The expansion of the system makes no changes to the already existing switching devices and sub-connections are required. Indeed, it is in many applications of data transmission systems according to the invention no need to take special precautions with the oscillators for each sub-connector to ensure different frequencies, since the normal tolerances of the components differ in environmental conditions etc. ensure that there are sufficient frequency deviations result.

A preferred embodiment of the invention has been discussed in detail above; it understands however, that the invention is in no way limited to the details of the exemplary embodiment. Rather, both with regard to the basic arrangement and with regard to the individual circuits numerous modifications are possible without having to leave the inventive concept. For example in the exemplary embodiment for actuating the switching device aie voltage between the wires of the data line evaluated. But it is also possible, the switching device depending on the Control current over the data line or as a function of the frequency of an alternating current signal on the data line or depending on another parameter of a signal on the Data line.

In addition 5 sheets of drawings

Claims (8)

Patent claims: 1. Connection device for establishing a connection between a transmitting and / or receiving unit and a line for transmitting data with signal generating devices which generate an electrical signal on the line with a parameter dependent on the usage state of the line, characterized in that connecting devices (398) for connecting the switching device to the line (23) that first detector devices (400) responding to the parameter are provided which generate a first electrical signal at an output when the value of the parameter differs from the nominal value provided for the free line Parameter deviates by a first predetermined amount that second detector devices (402) responding to the parameter are provided, which are connected to the connection devices (398) and generate a second electrical signal at an output when the value of the parameter is provided at the connection devices (398 ) deviates from the nominal value of the parameter predetermined for the free line by a second predetermined amount which is greater than the first predetermined amount, that first switching means (408) are provided in order to repeatedly generate a third electrical signal at an output, that second switching means (16, 34, 52) are provided in order to generate a fourth electrical signal at an output (F) when a connection to the line (23) is desired, that third switching means (410, 412) are provided to control the the connecting devices (398) effective impedance, in particular the impedance of the switching device depending on a fifth electrical signal at an input to change that fourth switching means (404, 406, 418 to 420) are provided which are connected to the output of the first detector device ( 400), with the output of the first switching means (408), with the output of the second switching means (16, 34, 52) and with at least one input of the third switching means tel (410, 412) are connected in order to apply the fifth electrical signal to the input of the third switching means (410, 412) when the first, third and fourth electrical signals occur simultaneously, unless the second electrical signal is present at the same time. 2. Switching device according to claim 1, characterized in that the second switching means (16,34, 52) generate a sixth electrical signal at an output, if so desired, the Release line (23) and that the fourth switching means (404, 406, 418 to 420) the fifth keep electrical signal away from the input of the third switching means (410, 412) when the sixth electrical signal occurs. 3. Switching device according to claim 1, characterized in that fifth switching means with the fourth switching means (404, 406, 418 to 420) are connected to the application of the fifth electrical signal to the input of the third ¹ ^ switching means (410, 412) despite to enable the occurrence of the second electrical signal when the fifth electrical signal has already been applied to the third switching means (410, 412) for a predetermined time interval. 4. Switching device according to one of claims 1 to 3, characterized in that the to monitoring parameter is the potential on line (23). 5. Switching device according to one of claims 1 to 4, characterized in that the first Switching means comprise an oscillator (408). 6. Switching device according to claim 5, characterized in that the fourth electrical switching means have a flip-flop (406), the data input of which is connected to the first detector devices (400) and to the output of the second switching means (16, 34, 52), whose clock input (CL) is connected to the output of the first switching means (408) and whose reset input (R) is connected to the output of the second detector device (402). 7. Switching device according to claim 6, characterized in that the reset input (R) of the flip-flop (406) is additionally connected to the second switching means (16,34,52) and responds to the sixth electrical signal. 8. Switching device according to claim 7, characterized in that an output signal of the fifth Schaltmktel is used to apply an output signal to the reset input (R) of the flip-flop (406) as a function of the second electrical signal.