DE2633906A1 - MOS integrated circuits mfr., esp. for memories - using layer of polycrystalline silicon to make conductors and electrodes - Google Patents
MOS integrated circuits mfr., esp. for memories - using layer of polycrystalline silicon to make conductors and electrodesInfo
- Publication number
- DE2633906A1 DE2633906A1 DE19762633906 DE2633906A DE2633906A1 DE 2633906 A1 DE2633906 A1 DE 2633906A1 DE 19762633906 DE19762633906 DE 19762633906 DE 2633906 A DE2633906 A DE 2633906A DE 2633906 A1 DE2633906 A1 DE 2633906A1
- Authority
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- Prior art keywords
- layer
- silicon
- silicon nitride
- polycrystalline silicon
- photoresist
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 52
- 239000004020 conductor Substances 0.000 title claims abstract description 12
- 230000015654 memory Effects 0.000 title abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 31
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 34
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 32
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Verfahren zur Herstellung eines Halbleiterbauelementes nachMethod for producing a semiconductor component according to
der Si-Gate-Technik.Si gate technology.
Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes nach der Si-Gate-Technik, wie es im Oberbegriff des Patentanspruches 1 näher bezeichnet ist.The invention relates to a method for producing a semiconductor component according to the Si gate technology, as described in more detail in the preamble of claim 1 is.
Zur Herstellung integrierter NOS-Schaltungen, insbesondere auch zur Herstellung von MOS-Speflcherschaltungen, wird heute bevorzugt die Polysilizium-Gate-Technik eingesetzt. Bei dieser Technik werden die Gate-Elektroden von Feldeffekttransistoren sowie Leiterbahnen zum Anschluß solcher Elektroden aus Polysilizium gebildet. Die wesentlichen Vorteile dieser Technologie bestehen gegenüber einer Technik, bei der diese Elektroden und Leiterbahnen aus Aluminium bestehen, darin, daß die störenden Gate-Source- und Gate-Drain-überlappungskapazitäten sehr klein gehalten werden können und daß in Gestalt des Polysiliziums eine zusätzliche "Leiterbahn"-Ebene vorhanden ist.For the production of integrated NOS circuits, in particular also for Manufacture of MOS memory circuits, the polysilicon gate technology is preferred today used. In this technique, the gate electrodes of field effect transistors are used and conductor tracks for connecting such electrodes are formed from polysilicon. the There are significant advantages of this technology over a technology in which These electrodes and conductor tracks are made of aluminum, in that the interfering Gate-source and gate-drain overlap capacitances can be kept very small and that in the form of the polysilicon there is an additional "conductor track" level is.
Bei der üblichen Polysilizium-Gate-Technik bereitet allerdings die Ätzung des Polysiliziums Schwierigkeiten, da durch Herausätzen die Leiterbahnen aus Polysilizium nur schwer mit einer glatten, nicht zu steilen Böschung hergestellt werden können. Da aber in vielen Fällen über die Polysilizium-Bahnen hinweg andere Schichten haftend aufgebracht werden sollen, müssen die Polysilizium-Bahnen selbst mit glatten Böschungen versehen sein, die nicht steiler als etwa 600 verlaufen. Eine weitere Schwierigkeit entsteht bei der Ätzung von Polysilizium aufgrund der Unterätzungen der verwendeten Ätzmasken, da bei serienmäßiger Herstellung die Unterätzung nicht bei jedem Chip gleichmäßig konstant ist, sondern jeweils anders und unreproduzierbar ausfällt.With the usual polysilicon gate technology, however, the Etching of the polysilicon Difficulties because the conductor tracks are etched out made of polysilicon only with difficulty with a smooth, not too steep slope can be. But in many cases there are others across the polysilicon tracks If layers are to be applied in an adhesive manner, the polysilicon tracks themselves must be applied with smooth slopes be provided that are not steeper than about 600 run. Another difficulty arises when etching polysilicon due to the undercutting of the etching masks used, as in series production the undercutting is not uniformly constant for each chip, but different in each case and turns out to be unreproducible.
Aus dem Stand der Technik ist bekannt, daß zum Abflachen der steilen, oft sogar überhängenden Polysilizium-Böschungen eine Phosphorpentoxid-haltige Siliziumdioxidschicht (Phosphorsilikatglas) auf die herausgeätzten Siliziumbahnen abgeschieden wird und sodann auf 1050 bis 11000C erhitzt wird. Bei Erhitzen auf solche Temperaturen gerät die Schicht aus Phosphorsilikatglas in einen zähflüssigen Zustand, so daß die steilen bzw. gezackten Polysiliziumstufen und Böschungen mit einer Phosphorsilikatglasschicht überzogen und dadurch fast vollständig eingeebnet werden. Dieses Verfahren hat jedoch den erheblichen Nachteil, daß bei größerem Phosphorgehalt des Phosphorsilikatglases Korrosionserscheinungen an dem Halbleiterbaueiement auftreten, und daß weiter eine Ätzung von Kontaktlöchern durch die Phosphorsilikatglasschicht schwierig ist.From the prior art it is known that to flatten the steep, often even overhanging polysilicon slopes a phosphorus pentoxide-containing silicon dioxide layer (Phosphosilicate glass) is deposited on the etched silicon tracks and then heated to 1050 to 11000C. When heated to such temperatures device the layer of phosphosilicate glass in a viscous state, so that the steep or jagged polysilicon steps and slopes with a phosphosilicate glass layer covered and thereby almost completely leveled. However, this procedure has the significant disadvantage that with a larger phosphorus content of the phosphosilicate glass Corrosion phenomena occur on the semiconductor component, and that further a Etching of contact holes through the phosphosilicate glass layer is difficult.
Aufgabe der Erfindung ist es, ein Verfahren zur Herstellung eines HalbX;iterbauelementes nach der Silizium-Gate-Technik anzugeben, durch das erreicht wird, daß die bei dieser Technik gebildeten Elektroden und Leiterbahnen aus Polysilizium mit Böschungswinkeln kleiner als 600 und ohne Überhänge versehen sind.The object of the invention is to provide a method for producing a HalfX; iterbauelementes according to the silicon gate technology, achieved by the is that the electrodes and conductor tracks formed in this technique are made of polysilicon are provided with slope angles smaller than 600 and without overhangs.
Diese Aufgabe wird bei einem wie im Oberbegriff des Patentanspruches 1 angegebenen Verfahren erfindungsgemäß nach der im kennzeichnenden Teil des Patentanspruches 1 angegebenen Weise gelöst~ Die Erfindung beruht auf der Erkenntnis, daß bei einer selektiven Oxidation einer Polysiliziumschicht durch eine Oxidationsmaske hindurch die Seitenflächen der dabei entstehenden Siliziumdioxidbahnen einen Neigungswinkel aufweisen, der etwa 450 beträgt. Werden nun die zu entfernenden Bereiche der Polysiliziumschicht nicht durch ohemisches Ätzen, sondern mit Hilfe selektiver Oxidation und anschließenden Abätzen des dabei entstehenden Siliziumdioxids entfernt, so sind die verbleibenden Polysiliziumbahnen und Polysilizium-Elektroden mit Böschur.gswinkeln von etwa 450 versehen. Sie weisen ferner auch keine Uberhänge oder starke Zacken auf.This task is as in the preamble of the claim 1 specified method according to the invention according to the in the characterizing part of claim 1 specified way solved ~ The invention is based on the knowledge that in a selective oxidation of a polysilicon layer through an oxidation mask the side surfaces of the resulting silicon dioxide webs a Have an angle of inclination which is approximately 450. Now are the areas to be removed the polysilicon layer not by ohemical etching, but with the help of selective Oxidation and subsequent etching of the resulting silicon dioxide removed, so are the remaining polysilicon tracks and polysilicon electrodes with Böschur.gswangeln of about 450 provided. They also have no overhangs or strong jagged edges on.
Besondere Ausgestaltungen der Erfindung ergeben sich aus den Unteransprüchen. Es ist insbesondere von Vorteil, als Oxidationsmaske eine Schicht aus Siliziumnitrid zu verwenden. Um zu verhindern, daß bei dem Entfernen der nach der Oxidation des Polysiliziums entstandenen Siliziumdioxidbereiches die unter der Polysiliziumschicht liegende Siliziumdioxid-Isolierschicht so stark angegriffen wird, daß dabei Unterätzungen der verbleibenden Polysiliziumbahnen entstehen, wird nach einer weiteren Ausgestaltung der Erfindung vor dem Abscheiden des Polysiliziums auf die Siliziumdioxidschicht zunächst eine dünne Schicht aus Siliziunnitrid aufgebracht, und sodann die Schicht aus Polysilizium abgeschieden. Diese Schicht aus Siliziumnitrid wirkt als Ätzbremse beim Entfernen der Siliziumdioxidbahnen, die bei der selektiven Oxidation der Polysiliziumschicht entstehen. Bei einer nachfolgenden Ätzung kann dann diese erste Siliziumnitridschicht entfernt werden, wobei die dabei auftretende Unterätzung der Siliziumnitridschicht so klein gehalten werden kant, daß sie nicht mehr stört.Special refinements of the invention emerge from the subclaims. It is particularly advantageous to use a layer made of silicon nitride as the oxidation mask to use. In order to prevent the removal of the after oxidation of the Polysilicon formed silicon dioxide area under the polysilicon layer The silicon dioxide insulating layer lying on the ground is so severely attacked that it is undercut of the remaining polysilicon tracks are created according to a further embodiment of the invention prior to depositing the polysilicon on the silicon dioxide layer first a thin layer of silicon nitride is applied, and then the layer deposited from polysilicon. This layer of silicon nitride acts as an etching brake during the removal of the silicon dioxide tracks, which occurs during the selective oxidation of the polysilicon layer develop. In a subsequent etching, this first silicon nitride layer can then are removed, the undercutting of the silicon nitride layer that occurs edges are kept so small that they are no longer bothersome.
Im folgenden wird beschrieben und anhand der Figuren näher erläutert, wie das erfindungsgemäße Verfahren durchgeführt wird.In the following it is described and explained in more detail with reference to the figures, how the method according to the invention is carried out.
Fig.1 zeigen eine Ausführungsart des erfindungsgemäßen Verbis 5 fahrens, Fig.6 zeigen eine zweite Ausführungsart.1 show an embodiment of the verb 5 according to the invention, Fig. 6 show a second embodiment.
bis 10 Gemäß der ersten Ausführungsart des erfindungsgemäßen Verfahrens wird auf einem Halbleitersubstrat 1, das beispielsweise aus Silizium besteht, als erste Isolierschicht 2 eine. Siliziumdioxidschicht, deren Dicke bereichsweise zwischen 30 und 120 nm (Gate-Oxidbereiche) und bereichsweise zwischen 300 nm und 1200 nm, insbesondere etwa 600 nm (Feld-Oxidbereiche), beträgt, abgeschieden. In Fig.1 ist nur die Feld-Oxidschicht dargestellt. Auf diese Siliziumdioxidschicht 2 wird eine Schicht 3 aus polykri stallinem Silizium abgeschieden. Das Abscheiden dieser Polysiliziumschicht erfolgt beispielsweise durch Aufdampfen oder Aufsputtern. Diese Schicht 3 aus Polysilizium hat eine Dicke æwischen etwa 300 nm und 500 nm. Auf diese Schicht 3 aus polykristallinem Silizium wird eine Schicht 4 aus Siliziumnitrid (Si3N4) mit einer Dicke von etwa 100 nm abgeschieden. Auf diese Schicht 4 aus Siliziumnitrid wird eine Fotolackschicht 5 abgeschieden, durch eine Fotomaske belichtet und entwickelt, so daß diese Fotolackschicht 5 mit Strukturen versehen wird (Fig.1). An den vom Fotolack befreiten Stellen wird mit einem Ätzmittel, z.B. mit heißer Phosphorsäure, die Siliziumnitridschicht 4 entfernt. Sodann werden die Reste der Fotolackschicht 5 entfernt und es werden diejenigen Teile der Polysiliziumschicht 3, die von der Siliziumnitridschicht 4 befreit worden sind, durch Erhitzen in Gegenwart von Sauerstoff und Wasserdampf in Siliziumdioxidgebiete 6 verwandelt. Da diese Oxidation des Polysiliziums nicht nur in der zur Substratoberfläche senkrechten Richtung, sondern auch zur Seite hin drfolgt, sind die bei der Oxidation des Polysiliziums entstehenden Siliziumdioxidgebiete 6 flächenmäßig etwas größer als die in der Siliziumnitridschicht 4 erzeugten Fenster 8. Die Oxidation des Polysiliziums zu Siliziumdioxid ist mit einer Volumenvergrößerung verbunden. Dies bewirkt, daß die als Oxidation maske dienenden Teile 10 der Silizi'umnitridschicht 4 an ihren Rändern 9 von dem erzeugten Siliziumdioxid nach oben gedrUckt werden. Die Oxidation erfolgt so lange, daß die Schicht 3 aus Polysilizium unter den Fenstern 8 durchoxidiert wird, so daß die dabei erzeugten Gebiete 6 aus Siliziumdioxid bis an die Siliziumdioxidschicht 2 heranreichen (Fig.3).to 10 According to the first embodiment of the method according to the invention is on a semiconductor substrate 1, for example made of silicon exists, as the first insulating layer 2 a. Silicon dioxide layer, the thickness of which in certain areas between 30 and 120 nm (gate oxide areas) and in areas between 300 nm and 1200 nm, in particular about 600 nm (field oxide areas) is deposited. In Fig.1 only shows the field oxide layer. On this silicon dioxide layer 2, a layer 3 of polycrystalline silicon is deposited. The deposit this polysilicon layer takes place, for example, by vapor deposition or sputtering. This layer 3 made of polysilicon has a thickness between approximately 300 nm and 500 nm. A layer 4 made of silicon nitride is placed on this layer 3 made of polycrystalline silicon (Si3N4) deposited with a thickness of about 100 nm. On this layer 4 made of silicon nitride a photoresist layer 5 is deposited, exposed through a photomask and developed, so that this photoresist layer 5 is provided with structures (FIG. 1). On the from Areas that have been removed from the photoresist are treated with an etching agent, e.g. with hot phosphoric acid, the silicon nitride layer 4 is removed. Then the remnants of the photoresist layer 5 removed and there are those parts of the polysilicon layer 3, which are from the Silicon nitride layer 4 have been freed by heating in the presence of oxygen and water vapor is transformed into silicon dioxide regions 6. Because this oxidation of the polysilicon not only in the direction perpendicular to the substrate surface, but also to the side Then there are the silicon dioxide areas formed during the oxidation of the polysilicon 6 somewhat larger in area than the windows produced in the silicon nitride layer 4 8. The oxidation of the polysilicon to silicon dioxide is with an increase in volume tied together. This has the effect that the parts 10 of the silicon nitride layer serving as an oxidation mask 4 are pressed upwards at their edges 9 by the silicon dioxide produced. The oxidation takes place so long that the layer 3 of polysilicon under the windows 8 is through-oxidized, so that the regions 6 made of silicon dioxide up to reach up to the silicon dioxide layer 2 (FIG. 3).
Im nächsten Verfahrensschritt wird die als Oxidationsmaske die nende Siliziumnitridschicht 4 entfernt (Fig¢4). Als letzter Verfahrensschritt erfolgt dann das Entfernen der Siliziumdioxidgebiete 6, was beispielsweise durch Ätzen in gepufferter Flußsäure erfolgt. Dadurch werden die vorgesehenen Elektroden bzw.In the next step, the oxidation mask is used Silicon nitride layer 4 removed (Fig. 4). As last one Process step the removal of the silicon dioxide regions 6 then takes place, for example by Etching takes place in buffered hydrofluoric acid. This will create the electrodes provided respectively.
Leiterbahnen 12 aus Polysilizium freigelegt. Die Seitenflächen 13 dieser Elektroden bzw. Leiterbahnen aus Polysilizium haben einen Böschungswinkel von etwa 45O. Um zu gewährleisten, daß die Siliziumdioxidgebiete 6 durch das Ätzen vollstandig entfernt werden, muß die Ätzzeit etwas größer bemessen werden als die zum Entfernen dieser Gebiete 6 minimal erforderliche Ätzdauer. Das hat zur Folge, daß auch die Siliziumdioxidschicht 2 angeätzt wird, so daß in ihr kleine Mulden 11 entstehen, die in Unterätsungsgebieten 7 unter die Bahnen aus Polysilizium 12 reichen.Conductor tracks 12 made of polysilicon exposed. The side surfaces 13 these electrodes or conductor tracks made of polysilicon have an angle of slope of about 45O. In order to ensure that the silicon dioxide regions 6 by the etching are completely removed, the etching time must be made somewhat longer than that the minimum etching time required to remove these areas 6. This has the consequence that the silicon dioxide layer 2 is etched, so that in her small hollows 11 arise, which in underlaid areas 7 under the tracks of polysilicon 12 are sufficient.
Nach der zweiten Ausführungsform des erfindungsgemäßen Verfahrens können diese Unterätzungen vermieden werden, wenn nach dem Aufbringen der Siliziumdioxidschicht 2 auf diese zunächst eine Hilfsschicht 14 aus Siliziumnitrid aufgebracht wird. Diese Hilfsschicht 14 hat eine Dicke zwischen 30 und 70 nm. Auf die Hilfsschicht 14 wird sodann die Schicht 3 aus polykristallinem Silizium aufgebracht, auf diese sodann die als spätere Oxidationsmaske dienende Siliziumnitridschicht 4, auf diese Siliziumnitridschicht 4 eine Fotolackschicht 5. Das weitere Verfahren zur Erzeugung der Bahnen 12 aus polykristallinem Silizium erfolgt wie bei der eben beschriebenen ersten Ausführungsform des erfindungsgemäßen Verfahrens (Fig.7, 8, 9).According to the second embodiment of the method according to the invention these undercuts can be avoided if after the application of the silicon dioxide layer 2, an auxiliary layer 14 made of silicon nitride is first applied to this. These Auxiliary layer 14 has a thickness between 30 and 70 nm then the layer 3 made of polycrystalline silicon is applied to it the silicon nitride layer 4, which will later serve as an oxidation mask, onto this silicon nitride layer 4 a photoresist layer 5. The further method for producing the tracks 12 from polycrystalline silicon takes place as in the first embodiment just described of the method according to the invention (FIGS. 7, 8, 9).
Nach dem Entfernen der Siliziumdioxidgebiete 6 wird dann zum Freilegen der Siliziumdioxidschicht 2 die Hilfsschicht 14 aus Siliziumnitrid an den zwischen den Bahnen aus polykristallinem Silizium 12 liegenden Teilen abgeätzt. Dabei werden die Bahnen bzw. Elektroden 12 aus polykristallinem Silizium als Ätzmäske verwendet. Bei dem Entfernen der Hilfsschicht 14 treten dann wiederum Unterätzungen 7 der Bahnen aus polykristallinem Silizium 12 auf, jedoch sind diese Unterätzungen sehr gering. Wenn die Hilfsschicht 14 aus Siliziumnitrid hinreichend dünn aufgebracht wird, z.B. mit einer Dicke von nur ca. 50 nm, sind diese Unterätzungen 7 so gering, daß sie vernachlässigt werden können.After the silicon dioxide regions 6 have been removed, it is then necessary to expose them the silicon dioxide layer 2, the auxiliary layer 14 made of silicon nitride on the between the tracks of polycrystalline silicon 12 lying parts are etched away. Be there the tracks or electrodes 12 made of polycrystalline silicon are used as etching masks. When the auxiliary layer 14 is removed, undercuts 7 of the tracks then occur again of polycrystalline silicon 12, but these undercuts are very small. If the auxiliary layer 14 made of silicon nitride is applied sufficiently thin, e.g. with a thickness of only about 50 nm, these are Undercuts 7 so small that they can be neglected.
6 Patentansprüche 10 Figuren6 claims 10 figures
Claims (6)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0005351A1 (en) * | 1978-04-27 | 1979-11-14 | Xerox Corporation | A method of making a narrow gate MESFET |
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1976
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0005351A1 (en) * | 1978-04-27 | 1979-11-14 | Xerox Corporation | A method of making a narrow gate MESFET |
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