DE2610749A1 - FREQUENCY-TIME MULTIPLEX TRANSMISSION SYSTEM - Google Patents

Description

Pile 4624-2

Patent attorneys

Dipl. Ing.Hans-Jürgen Müller Munich, March 15, 1976

Br. Rer. nat. Thomas Berendt ^scn

• S Mönchen 80 Lucile-Grahn-Straße 38

NS EIdSCl ¹ ROErICS, 1386 West KoMnwood Lane, Fresno , CaI.937Od (V.LJt.A.)

Frequency-time division multiplex transmission system

In order to allow a larger number of participants access to the same transmission medium, a large number of Multiplexing has been created. The "two major methods are frequency division multiplexing and Time division multiplexing "known. The application of these" two Procedure in the field of telephony h.at enables that two pairs of conductors of "up to 24 and more participants at the same time" can be used. Try that take advantage of the low probability that all participants of a time division multiplex system speak at the same time approach led to switching units known as concentrators These switching units, one of which is in the toll switch and the other is commonly used in the vicinity of a remote group of subscribers to be "served" is arranged, allow "up to three times or even more participants than the time division multiplex system (typically a PCM system) can actually operate simultaneously (usually 24), potential access to Toll switch. The disadvantage of these systems is

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that in the unlikely pail that more than e.g. 24 Participants request access to the system, only the first "to be served; the rest must wait" for a free one Channel is available.

Since the narrow pulses used in time division multiplexing systems have a fairly "wide pass band" at the correct Requiring transmission, regenerative amplifiers must be provided at specific locations along a cable to compensate for the strong attenuation of the higher frequencies by the cable. Such amplifiers generate a new pulse instead of each pulse detected at the input of the amplifier. The acquisition step is hindered by a phenomenon known as pulse instability and random errors in the pulse train which appear as interference signals in the subscriber's receiver.

A combination of frequency division multiplexing and time division multiplexing (Frequency time division multiplexing) is used in systems such as the RADA system (single address with optional Access) applied. In these systems, information is transmitted using an addressing scheme in which signals or impulses with high frequency energy are transmitted at certain frequencies and at certain moments of time. This addressing scheme can be more easily understood using a frequency-time matrix, which is an arrangement of "holes" in the frequency-time domain, each hole being defined by a particular frequency and a particular one Time slot within a larger time interval is considered as a time sub-range. An address consists of a group of two or more high-frequency

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pulses, the predetermined holes in the frequency-time matrix "occupy. Due to the large number of addresses that can be defined on the matrix in this way, a specific address can be assigned to each bit of subscriber information.

Frequency time division multiplexing systems using this type of addressing are subject to misaddressing, and inadvertently Transmitted addresses are received anyway, because high-frequency pulses received from a large number of participants are generated, occupy hole combinations on the frequency time matrix in an arbitrary manner, which are used as subscriber addresses are defined. Such incorrect addresses generate an interference signal background (intrinsic interference signals), which is also associated with The number of participants increases rapidly.

In the improvement of a frequency time division multiplex system according to US patent application Kr. 359 864 of the applicant, in particular with regard to the reduction of self-interference signals, it was found that the frequency time matrix has significantly greater information content potential than previously assumed. It should be noted that previous Frequency time division multiplexing systems on a two-valued or binary state for each hole in the frequency time matrix based, d. H. each hole only has either the presence or the absence of an impulse. The present invention makes use of this greater potential and also eliminates the problem of inherent noise. Furthermore is it through a radix or base conversion process the invention enables more participants to be concentrated in the system without reducing the required bandwidth significantly must be increased and without reducing the ability of participants to access the system,

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how this "is the Pail with the concentrators which have been customary up to now. After all, "the typical ents-marriage circuit structure is based of receivers in time division multiplex systems on the Detection of narrow, interference signal-like impulses, and in the presence of normal interfering signals it is difficult for a receiver to distinguish between interfering and correct pulses to distinguish; So if the desired information is accompanied by interfering signals, there is a likelihood that the output signal of the time division multiplex receiver contains digital errors. The invention significantly improves the decision-making area, that several repeated events are received before a decision on the correct one State is carried out. It should also be noted that time division multiplex systems using telephone cables are local Changes to the cable characteristics are subject, which results in different transit times for different frequencies resulting in a distortion of the pulse shape. In the invention allows the use of sinusoidal RF carriers in the frequency time matrix that the system is relative is immune to such problems resulting from cable abnormalities.

Due to the larger information content potential in one Frequency time matrix, the invention is particularly useful for High-speed data transmission uni? · Freeignet.

In addition to the previously mentioned US patent application ¹ , reference is also made to US patents 3,806,655 and 3,769,4M and the publication "Bell System Technical Journal", Volume 53, ITr. 5, pp. 867-936.

The invention is applicable to various types of message transmission systems as well as data transfer systems

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reversible. For the sake of clarity, the invention however primarily in relation to a telephone connection system explained. Of course there is an analog-digital conversion a speech information sub-transmission system a data transmission system is not required. When used in the field of data transmission is to Note that all data that can be represented by digital words (groups of digits) are postulated by the system of the invention are processable in either sequential or parallel form.

The transmission system according to the invention comprises a plurality of transmitters and receivers, each with a transmission medium, e.g. B. electromagnetic or optical transmission paths that can transmit modulated signals, are connected. Each transmitter and receiver can serve a reciprocal number of subscribers and can be arranged at various points along the transmission medium. Each transmitter has two main functions, the first of which is a combined storage, time stretching and reading out of pulses which represent information bits arriving on subscriber input lines. These pulses are typically generated in the transmitter either by delta modulators, which convert the speech information into direct information, or by coupling or interface circuits that are used in the data transmission. The second puncture of the transmitter is the processing of these temporally stretched pulses so that one of several predetermined phase shifts is determined in each time slot of a time sub-range for an assigned HP carrier of a frequency time matrix ".

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The explanation of the transmitter function is simplified by that the address assignment of each subscriber corresponds to a time slot in a time sub-range of the frequency time matrix. The number of time slots in a time sub-range is represented by ρ. The receiver according to the invention returns the Transmitter functions essentially around, with the exception of the phase displacement detectors, which relate to the identification generate a redundancy of the received phase. The storage, time stretching and reading of subscriber input information bits or -impulses is saved by keying the input impulses into separate q storage registers performed, where q is an integer representing the number of information bits or pulses within a time sub-range means, where a sequentially occurring group of time intervals forms a time sub-range. In one In a certain first time sub-range, these pulses are keyed into a first group of storage registers. By doing The inputs of this first register group are blocked and the outputs of the Register opened. A second group of registers receives the Pulses in the second time sub-range, while the first group of stored pulses is read out. These two groups of registers swap their roles during alternate time sub-areas. The shorter input pulse of each information bit period is stored in this way for the entire duration of the next time sub-range and thereby "stretched" for reading. The outputs of the two registers that are assigned to one of the q bits are linked and form a single output line, the total number of output lines being q, and on each Line there is either a pulse or no pulse, each with a duration equal to the period of the time subrange.

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Then the stretched pulses are typically processed through a group of ρ UKD matrices, each of which a "true" state on one of 2 ^ matrix output lines generated. The size 2 ^ is the number of different Binary links created by a UID matrix of pulses or the absence of pulses on the q Matrix input lines can be generated. Depending on the type of subscriber signals entered some of the 2 ^ combinations can be sufficient unlikely, so it may not be necessary is to provide output lines for each of the combinations. Assume that the number Output lines of an AND matrix is m, with m ^ 2 ^. The true state of one of these m lines, which has the duration of an entire sub-area, becomes a Phase shifter keyed in, the phase of which has a predetermined relationship to the true state represented by this specific condition. The duration and the cycle of the key pulse correspond to the assignment of the particular Subscriber to one of the ρ timeslots in the time sub-range. The phase shifter regulates the phase of an HP carrier, the frequency of which has been assigned to this particular group of ρ subscribers.

There is a direct correspondence between the phase shift values in each of the ρ timeslots with m different values for each time slot transmitted information and a p-digit digital word (or a Digital number) with the base m. This match is a particularly useful means of performing a Basic conversion, which extends the system if necessary using the same frequency time matrix and no significant increase in bandwidth he follows.

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The Terfahren and system according to the invention can Parts of the transmitter and receiver units also work as regenerative amplifiers. The recipient captures reconstructs the phase shift level in each time slot, using the acquired information local transmitter a new HP carrier, which synchronizes with the received carrier and to the corresponding Amounts is out of phase.

The input impulses were used for data transmission only Storage part are fed. Both in voice information and in data transmission are According to the invention, several periods of the phase-shifted carrier are transmitted per time slot, and thus result there are several opportunities in the system for the acquisition of the phase shift value. A decision maker is used in the receiver that uses this feature and thereby the likelihood of occurrence of Interference signals at the output due to incorrectly detected phase shifts are significantly reduced.

The invention therefore creates a message or data transmission system that has one or more Transmitter has; the input signals, if required, converted into digital impulses, these impulses stored and stretched over time; the impulses are in Time frequency matrix addresses are implemented, and each of a group of radio frequency carriers is within a specific one Time slot at one of a predetermined number of phase angles during each time sub-range to überertrapxrair out of phase so that the number of Information bits that can be transmitted within a given bandwidth are maximized and transmission errors be minimized. With the transmitters via a

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trammgsmedium, ζ. B. a telephone cable, connected receivers reverse the processing steps of the senders.

An embodiment of the invention: is shown below explained in more detail with reference to the drawing. It lines:

ig. 1 is a block diagram of a shared telephone interconnection system with the basic components according to the invention;

Pig. 2 shows the block diagram of a receiver-transmitter unit and a pulse processing unit according to the invention;

Pi/?. 3 shows the circuit diagram of a storage, time stretching and reading unit according to the invention;

Pig. 3A waveforms in specific areas and 3B of the circuit according to Pig, 3;

Pig. 4 shows the circuit diagram of the AND matrix ! "ig. 2;

Pig. Figure 4A shows the wiring diagram of part of the Pig matrix. 4;

Pig. 5 shows the block diagram of a receiving part of a receiving-transmitting unit;

Pig. 6 is a block diagram of a conversion circuit used in the invention;

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Pip ¹ . 7 shows the block diagram of the transmitting part of a receiving-transmitting unit according to the invention

^p . ei.-n circuit diagram of a simplified transmission part? mr YeranscTiaulichimg · the operation of the same;

8A waveforms at certain points the circuit according to Pig. 8 occur;

Pig. 9A shows the block diagram of a sequential data processing unit which is used in FIG Invention is applicable;

Pig. 9B is the block diagram of a parallel

Data processing unit applicable to the invention; and

Pig. 10 shows the block diagram of a basic conversion calculator which is used in the circuit according to Pig. is used.

A telephone connection system according to the invention can operate with a considerable number of subscribers; to the To simplify the explanation, however, the drawings are limited to only a few subscriber input lines. Pig. 1 shows the overall block diagram of a typical interconnection system according to the invention, with several subscriber input signals are given in the form of voice signals. This is where the participants usually find themselves in different places, and about the versatility of the

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To explain the invention is limited to the following Description on this structure. It should be noted, however, that the invention also applies to one-way or two-way point-to-point connections is applicable, with all subscriber signals in the same common Unit can be entered. It should be noted that when using this connection system according to FIG In telephony, the voice signals are typically sent in both directions. When explaining by Pig. 1 and the following figures, it should be noted that the transmission of signals from the subscriber to the central office end office. Since the process of processing the signals in reverse Direction required facilities are identical, they are not explained, speech signal converter (telephone receiver) and modulators and pulse processing units associated with them are shown at 21-27. The modulator section of each pulse processing unit is typical a delta modulator, but it should be noted that the invention is not limited to this type of modulation, because the analog-to-digital converters of other devices also generate digital signals. For this reason the modulator element of each pulse processing unit is not explained in detail. The pulse processing stage the unit is used to convert the binary subscriber signals arriving sequentially at high bit rate in m-ary digital signals with lower speed. The pulse processing stage is still used in conjunction with Figs. 2, 3, 4 and 6 explained.

The participants 21, 22 and 23 are connected to a single receiving-transmitting unit 28, which is one of several Possibilities for the connection of participants to

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aas system. Other options are through the connections 24, 25, 26 and 27 are shown and will be explained later. In the description "refers the term "module" "or" building block "refers to the common Device consisting of a double receive-transmitter unit as well as individual modulator and pulse processing units, which "serve" several participants together, as is indicated at 36. Further Note that the term "receive" has a dual function. "One of those punctures "consists of the usual acquisition of a high-frequency signal and its conversion into one for the subscriber suitable shape. The second! Puncture is that of a receiver in a regenerating amplifier, wherein the detected signal is processed for immediate retransmission. Pig. 1 shows regenerative Repeater 29, 30 and 31. Kie Repeater function will still in connection with the receiving part after the Pig. 2 and 5 explained.

A base or radix conversion calculator that can be seen if necessary 32 can be used to concentrate more participants in the system without degradation performance and a noticeable increase in the required bandwidth. It should be noted that the subscriber signal at the output of a modulator and pulse processing unit m-ary has digital form and in this form can be viewed as a single digit with the base m. A Multi-digit digital word with the base m is created by combining the individual digits of several Output signals from the modulator and pulse processing units educated. By converting to a higher one

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Basis, this multi-digit word takes up fewer places, so that more subscriber signals are multiplexed can be included in the system. The basic conversion calculator is referenced in detail on Mg. 2 and 10 explained.

A central office end office 33 is a typical one End station for a subscriber or self-dialing multi-channel system. This end office is provided with circuits in addition to the speech signal processing units for processing monitoring characters such as "hang up / pick up", ringing, dialing and automatic number recognition. No further explanation of this end office is required, as those required for speech signals Circuits are designed identically to the circuits at the participant locations. Required Circuits for surveillance gauges are not used here "as they are well known.

Fig. 2 is the block diagram of circuit units used in a typical double receive-transmit unit 34 and a pulse processing unit 39 of the system of FIG. 1 are provided. There are two in each module Receiving-transmitting units 41 and 42 required. Signals fed from the left by a regenerating amplifier 29 are first detected by a receiving element 43 of the receiving-transmitting unit 42. A first The output signal of the receiving element 43 is matched with the input signal a left-right clock signal generator 44 coupled to synchronize receiver phase detectors and relaying logic elements 46. A second output signal of the receiving element 43

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holds the signal information to be passed on through these logic elements. The output signal of the Logic elements are phase shifters of a transmitting unit 47 for controlling the phase of the relayed Carrier waves are carried out. More details of the Receiving-transmitting units are explained in connection with FIGS. 5 and 8.

Local participants, the signals to the right by Pip ·. Send 2, deliver sequential binary sismals to typical inputs 51a, 51 "b and 51c. These binary signals are processed by a group of memory, time stretching, and reading re-ectors 56. The parallel Output signals from these registers are fed to a group of UBD matrices 57, each of which is a group of m has output lines. Only one leadership in each group has a "true" state during any given Time subrange. An optional base conversion calculator 58 can be used to connect these matrix output lines to the transmit logic gates 46 to connect the transceiver unit 42 and thereby the processed signals from the local participants on the transmission medium to the right.

Input signals from the right side of Pig. 2 kick into the receiving-transmitting unit 41 and are operated in an identical manner as in the receiving-transmitting unit processed, with the exception that certain signals are taken from receiving element 59 for reception by subscribers, on a third output line and decoded. If not an optional base conversion calculator 53 is used, the input of the im-

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pul s ver ar "belters 39 from the receiver 5 °>" actually to the τη lines per participant. A decoder 54 converts the parallel digital input into an equivalent binary output signal in seauential form, which is the desired output signal form for the participants and is typical. Outputs 52a, 52b and 52c appear. In this example, further processing would be required to demodulate these signals into analog form at speech frequencies.

It should be noted that only a single base conversion calculator must be provided to perform the functions of units 53 and 58 of Fig. 2 and this calculator serves a dual purpose as it works both on the left-right path (speaking) and the reent-left-we £ (listening) is used. This dual purpose is a transformation of. from a low to a higher base on the speech path and an inverse conversion on the auditory path. As mentioned earlier, this conversion is the inclusion a bigger one. Number of participants in the system possible. These conversions, which are separate from one another, can be carried out by a single small computer operating in the time division multiplex process be performed. A further explanation is given in connection with FIG. 10.

Figure 3 shows the storage, time stretching and reading means 56 according to FIG. 2, the five sampling pulses per time sub-range (q = 5) processed for a single participant. At the moment a binary bit sequence occurs at input 61 this single subscriber source. As already mentioned, this subscriber source is not based on output signals of a typical delta modulator

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however, be held for it. This modulator converts the analog signals generated by the subscriber into digital ("binary) form, and rwar by using a sampling circuit. Such a sampling circuit samples the rate of change τοπ speech signals at a speed that is significantly higher than the highest zn transmitted speech frequencies? ⁷ This scanning speed also becomes the speed of the binary bit sequence which is fed to the connection 61.! Furthermore, the connections 62 and 63 are fed with alternating partial area signals, which cause the registers to swap roles from one partial area to the next. Five clock pulses, sequential and occur repeatedly in partial areas, terminals 64, 65, 66, 67 and 68 are applied for keying each input signal into a separate register for storage purposes.

Clock signals for the circuit are provided by a clock signal generator 44 according to Pig. 2 generated, which receives a pilot carrier from a telephone exchange and has divider lilacs that generate the required clock signals. For example, the 600 kHz pilot carrier divided by 12 produces an early 50 kHz sampling pulse and ^{a late sampling pulse with a delay 1} of less than 1/50 kHz. By further dividing the 50 kll ^ signal by five, a 10 kHz subrange rate is generated, which when divided by two alternating subrange signals at connections 62 and 63 of Pig. 3A generated. Sampling pulses fed to a five-digit shift register, which can be reset at the beginning of each sub-area, generate signals with time intervals that are specified at terminals 64-68 according to Pig. 3B.

Before the circuit according to Pig. 3 is explained further, the purpose of the memory, time stretching and reading

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register. As mentioned earlier, the short input pulse during each information bit period stored for the entire duration of the next sub-area and thus "stretched" for reading. Since q also was defined as an integer, which means the number of information bits in a time sub-range, it can be seen that all q-states have to be saved and later to be enabled by separate registers on separate output lines. This saving, time stretching and readout enables the subsequent parallel Linking of bit number patterns in an IBTD matrix. For. The Participants are provided with m starting lead courses: n, and one "true" status signal is on one of these lines present for an entire time sub-range. There is a direct correspondence between a given one Course of the q information bits and a "true" signal on one of the output lines of the UBD matrix and further correspondence between the "true" signal of the matrix line and a specific phase-shifted one Carrier visible during a certain time slot. In other words means a single "True" signal, represented by a certain phase shift, that the system in an earlier part of the range a certain information bit sequence has been supplied.

Referring again to FIG. 3, this becomes the case The method and the system explained by the individual bits of the binary bit stream at connection 61 appropriate Registers are fed. TOTD members 71, 73, 75, 77 and 79 are open during an entire partial range by a logic "1" on terminal 62. In the same way AND gates 72, 74, 76, 78 and 80 are opened by a logic "1" at terminal 63. These opening pulses to the

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Ports 62 and 63 are always complementary; H., when terminal 62 has a logic "1", points the connection 63 has a logic "O" and vice versa. Feeding takes place simultaneously within each sub-area individual bits to suitable registers in this way "causes separate logic pulses to be sent to connections 64-68 which occur in five "different bit periods; these impulses" cause that the correct AND element is switched on in the correct sequence.

To illustrate the lateral relationship between the information bits and the register contents and the elesenen from ^ information, reference 3A is set to "iff!. Reference. A typical example of an information bit at terminal 61 is shown here, the part area A, the bit sequence 10110 and the Sub-area B has the bit sequence 01010. The combination of clock signals at the connections 62-68 controls each of these bit sequences in the intended group of registers, as shown in the figure. Furthermore, signal ^{curves 81!} -90 ^T are shown, which contain the contents of registers 81- 90 in a temporal relationship to the input signals. To complete the picture, register readout signals (at the output of AND gates 91-100) for three sub-areas are shown in Pig. that the information bits during the sub-area immediately preceding sub-area A were all fills.

Fig. 4 shows a typical AND matrix, where the signals at the outputs 101-105 of FIG. 3 connections 121-125

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to the left of Pig. 4 are fed. The purpose of the TIMD matrix is to receive the various 2 ^ binary links from the q read output lines of the storage registers and to generate a "true" output signal on m output lines which represents a certain binary link that is present during a certain subrange. The matrix itself is formed in the usual way from diodes or logic gates 126 and has connections from the refister outputs on its left side, which have q lines, with q = 5 in this Pail. Each input 121-125 is directly connected to a separate matrix line. and via an assigned EICHT element 121 ^! -125 ^! connected to a second separate matrix line. An example of the operation by which a "true" status signal is generated and pin 144 to Pig. 4? Vu? Will now be explained as a typical UIHD matrix function. It is assumed that five parallel bits have such states that the connections 121, 123 and 125 have a logic "O" and the connections 122 and 124 have a logic "1" (+) corresponding to the sub-area A ^T according to Pig. 3B. Points 131-135 from Pig. 4 are the UITD gate input signals. The output signal at terminal 144 is the UlTD output signal for this sub-area. Since the signals on the lines from terminals 121, 123 and 125 are logically inverted, all of these UKD input signals are a logic "1" (+). According to a typical UKD table of values, if all of the inputs are positive, the AND gate output will be positive and therefore the output on terminal 144 will be positive for an entire partial range. It should be noted that between the simultaneous

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Binary states at the inputs of the AND matrix and a single-digit number with the base m, which relates to the matrix input lines, there is a direct match. The "true" signal on a line corresponds to a digit of this number, and there are m possible "true" signals which represent m different possible bit combinations of q bits which are fed to the matrix. The manner in which these m lines are connected and the signals used in the invention are explained in connection with the transmission unit. It should also be noted that m can be less than 2 ^ because certain bit courses from 2 ^ combinations can be improbable, so that it may not be necessary to provide output lines for each of the combinations. If z. B. q = 5, the combination 00100 of a delta modulator could be an unlikely course, since such a rapid change cannot occur with band-limited speech.

To clarify the mode of operation of the matrix according to FIG. 4, Reference is made to Figure 4A which shows the connections of the diodes to the first vertical column the matrix shows. The top row of connection points is associated with a positive power supply and across Series resistors 152 are connected to a first column line 153 which runs to the output terminal 141. It it can be seen that in the absence of further connections, a positive voltage with respect to earth at the output 141 appears. The input terminals 121-125 are assigned via ITICHT members 121'-125 'and diodes 126 with the first column line 153 connected. These diodes conduct

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When a negative voltage is applied to its left side via the ITICHiE elements 121 «-125 * If one assumes that a negative input pulse is supplied to each of the input terminals 121-125, each of the diodes is consequently a positive pulse applied so that no diode conducts and as a result einpisgangssienal appears at connection 141 for the binary word 00000. Any other! Combination of input pulses, e.g., B. 01000, the occurrence prevents an output signal at the terminal 141, because in this Pail the NOT gate 122 'a negative pulse to the left side of the associated diode 126 would create, so that the Column line 153 would be grounded. It should be noted that the matrix includes all possible, or at least all desired, combinations of diode connections starting with that on the left hand side of Pig. 4 to the one on Pig's right. 4 so that any desired binary word can be used to produce an output signal or a true state on a unique output terminal.

It should be noted that both the receiving part and the transmitting part of the system according to the invention due to of signals each received from the other part works; it is therefore for the sake of simplicity first, a receiving unit explains how it can be used in the invention. Pig. 5 shows a Receiving unit with acquisition and clocking stages to receive the transmitted information from the phase-shifted To remove straps. First, it should be noted that the receiving unit has the following punctures

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has: Firstly, a reference phase for use in the transmitting unit is derived from each received carrier; Secondly, the phase angle is detected which is exceeded during each time slot in the time sub-range; and thirdly, synchronization signals are derived which are used in the receiving and in the transmitting unit. Since the circuit parts for each carrier frequency are identical, this is limited The following description refers to a carrier frequency path Coupled via a transformer 203 to a resonance amplifier 204 which has tuned oscillator circuits which are attenuated by an analog switch 206 so that oscillations which occur in one time slot do not continue into the next time slot. The analog switch 206 is controlled by a clock signal controlled, which is fed to an input 207 from a transmission unit. This clock signal, which is effective during the phase transition time interval, is generated in the transmission unit, as will be explained below. Separate resonance amplifiers and analog switches 211 are also supplied with the input signal for separate carriers, and terminals 212 are connected to them. The input signals at the connections 201-202 are also coupled via the transformer to a PLL circuit 213, the output signal of which is fed to clock signal generators 44 (cf. FIG. 2).

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The clock signals from the clock signal generators 44 occur at output terminals 214.

The output signal of the resonance amplifier 204 is fed to a PI1 circuit 216 which has a phase comparator 217, the output signal of which is passed through an RC filter 218 coupled to a voltage-regulated oscillator 219 is, the output of which is in turn fed back to the phase comparator. PLL circuits are well known and consist z. B. from a commercially available integrated circuit group such as RCA CD4046. The way of working "of PLL circuitry is also known and is therefore used not explained in detail. It should be noted, however, that the PLL circuit 216 has three outputs are that in Pig. 5 are designated as outputs 221, 222 and 223. Within the PLL circuit, the RC filter 218 time constant considerably longer than made the duration of a sub-area, typically it is more than ten sub-area durations. Consequently the output signal of the voltage controlled oscillator 219 is a square wave signal with a frequency equal to that Is carrier frequency, and with a phase which is a time average of the phase of the input signal of the PLL circuit is because phase changes that occur during a partial range have a minimal effect have on the output signal of the voltage-regulated oscillator connected to terminal 221, and as Eullgrad reference phase can be designated. The exit 221 is capacitive with an output 226 of the receiving unit coupled, with which in turn a resonance circuit 227 is connected for taking all present in the square-wave signal

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higher frequency components to form a sinusoidal carrier frequency with the reference phase, which are in the transmitter unit is forwarded.

The character of the signal appearing at output 222 is important in that this signal serves as the basis for phase detection in the remainder of the circuit. If the input signal from amplifier 204 has a leading phase compared to the reference signal at output 221, a signal appears at output 222 which is typically rectangular (logic "1"), with the leading edge appearing at the moment the input signal is Threshold value crosses in one direction, and the trailing edge appears at the moment in which the full phase of the reference signal crosses an equal threshold value. In the case of a lagging phase, the crossover roles of the two signals are reversed so that the signal with the HuIl reference phase controls the leading edge of the rectangular output signal and the input signal controls the trailing edge. The polarity of the output signal in the case of a lagging phase is opposite to that in the case of a leading phase (logic "0"). When the input signal has a zero phase, the output impedance of the phase comparator 217 is very high (typically 10 SX ), which is important with regard to the operation of coupling transistors to be explained. A signal is thus generated at output 222, the duration of which is directly proportional to the phase difference between the input signal and the reference signal of the PLL circuit. Another output signal of the PLL circuit 216 appears at the output 223 and is used to signal a phase change of the carrier to a transmitting unit. At least some specific PLL circuits, like

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also, the one mentioned above, use a plural Flip-flops, one of these flip-flops having a first logic state during the time between the receiving carrier and the output signal of the voltage-regulated Oscillator has a full phase difference and an opposite logic state to all of them Times when the recipient of the Output signal of the voltage-regulated oscillator one Has phase difference. So at the exit · 223 exists to all Times when the receive carrier is out of phase is, a first logic state, and this output pulse takes the opposite logic state during the entire time the receiver is out of phase, i.e. i.e., one different from zero degrees Has phase value. The output 223 is connected to an output 228 of the receiving unit, whose Signal is used as a control signal in the transmitter unit to keep the transmitter output signal from the zero degree reference phase can be shifted to another discrete phase value.

The phase detection of the receiver carrier in the receiver unit according to Pig. 5 is carried out by a leading phase detector 231 and a lag phase detector 232. These members are identical, and therefore only the leading phase detector 231 explains. The phase detectors count a sequence of high-frequency clock pulses, which are generated here by a PIL circuit 233, whose input is connected to the output 221 of the PLL circuit 216. This PL1 circuit 233 is of conventional design and comprises a phase comparator 234 which is fed through a high-frequency filter 236 with a voltage

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controlled oscillator 237 is coupled, which in turn is fed back to the phase comparator. In this PLL circuit, however, there is preferably between the output of the voltage-controlled oscillator and the input of the phase comparator in the frequency by (m + 2) dividing frequency divider 238 is provided so that the final output signal of the voltage-controlled oscillator is set to (m + 2) times the carrier frequency, and this output signal appears at an output 239. The output signal of the PLL circuit 233 appearing at the output 239 has a frequency which is (m + 2) times is the carrier frequency; since "m" is the number of possible discrete phase values, it can be seen that two monitoring time intervals are provided so that in every given time slot (m + 2) clock pulses are generated which are used in the phase detectors 231 and 232 will. These clock signals at the output 239 are also fed to a shift register 241, the clock signals generated at outputs 232 for use with other carrier channels. The shift register 241 is created by connecting the Reference phase signal of the output 221 of the PLL circuit 216 via a NOT element 243 to the shift register 241 reset. In this regard, it should be noted that input carrier signals at terminals 201 and 202 contain an identification of separate sub-range signals, e.g. B. by a forward shift in one Partial area and a backward shift in the following Sub-area, so that the clock signal generator 44 is reset for each sub-area.

The phase detection according to the invention comprises the implementation the duration of the square wave signal at output 222 into a

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"true" state on one of m output lines Connections 246 from Pig. 5. This "true" state represents then one of the m discrete phase values received in a given time slot. The implementation takes place here by using the square-wave signal at the output as a time-adjustable key signal for controlling a A plurality of shift registers 247 in the leading phase detector

231 and the same shift register in each partial phase detector 232, so that a sequence of high-frequency clock pulses is counted which are sent by the PLL circuit 233 whose output 239 are generated. The signal at output 222 has a level above ground potential Average value and is therefore not suitable for direct input to the input of typical digital logic circuits. In order for a suitable directly coupled interface or coupling circuit between the output 222 and the circuit parts of the phase detectors 231 and 231

232, coupling transistors 251 and 252 are provided. The transistor 251 is an npn transistor, a positive voltage is applied to its collector, while the base electrode is connected via a resistor the output terminal 222 and the emitter connected to the input of the leading phase detector 231 and across a resistor is connected to earth. In the phase comparator 217, a leading phase of These input signals are fed with a positive trend Pulse generated that turns on npn transistor 251. The transistor 252 is a pnp transistor, the emitter of which is connected to a positive voltage terminal and its collector with the input of each partial phase detector 232 is connected, so that a negative going pulse at output 222, which is the result of an input

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signals with phase lag to the phase comparator, the pnp transistor 252 turns on. In particular, is to note that neither of transistors 251 and 252 is energized when the input phase is Hull since the high impedance state of output 222 under this condition prevents such a current flow.

Since the two detectors 231 and 232 are designed to be identical and with the exception of the occurrence of input signals opposite polarity work the same, only the operation of the leading phase detector needs to be explained. The time-changeable key signal that appears at the emitter of transistor 251 is used in two ways used to open the shift register 242 so that they count the number of high-frequency clock signals, from the clock or the PIL circuit 233 during the duration of the key signal. The second function of the time-changeable key signal is is to open a TJND gate 253, one input to the clock signal terminal 239 and the other input is connected to the emitter of transistor 251 to controllably send the clock signals to the shift registers to let through. Another UED element 254 is connected in the same way to the lag phase detector 232,

The registers 247 of the phase detector 231, which are designated IT ₁ -I ¹ IV here, are connected to a plurality of read and control AND gates 256, which are shown in Pig. ' 5 are shown schematically, all connections of the third AND gate 256 'being shown. These read and control AND

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Gates 256 are blocked during alternating half cycles of the carrier frequency by a signal which appears on a blocking line 257 which is connected to the output 221 and also to the registers 247 via a NOT gate 258. The AND gates 256 are thus blocked during the time interval in which the registers count clock signals during one half cycle of the carrier frequency, and are open for reading out register contents during the following half cycle of the carrier frequency. The blocking line 257 also runs via a capacitor 255, so that an edge-triggered reset signal is fed to the registers 247 at the beginning of each counting period. In Pig. 5 is e.g. B, the upper output of IT .. the Q output, and the lower output is the ζ output. The complementary lines of successive register pairs are connected to each of S controlling AND elements, so that the register contents can be logically read out and a "true" state is generated on the output line of the corresponding controlling AND element. Let it be For example, assume that during a given time slot the radio frequency carrier has been phase shifted by an amount corresponding to three clock signal durations; It is also assumed that the carrier frequency has a duration such that eight countable periods occur in the time slot. In this example, three clock signals are counted in the first half of each high frequency period _{and stored in the shift registers PF ^, IT 2} ^{and 1} ^. At the beginning of the next period, the shift registers are reset to zero and start a new count. This process can be repeated up to eight times, once for each of the countable high frequency periods. The Q outputs of the shift registers

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FF. ,, FFp and FF, are each a logic "1", and the Q outputs of registers FF, and FF ₁ - are each a logic "0" at the end of each high frequency period counting interval. The controlling AND gate Rr. 1 is blocked because its input signal from the complement (Q) of FFp is a logic "0". In the same way, the AND gates No. 2, 4 and 5 are blocked because a "0" is present at their inputs; however, a logic "1" is present on all inputs of AND gate no. 3, whereby the only logic output signal "1" of this high frequency period is generated, which represents the aforementioned "true" state.

The output signals of the read and control AND gates are fed to a counter 259 which is programmed to generate an output pulse after a predetermined number of equal phase-shifted periods was received. This counter 259 counts a predetermined number of "true" states in a particular time slot and after this predetermined number generates a signal at an output 246, this number being count values occurs in each half cycle of the reference carrier signal so that there is a degree of interference signal immunity in the detection system is installed. The registers of the counter are also given frequency-time matrix time slot signals supplied by a clock signal generator 44 according to FIG. 2, and a terminal 260 is connected to the counter. The probability that a Glitch creates an undesirable "true" state at an output 246, is thus strong reduced.

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The receiving unit according to the invention (PiF. 5) leads the two previously explained punctures. The puncture as a regenerating amplifier is made possible by the connection the connections 246 to a transmission unit for the immediate Retransmission carried out. The second puncture the detection of phase shifts for the local subscriber is carried out by several UITD elements 261, whose Inputs are connected to the terminals 246 and supplied to those from the clock signal generator 44 strobe pulses are, as is indicated at the connection 214 ', which corresponds to the outputs of the clock signal generator 44. There are m key outputs 262 provided, and a "true" state appears at one of them, which occurs during the time slot assigned to this local subscriber is blanked. It should be noted that this frequency has further local Participants can be assigned; however, this would be a further group of output signal elements for each participant similar to those at the outputs 262 required.

The bad phase detector 232 operates in the same way like the leading phase detector, and consequently several outputs 246 are provided for it. These are more suitable Way connected with AND gates, so that at selected terminals 262 "true" states in the corresponding Time slot of a local subscriber occur.

It should be noted that the signals appearing at the outputs 246 are converted into a corresponding binary bit sequence for local participants are and will be implemented

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by a scarf tuns: after Pig. 6 reached. To the left of Pig. 6 connections 262 are provided, which are a pale number of connections in Pie :. 5 correspond. The "true" state in Siicnalform on one of the m lines connected to the terminals 262 is stored, ^ ~ ince edehnt and read out, v ^ d namely i "^ manner similar to" hot pt registers by Pi. 3. this is done here with a group of registers 266. Corresponding to that in connection with Pig. 3, the output signals of individual registers are maintained for an entire time sub-range after that in which the signal was received. The conversion of this output signal into a suitable bit sequence takes place in one of several logic levels, e.g. B, the logic linkage stage 267. A "true" output signal from the registers 266 is fed, for example, to the logic linkage stage 267 as an input signal of a UO element 268; the other input of the AND gate 267 is supplied with an output signal of an OR gate 269 of the stage. The input signals of the OR gate 269 are the positive pulses which occur in each of the q intervals which require a logic "1" level in order to reconstruct the relevant bit sequence, which is represented by the corresponding "true" state. Each of the logical linkage levels such as the level 267 of Pig. 6 is designed so that when a "true" condition occurs, a predetermined word is generated from registers 266 on the input line. So z. B. to reconstruct a pole of five logical "1" bits in a partial area, the inputs of the OR gate 269 separately with the connections 64-68 according to Pig. 3A connected. The pulse source for these connections is the clock

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Signal generator 44. For example, assume that this is in the partial range B by Pig. 3B transmitted binary word has been received and is read out as 10110. This reading takes place by the linkage logic stage 267, where a "true" state is present at the AND gate 268 and the inputs of the OR gate 269 are connected as shown in FIG are. As a result, the OR gate 269 is given a logic "1" and during the first time slot both inputs of the AND gate 268 a logic "1" supplied, so that at the output of the AND gate 268 a logic "1" occurs and thus a logic "1" appears at terminal 271. Since the second and the last Digit are a logical "0", the second and the fifth input of the OR gate 269 are connected to ground, so that a "0" is generated at terminal 271. The output of AND gate 268 is through a diode with a Output terminal 271 connected, and in the same way are the outputs of further logical "linkage levels 272, 273 etc., which are connected to separate input connections 246 via registers, with this output connection 271 connected. Each of these logical linking stages is designed in such a way that one in each case different word is reconstructed. The binary bit sequence for a specific one appears at output 271 Attendees. Further subscribers to whom other available time slots are assigned in the frequency-time matrix, have similar implementation stages as through the registers 274 is indicated, the inputs 262 'and are coupled to logic stages 276, so that for each Participants a single output 277 is fed a bit sequence.

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To explain the transmitting part of the receiving-transmitting unit 47 according to the invention, reference is now made to FIG. The connection 226 corresponds to this same connection in the receiving part after Mg, 5. This connection 226 receives the reference phase carrier, the is fed via an amplifier 302 to an analog switch 303, the output of which is via a resistor coupling is connected to an operational amplifier 304. laugh Mg. 7 is the starting point: the operational amplifier 304 resistance level with another Operational amplifier 306 connected, the output of which in turn via a transformer 307 with a balanced line forming terminals 308 and 309 is connected. Because the analog switch signals passes, the outputs 308 and 309 are thus fed to the reference phase carrier. The circuit elements between input 226 and the input of the operational amplifier 306 may be referred to as reference phase carrier circuit 311, and a like circuit 311 ' is between an input terminal 212, the one another carrier connection of Mg. 5 corresponds, and the input of the operational amplifier 306 is provided for a further carrier frequency.

With regard to the generation of phase-shifted signals for the transmission, it should be noted that these through Use of controlled C-amplifiers and oscillator circuits or by using switches and oscillator circuits. Mg. 7 shows two amplifiers 316 and 317, whose outputs are associated with Oscillator circuits 318 and 319 are connected. The bias voltages of these amplifiers 316 and

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317 are set to work as a C amplifier and thus their corresponding oscillator swing circuits trigger at the desired carrier frequency. Input signals for the amplifiers are taken from the connectors. 246 of the receiving part received and carried thus the information to be transmitted in pulse form. The pulses on terminal 246 become main flip-plops 321 stored so that the received short pulses outlast the following time slot and converted back into suitable phase shift values will. Output signals of the flip-flops 321 become UID gates 322 supplied, and each of these UCT gates has a separate one connected to one of the terminals 242 of the shift register 241 in the receiving section Entry. As a result, the UITD gates 322 receive one after the other. Clock signals at one of their inputs during each half cycle of a high frequency carrier, and when that stored in one of the flip-flops "True" state with the clock signal at one of the AND gates coincides, a key pulse is generated at a common output 324 of the AND gates 322. Of the Output 324 is with the inputs of amplifiers 316 and 317 connected. These also receive a rectangular one Clock signal with half the pulse frequency of the time sub-range, so that each amplifier alternates works in alternating time slots. The clock signals are fed to a terminal 326 which is associated with the amplifiers 316 and 317. is connected and controls them alternately, and this clock signal can be from a clock signalerz_eu /? Er according to Fig. 2 can be obtained. The purpose of this alternating operation of amplifiers 316 and

6 0 9 8 4 0/0 7 7 9

is to create enough time so that one oscillator circuit can generate oscillations with the correct phase, while the oscillations in the other oscillator circuit are dampened. The clock generator connection 326 is also connected to a selector switch 32 ^ and controls this; the selector switch is connected to the oscillator circuits 318 and 319, so that the output of the switch is switched from one to the other oscillator circuit on the basis of the clock signal. The Ausffanffssignal of the selector switch 327 is fed to an analog switch 328, the output of which is in turn resistively coupled to the input of the operational amplifier 304 in the reference phase carrier line 311 via a connection 329 of the switch. The analog switches 303 and 328 are activated by the phase change signal at the connector of Pig. 5 on and off. This connection is connected as shown in FIG. 7 via an OR gate 331 to a clock generator and pulse telephone unit 332, which generates complementary signals for controlling the switching operation of the analog switches 303 and 328. As already mentioned, this is the connection 228 in Piff. 5 is a signal that indicates a phase change, and it is then sent in the transmitting section to Piff. 7 is used to operate the clock and pulse shaping unit 332 so that the analog switch 303 is turned off and the analog switch 328 is turned on. The signal at terminal 228 is e.g. B. then a logic "0" when a phase difference begins and exists with respect to the reference phase, and becomes a logic "1" again when these phases are the same again; from it is

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It can be seen that analog switches 303 and 328 operate to connect outputs 308 and 309 to either feed the zero-phase-shifted carrier or the phase-shifted carrier.

If some of the time slots are from already existing If carriers are not occupied, signals can be localized Subscribers who have passed through pulse processing units are introduced into the transmitting section, and indeed z. B, at connections 336 »the assigned via Flip-flops 337 are connected to the circuit in the same way as terminals 246 are connected. The connection also occurs from flip-flop circuit 337, whereupon a "true" state with an Eull phase reference carrier is transferred a NOT gate 338 to an input of the OR gate 331 is directed. A time slot reset terminal 339 is also provided which is associated with each of the flip-flop circuits 321 and 337 are connected to allow any flip-flops or registers at the end of each time slot deleted or reset. The reset terminal 339 applied clock signals can e.g. B. from the clock signal generator 44 can be obtained. In general, one of a clock signal generator and a radio frequency carrier Sub-area signal ζ generated in the toll switch. Β. be used to synchronize signals through the system to each receiving-transmitting unit. Such a signal is then used to Time slot bit interval generator and pulse shaping clock generator at the appropriate times head for. Since clock circuits are known, they are not explained further here.

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It should be noted that the illustrated parts of Fig. 7 refer to a single carrier "and that of course further carriers can be introduced into the line, so that additional participants can be added can. In this regard, reference is made to the portion of Fig. 7 below and to the right of that passing through the figure Dashed line indicated.

By the other circuit parts of Fig. 7, a new high frequency carrier can either for, current or future Address assignments of up to ρ timeslots per carrier can be introduced in the frequency-time matrix. The connections 341 can be connected to m input lines, which allow the use of a local modulator pulse processor and associated flip-flops. A internally generated carrier is generated by a stable high frequency oscillator 342, the output of which is fed to a frequency divider 343 where it is divided by (m + 2); its output signal is again via an amplifier and analog switch stage 344, the corresponds to members 302 and 303, terminal 346 fed. The inputs 341 are with IMD elements 351 connected, the other inputs each with a (m + 2) Places having shift register are connected, which is operated by an AND gate, which in turn is connected to the high frequency oscillator 342 and the frequency divider 343. The output signals of the UlJD elements 351 are fed to a phase shifter 352 which, for example, can be embodied in the same way as the amplifiers 316 and 317, their associated oscillator circuits and the selector switch 327 comprehensive stage. A

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Clock terminal 353 feeds a square wave signal to the phase shifter with half the pulse frequency · of the time slots so that the output of the phase shifter applied to an analog switch 354 is actually the phase shifted Carrier is fed to an output 356 will. A clock and pulse shaping circuit 357 operates switches 344 'and 354 in the manner already explained. The terminals 346 and 356 are resistive across an operational amplifier 358 coupled to the input of the operational amplifier 306 so that its pulses to the outputs 308 and 309 forming a balanced line.

With regard to the transmitting part, it should also be noted that the analog switches 303 and 328 switch the carrier phase cause; it should be explained in which way this switchover is carried out. It is known that a ■ abrupt transition with every signal a wide frequency spectrum required for an accurate reproduction of this signal. This invention comes with bandwidth in mind such a broad frequency spectrum is not imprinted, and it is therefore desirable or even necessary, Make carrier transitions from one phase to the next as gradual as possible. A compromise is foreseen so that this gradual change is possible on the one hand, but an appropriate one in "each time slot" on the other hand Time is available so that the desired phase can be reliably detected by the receiver. To generate the waveform of the complementary signals supplied to the analog switches from the clock and pulse shaping circuits 332 A number of known methods are available for control signals, and therefore they are not

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Nä'aer explained. It is envisaged that the "two different phases of the carriers will overlap during the transition time interval, thereby reducing the bandwidth required by the system". The gate portions of overlapping pulses are shown in an article by Prabhu and Rowe entitled "Spectrum of Digital Phase Modulation by Matrix Methods", published in Bell System Technical Journal, Volume 53, p. 899 (May-June 1974), explained. The overlapping of the two different phases of the carrier is carried out by using a special clock and pulse shaping unit 332, whereby the start of the overrange control signal occurs before the start of a time slot. This unit is synchronized by a reference clock signal serving for the entire system, namely by using delay lines, clock generator multivibrators or counters which are controlled by the previous time slot. In view of this wide variety of known agents available, no further explanation is required. It should be noted, however, that partial area synchronization is required for the system according to the invention; this can easily be achieved by transmitting a pilot signal that carries the partial area timing information. A delay in the onward transmission of the partial area clock signal is provided in each receiving-transmitting unit, so that the transition overlap interval is present.

With regard to the timing of the system according to the invention, in particular the transmitter part according to Pig. 7, it should be noted that the clock pulses from the shift register 241 of Pig. 5 can be derived.

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The high frequency pulse train, which is produced by the stage 233 of Pig. 5 is generated at the terminal 239 is fed as an input pulse to the shift register 241, and this High frequency pulse train has a frequency (m + 2) times larger than that of the reference carrier and one These high-frequency pulses occur precisely at the point in time when the reference carrier crosses zero Has. It has been said that the clock signals for the transmitting section from the shift register 241 of the receiving section are generated, and the temporal relationship between the output signals of the shift register and the phase shifted carrier is controlled in such a way that each phase of the relay to be relayed The carrier in the transmitting part can be selected by using the output lines of the shift register, each of m such output lines being a direct match to a specific one associated with the carrier discrete phase value is assigned. To get the shift register output signals in the correct order trigger, the reset terminal 244 is a from terminal 221 of the PLl circuit of the receiving part incoming reset pulse supplied to the operation of the Shift register triggers so that z. B. whose first output line always carries a signal that the -180 ° - Point of the reference carrier comes closest and the Carrier to be transmitted further could be assigned as the largest leading phase value. The term (m + 2) was therefore chosen here to avoid a temporal conflict with regard to the -180 ° point and the + 180 ° point of the reference carrier. In other words, neither of these two phase values agrees with any of the m

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Phase values match. If more of these phase values were excluded from the m values, the term (m + 2) would have to be changed so that the voltage-regulated Oscillator 237 of circuit 233 would produce a different phase-locked frequency. Such excluded Values can be used for control functions or the like, e.g. B. for monitoring signals in application of the invention in the telephony field. It should be noted that any change in the number of Total phase values for the maximum number of coded representations that can be made with m combinations are to be sent, must be related, as will be explained below.

The mode of operation of the transmitter is best shown in the simplified circuit diagram according to Pig. 8 can be seen, where simple controlled switches can be used as functional units. High frequency pulses appear sequentially at terminals 323, and these pulses are generated at terminals 242 of the shift register of the receiving section. Any of the analog switches of FIG. 8 can made up of P-channel or M-channel MOS transistors or integrated Circuits exist, e.g. B. the component manufactured by RCA CD 4016, the four CMOS analog switches per unit included. The flip-flops 321 comprise JK registers, and if one of these m registers has the level "1" a train of eight high frequency pulses passes through the associated analog switch 322. Each of these pulses arrives on an associated line at each of the input holders and occurs repeatedly once per high frequency period in a temporal position that is related to a discrete phase value

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stands. To generate a "specific high frequency carrier phase shift Shifting during a certain time slot runs through the time position of the corresponding High-frequency pulse blanked by the JK-Plip-Flop 321 the corresponding inalog switch 322 to the inputs of switches 351 or 352. These Switches are switched on alternately with opposite half-phases of the high-frequency carrier for driving the oscillator circuits 318 and 319 and generating a corresponding phase-shifted sinusoidal Impulse. If z. B. the pulse at terminal 323 means the most leading phase value of m phase values and this pulse in the specific time slot is chosen, the pulse would be repeated with the high frequency carrier frequency in this most leading phase position of each carrier period occur. The switches 351 and 352 are at half the pulse frequency of the time slots are alternately controlled by a signal appearing at connection 326 which, according to Pig. 8 via the clock signal and pulse shape unit 332 is supplied, although this is not mandatory. This signal is the control switch 351 directly and the Control switch 352 is supplied via a HICHT-Glieä 353. Each oscillator circuit 318 and 319 is damped, and this is achieved by switches 354 and 356, which are connected in parallel with the oscillator circuits 318 and 319, respectively. Operation of the switch 354 is complementary to that of switch 351; H. the control signal is sent to switch 354 via the NOT gate 353 supplied, and the attenuation switch 356 is operated complementary to the switch 352 by the control

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signal is fed to the switch 356 directly. It can thus be seen that when e.g. B. the switch 351 is open, the switch 354 is closed and damps oscillations in the oscillator circuit 318, while on the other hand "with the switch 352 closed, the damping switch 356 is open so that the oscillations generated in the oscillator circuit 319 can pass through. The analog switch 328 of the transmitter includes in FIG. 8 two switches 328a and 328b operated in a complementary manner. These two switches are controlled by the square-wave clock signal at the input 326, and the clock signal can be supplied by the clock signal and pulse shaping unit 332. In the previous example with the switch closed and the attenuator switch 356 open, the selector switch 328b would be closed and the selector switch 328a would be open. In this example, the RF oscillation would be fed from the oscillator circuit 319 through the operational amplifier 304 to the output terminals 308, 309. The analog switch 303 is in Pig. 8 in the same way as in I ¹ Ig. 7, it connects the input 226 to the outputs 308, 309 and is controlled by the phase-shifted signal at the connection, either through a connection via the clock signal and pulse shaping unit 332 (see. Pig. 7) or via a direct connection to the Switch 303 via an ITICHT G song.

Pig. 8A shows waveforms from at various points in the transmitter part of Pig. 8 occurring signals; is there it can be seen that the waveform is rectangular

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HF carrier is. Note that this is a simplification in that the HP carrier is actually sinusoidal. With this simplification it is still possible to use the analog switches according to Pig. 8 instead of the amplifier according to FIG. 7 for ease of explanation. The pulses B in I ¹ Ig. 8A are the high frequency pulses sequentially applied to terminals 323, and key pulses C are applied to inputs 246 of Pig. 8 supplied. These pulse pulses are used in the manner explained above to generate a sinusoidal signal D at an output 329 of the analog switch 328.

It can be seen that the transmitting part so artleitert that during alternating time slots alternate Oscillator resonant circuits are supplied with pulse peaks, and since these oscillator resonant circuits "in the oscillate with the same HP carrier frequency, the desired phase-shifted carrier is generated. The alternating Control of these oscillator circuits enables them to be switched on and off, so that they generate sinusoidal signals in a controlled manner. Since the bandwidth of each HP carrier is determined by the type and The manner in which the control signals are shaped by the clock signal and pulse shaping circuits v / ground, the porm of these signals is also controlled. It was found that at constant Impulse energy and a controlled Q factor of the oscillator circuit form the sinusoidal signal full usable amplitude reached during the period of two HP periods and then during the

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remaining time slot constant amplitude and phase Has. Since in the illustrated embodiment of the invention no complex circuits this energy or affect the Q factor are the phase angles repeatable, typically within a degree or two. In this relationship is note that the limit of m is the number of phase shifts which can be reliably detected during each HP period. If an even more detailed Method and phase fine control were used, as is known, the value of m can still be increased, thereby increasing the information content "of each time slot without noticeably changing the bandwidth would be increased. The cost of further circuit stages can, for. B. through available income can be offset from increased information per bandwidth, which are transmitted via certain Pern transmission lines could be transferred. A more detailed phase selection is e.g. B. possible in that the HP carrier is raised to a higher frequency if the transmission medium allows it, and that also a Auxiliary carrier is introduced. Such a subcarrier can be based on a phase value from a certain number of phase values are shifted in phase to decrease in a group of time segments, and in each selected one Time interval, the HP carrier can be phase shifted to a different group of phase values, so that both a process flow and a finely tuned group of values are given, to increase the value of m, where m is again a total number of possible phase values in each time slot means. In the exemplary embodiment, m was replaced with 12

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elected, with five leading and five hacheils as well as two monitoring phases; it goes without saying that. this fourth of m is not a limitation.

The system according to the invention is used to transmit information, but the invention is the same can be used for data transmission. Data can come from a data source, e.g. B. a computer or a memory, either sequentially or in parallel. Fig. 9A shows the sequential data processing after of the invention, and FIG. 9B shows the parallel data processing according to the invention, FIG. 9A shows one Data source 401 which, at an output 402, generates a series or sequence of digital bits that are to be transmitted Represent data. The clock frequency of this digital train does not necessarily have to be the same as be the sampling frequency or the sub-range frequency according to the invention. As a result, interface buffers are 403 are provided, which can store q bits in each time sub-range of the system. the Interface buffers include flip-flops and associated logic control circuitry and are in conventional fashion constructed so that they receive information signals coming from the data supply 401 input registers 404 which correspond to the storage, time stretching and readout registers 56 of FIG. At the connection 406 is supplied with a signal having an early sampling frequency and supplied to the buffer memories 403 to reset this with this early sampling frequency. At terminal 407 a signal is fed that has a late keying frequency that is the same frequency as the early keying frequency, but long enough -

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was delayed so that all information from the buffer memory is entered in registers 4-04, before the latter are controlled and put their output signals on lines 408, which are connected to matrices 57 according to Fig. 2 are connected. The interface buffers

403 generate a "buffer ready" command signal that over the line 409 for data supply: 401 is routed. Since the clock frequency of the data supply is lower than is the clock frequency of the system, the buffer stage 403 stores the information supplied only until it is cleared by the early key pulse at 406; at this point the data supply is switched on again and transfers information to the buffer stage. On the other hand, if the clock frequency of the data supply is higher as the system clock frequency, the signal on line 409 is used to intermittently carry out the transmission lock of data to buffer level. If data is fed to the system at 408, the remainder occurs The system carries out signal processing identical to the one explained above, if a delta modulator is sequential to it Supplies data, the desired sequence occurring with the sampling frequency being present at the receiver output is. It should be noted that clock signals such as those used e.g. B. appear at terminals 62-68 of Figure 3, the registers

404 at connections 411 of Pig. 9A are supplied, and it should also be noted that when the sampling frequency of the system according to the invention is either too slow or too fast for the data sink to which the data is to be supplied a similarly designed buffer memory at the receiving end of the system would be required to store the same, but reversed puncture as the buffer stage 403 to be carried out in the transmission path.

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It is known that a data supply is either data can transmit sequentially or in parallel; Pig, 9 B shows a system according to the invention for transmitting Data from a parallel data supply 420, with each output line 421 corresponding to the bit value in the digital word present in all lines is weighted. The number of lines for one user is not necessarily restricted to q, except when the data transmission instead of the speech input data is too use is. For both sequential and parallel data processing, it should be noted that that either a modulator or the buffer memories of FIGS. 9A and 9B with an address assignment of one User per time slot can be used in the time frequency matrix, which simplifies the explanation and "understanding of the system will be facilitated. The parallel output lines 421 from the Data supply 420 are connected to the input of transmission interface buffers 422, which in turn the transmission signal processor tmd transmission part of the Invention supply signals. It should be noted that with parallel data input, the memory, time expansion and Readout register 56 according to the invention separate Require input lines for each data bit and consequently a key-in clock signal and logic gates, to enable the introduction of parallel data in each sub-area. For this purpose there are connections 423 and 424 are provided, which are connected to suitable clock signal generators, and the rest the system according to the invention processes the data

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in the same way as a modulator except at the receiver output. Instead of regenerating a serial bit sequences are parallel receiver interface buffers 426, which feed the data to a data sink 427 in a desired form.

The invention offers a great advantage for data transmission in comparison to currently common telephone data devices which transmit data over voice lines in the pass range of 200-3000 Hz. One advantage lies in a much higher bit transmission speed that is possible with the invention. In this context, consider an embodiment of the invention which uses a subscriber multiplex system (bearer system), speech information being transmitted in each channel in the above-mentioned passband. Telephone company data terminals typically transmit computer data by tones at a rate of 1.2k bits / s. In the previous example of the invention in the form of a subscriber carrier system with the interface or coupling units described, the data or bit rate is ~ Fig. _t that can be picked up in every speech channel without interference in neighboring channels]? = q. f _f , with q = number of bits or pulses per sub-area and fr. In an embodiment of the invention in which q = 4 and f ~ = 12.5 kHz, it can be seen that a transmission rate of 50k bits / s is obtained through a single speech channel. This is a major improvement over

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the speed of 1.2k bits / s that is currently possible with telephony data terminal equipment. Further "is the rate error rate as they are currently available for commercial data transfer · over the Telephone company lines "consists of 2 bits / min, which is well above the error rate of the invention. Attempts are being made at the moment from other sources to increase the possible data transmission rate, and in this regard PCM systems (pulse code modulation systems) converted for use in high speed data transmission; the However, the error rate is intolerable for most computer users, and an adjustment to this Systems at the best results will entail interference between adjacent channels, and accordingly some channels may not be used at all. A receiver in a PCM system searches the interfering signals after the single occurrence of each bit, whereas the receiver according to the invention makes the multiple event decision to select the correct data state and to reject interfering signals that occur in a smaller number of multiple events. As a result, the invention offers a great deal large part of the goal in terms of keeping errors in data transmission small.

Referring to Fig. 2, basic conversion calculators have already been presented 53 and 58 mentioned which can be used with the invention to increase the amount of information sent over the transmission medium can be. A for use in the

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Finding a suitable radix or base conversion calculator is in Pig. 10 shown. A detector 451 leads one Computer unit 452 signals to; the computer unit includes a base "m" binary conversion and working in parallel Buffer storage. A computer clock signal is fed to the computer unit at connection 453, and that The output signal of the computer unit is sent to an instruction unit 454 and an arithmetic unit and accumulator stage 456 supplied. The instruction unit 454 is connected to a read-only memory 457, which is that of the basic conversion computer used program stores, and the instruction unit is also with the arithmetic unit and Aldcumulator stage 456 as well as with a processing unit 458 connected. The command unit receives a signal to execute the first program step and queries the pest value memory 457 to receive a command for this step, the arithmetic unit and Accumulator stage 456 and the processing unit is fed. The processing unit is identified the step as carried out, and the result is fed to a buffer 459. The output signal of the buffer memory 459 is fed to a computer output unit 461, which also has transmission clock signals at connection 462 receives. The computer output unit is equipped with a transmitter unit 463 connected as they are in the Pig. 7 or 8 is shown.

Pig's basic conversion calculator. 10 uses two storage units, the plague value storage unit being used to Permanently store processing commands that are required to control the computer, so that this performs the basic conversion using arithmetic operations.

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The buffer is used to store partial solutions that are obtained from the various conversion steps. These stored partial solutions are first written into the intermediate memory and then transferred to the outside, the memory being erased and further input values being able to be received. In this way it is avoided that expensive storage units such as core memory or the like are required.

It has already been explained with reference to Pig, 1 and 3 that the purpose of the basic conversion calculator that is to ensure that, if necessary, more participants can be combined in the system without that there is a performance degradation and a substantial increase in the required bandwidth. When the system has accepted the maximum number of participants using the base "m" Can be served, it is by converting to a higher base "R", the R different phase values needed, possible, in the same frequency-time matrix to transmit more information. At the reception entrance, e.g. B. at the receiver of a telephone exchange of a telephone system, would be an inverse conversion of R required to m. In the transmission direction, the conversion to a higher basis takes place in that the Input unit the base m-digit places of UED matrices according to Pig. 4, with intermediate storage of these digits in Buffer storage enables the computer to then use the computer clock frequency to digitize the digits "calls". After converting to a higher

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Base done by the calculator will be the end result stored in the output unit and from the transmitter part of the system with the normal subrange frequency used. The solution steps to be carried out are explained below; however, since the ]? union units according to the remaining Units of the calculator that are in Pig. 10 are known as blocks, they are not grounded here explained in more detail. The reverse operation is essentially carried out in the receiving section.

To reduce the number of program steps and thus to simplify the calculator, it is very desirable to to choose a base m and a base R which are related by a power factor of 2 stand. The following equations illustrate the solution steps necessary for a ratio of two between R and m can be programmed into the computer. First the number equation for a Number given according to the ordered digits for the base m and the base R:

= BR ⁰ + D ₁ R ¹ + D ₀ R ² + DR ⁵ + ... D in the base R

Ol <L J

Y. = dm ⁰ + d, m + d _o m + d ~ m + ... d in the base m m ο ι α ο

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TJ

Conversion -to. o "ben (from m" to R) with τη = τ-ζ

^d 2 2

Conversion downwards (from R to m):

¹ + D (2m) ² + D (2m) ³

= D _n (2m) ° + D ₁ (2m) ¹ + D ₉ (2m) ² + D, (2m) ³ +

. 1 + 2D ^ ¹ + 2 ² D ₂ m ² + 2 ³ D, m ⁵ +

Example:

1 1 4 4 2 r- convert based on

> / ⁵

- ' ι

/ ' 1 * "' - 2 5 4
N _c = 2 + 4 * 5 + * 4 * 5 + 1 * 5 + 1 * 5

2 + 4 · 1O _1n + ^ y · 100 + -τ? 1000 + Ij. 10000 ^ tu ₂ <! ₂ ^

2 + 20 + 100 + 125 + 625 = 872 _1Q . 6098A0 / 0779

The reverse conversion is as follows:

872 ₁₀ = 2 + 7 * 10 + 8-100

= 2 + 14--5 ¹ + 32 5 ² (base 10) = 2 + 24 10 ₅ + 112 1ΟΟ ₅ (base 5)

2 + 24-0 + 11200 = 11442 ₅ .

It can be seen that the information transmission system explained above uses a frequency-time matrix in such a way that a substantial portion of the goal is reached. By using phase-shifted HP-carriers each hole of the matrix carries more information than would be possible if only KP signals would be used. In this regard, it is of interest to consider certain significant factors that affect the way the system works. The first of these factors is the number of participants that can be accommodated by a particular frequency-time matrix. The size of the matrix is expressed by the number of holes in it, represented by the character H, which is equal to the product of the number of separate HP carriers and the number of time slots in the time sub-domain. If the number of participants is indicated by the character S, then the relationship between H and S is as follows:

^log

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From this relationship it can be seen that when R> m made the number of participants larger than the number of matrix holes can be. The maximum value of R for a given system is governed by the shortest time interval T, which can be processed by the circuit in the phase shift detector as well as the highest used in the system Carrier frequency f, as the following equation shows:

R + 1 ^.
^{1 1} cm

In the above equation, 1 becomes R for the reason given in the explanation of the phase separation detector added, namely to create monitoring intervals at the beginning and at the end of a carrier period.

A second factor is the need for the basic conversion process to keep it as simple as possible. Since the arithmetic operations are normally carried out by implementing all If numerical values were to be made into binary values, it would be advantageous to use both the base m and the base R as To have power factors 2. If R = 2m then the size is

the factor by which S is greater than H, and also shows that m should be kept as small as possible, um get the most benefit from the base conversion.

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A third factor is the smallest number of strobe pulses from a phase-shifted carrier which can be reliably detected by the high-speed digital phase detector which was explained in connection with FIG. The presence of glitches on the phase shifted carrier results in spurious coincidence pulses being applied to some of the counters. In order to prevent the pulses from being saved as "true" values of the detected phase shift, it is desirable that as many correct coincidence pulses as possible are fed to the appropriate counter. The worst situation arises at the lowest carrier frequency f _c1 , at which the number of correct pulses is smallest, since the number of signal periods is smallest. If j is the smallest number of correct detector outputs that must be received in order to reduce detector errors to an acceptable level, then the lowest carrier frequency to use is as follows:

f _c1

with ρ = number of time slots in a time sub-range, g = ratio of time slot to phase detection interval and
f "= subrange frequency.

Above, a preferred embodiment of an information transmission system has been explained, which in time and Phase shift multiplexing works and the

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Improved performance of Überraffun.pssystemen in such a way that that a limited bandwidth by a transmission medium Höehstmenee is transferable to information. The invention is both in the general field of voice communication by telephone as well as for data overtraining at extremely high speeds or high bit rates is very beneficial.

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Claims (5)

Claims ^ l Preqnenz-Zeit-Multiplex-ÜberraininFssystem, F eke ν. ν v, calibrate η et by el · "en s he who receives su via he met de input signals and a unit for the formation of successive time sub-ranges, with the input signal being scanned several times in each of these time sub-ranges to generate a binary pulse signal for each sub-area, as well as a phase shifting unit which can be controlled by the binary pulse train to phase shift a carrier signal in each sub-area in accordance with the sub-area information; a transmission connected to the output of the transmitter d ium; and a recipient who is familiar with the transmission medium is connected and a unit for detecting the phase shift of the carrier and for counting the number of phase-shifted carrier periods in each sub-area for identification only Phase shift information when counting one predetermined number of phase-shifted periods per sub-range, so that interference signal errors are minimized and a unit for the reconstruction of the transmitter from the phase shift in FS information included input value. 2. ÜberraiTuncrssystem according to claim 1, wherein the The input signal is an analog signal, characterized in that that the transmitter has two oscillator 609840/0779 Oscillating circuits (318, 319) which oscillate at the frequency of a carrier, units (316, 317) for alternating Control of the oscillator circuits (318, 319) by additional: contained in the binary pulse Information and thus for the alternating generation of phase-shifted carrier signals and switching stages (303, 328), which the phase-shifted carrier signals alternately to the transmission medium respectively. 3. Transmission system according to claim 1, characterized in e-e, that the recipient has: a PLL circuit (216) derived from the transmission medium Receives signals and the signals supplied from it original out-of-phase carrier for retransmission generated, a leading phase detector (231) and a low phase detector (232) with registers (247) and logic elements (256) for detecting those shifted with leading and trailing phase Input carriers, counters with registers (247) and the logic gates (256) are connected and the number of phase-shifted carrier periods per unit of time count, and logic switching stages which are connected to the counters and to a clock signal generator (44) and reconstruct the binary pulse train. 4. Transmission system according to claim 3 »characterized by a demodulator receiving the binary pulse train, the an analog signal is generated from it. 5. Transmission system according to claim 1, characterized in that the receiver comprises: with a clock signal 609840/0779 generator (44) connected input registers (404), interface buffers (403) which are connected to the input registers (404) and to a data source (401) for generating a digital bit sequence can be connected, elements (406, 407) which enter the buffer memories (403) for their deletion early key control signal and the input registers (404) with respect to the early tactile control signal, supply the late tactile control signal with a slight delay, whereby this Storage of the buffer memory information in them can be deleted. 609840/0779