DE2606028A1 - Automatic dialling unit for adding to conventional telephone - has coded number memory and reset to allow repeated dialling - Google Patents

Abstract

The automatic dialling circuit can be added to a conventional telephone apparatus and has a buffer memory to retain code words corresponding to telephone numbers. Each word comprises several bytes representing the call number digits. The memory words are converted into dialling pulses when receiving the word bytes sequentially from the memory. An output pulse generator opens and closes the circuit and is controlled by the dialling pulses. A current monitor monitors the current flowing in the a-and b-wires when the handset is raised. The monitor reacts the circuit that couples the memory output to the converter, when the handset is replaced, so that the code word can be repeated immediately once the cradle switch has been depressed.

Description

Automatic dialing add-on for a conventional telephone

The invention relates to an automatic dial option for conventional rotary dial telephones.

For years there has been a need for an apparatus that can provide the Decreases the work of dialing all digits of a desired telephone number. This Requests are becoming more and more urgent as the telephone service spreads a very long chain of digits is necessary for normal dialing of a partner is.

For example, if you choose one from a big city in our country Partner in another big city, you dial with the first digit on long distance dialing and with the second digit a long-distance electoral district. The next two or three digits identify a sub-district of the selected city is equivalent to. The following six or seven consecutive ones Finally, digits correspond to the desired telephone number. This can be total result in twelve digits.

There are already devices for automatically dialing digits a phone number. One recently published in U.S. Patent 3,670,111, with semiconductors working device automatically ejects all digits one in sequence from a saved group of phone numbers selected when calling a presses certain button on a keyboard.

This known device uses instead of dial pulses Sounds of different frequencies to identify the digits.

However, there are numerous telephone exchanges that do not provide the necessary technical equipment for processing multi-frequency tones are equipped. In order to the device cannot be used in the area of such telephone exchanges.

In addition, this recently published device as an add-on is neither intended nor suitable for a normal telephone device. Rather, acts This is a replacement device, the only housing of which is both the semi-conductor automatic circuit as well as the telephone elements including the handset.

Such an integral replacement device is convenient, but expensive, because the existing conventional telephone becomes obsolete. Well there is a big one Number of conventional Telephone sets in operation, so that there is a need for an additional device that connects to the dial telephone set can connect and take over the automatic dialing work. There are already many such accessories have been proposed, but they all have various disadvantages.

To simplify the installation of such an additional device is It is desirable to have as few wire connections as possible between the additional device and the rotary telephone to have. The external connection is available via the dial telephone only two wires are available, which are referred to as a and b wires. These two Wires transmit the signals from a telephone via numerous exchange facilities on the other hand, in contrast to this, you need additional dialing devices in the case of known additional dialing devices numerous electrical connections between the telephone and dialing add-on. So needed For example, the accessory device known from US Pat. No. 3,670,111 includes a hook switch wire between the hook switch of the phone and the control section of the automatic Selector circuit.

The installation of the dial-up option is made possible by the necessary connection a hook switch wire to the optional accessory complicated. On the other hand, it is desirable control certain automatic dialing functions via the hook switch. One of these Functions is an automatic dial closing function, because it is used in the case of a manually incorrectly dialed number by pressing the fork switch the erroneously can terminate the dialed number manually. The previously proposed additional devices did not have this function. This is because the listener is recorded and If you mistakenly pressed the wrong participant button on the keyboard, you have to go to in any case wait until all the impulses from the wrong telephone number have gone out, until you can dial the right number.

This disadvantage is particularly serious with regard to additional devices for conventional rotary dial telephones, because their signal pulse sequence is considerable is lower than that of the push-button multi-frequency tone telephones.

The known additional dialing devices have another disadvantage, which is even more serious with regard to the additional relationship to the rotary dial telephone is.

This disadvantage resides in those generated by the output pulse circuit Noise. In operation, the known additional dialing devices are very annoying loud clicks when they generate dial pulses.

The object of the invention is to avoid the disadvantages listed an improved automatic dialing add-on for conventional telephones create.

According to the invention, this object is achieved by a repertoire memory for storing several coded data words each corresponding to a telephone number, each of which contains several bytes, each of which in turn contains one the first to the last decimal digit of the telephone number is coded accordingly is; a keyboard for creating selection signals to identify a selected data word in the repertoire memory; a converter circuit with a Output for receiving coupled data bytes and an output for creation of digit time impulses during operation dependent on from data bytes reception; a resettable sequential circuit for sequential coupling the data bytes of a selected data word to the input of the converter circuit; a controllable output pulse generator for setting up and interrupting a series circuit path; a circuit dependent on the time pulses for controlling the output pulse generator; a current sensing device; one the current sensing device, the output pulse generator and device tandemly connecting the telephone set so that the via the When the handset is removed, the tip and ring wires also flow through the series circuit path and the current sensing device flows; one to that by the current sensing device Device responsive to flowing current for generating a logical fork status signal to detect whether the handset is on the cradle or not; and a circuit for coupling the logical fork status signal to reset the sequential circuit, when an open fork condition is recognized, so that a data word can be re-selected essentially immediately after the telephone hook switch is depressed can be triggered.

The selection additive according to the invention enables the automation of the Dialing process with convenient installation, as can also be seen from the following Description of an embodiment can be found.

In a further development of the invention, the additional selection can also be the previously Suppress any annoying clicking noises that occur. This preferably includes one logic circuit for generating a logical converter status signal to detect whether the converter circuit generates time pulses, and one of the logical Converter status signal-dependent circuit for attenuating the background noises that result from the establishment and interruption of the series circuit path in the output pulse normally generated. A capacitor, one relay and one the relay when recognized by the logical converter status signal, that the converter circuit works, include exciting relay driver circuit. Furthermore, the relay can have switch contacts for connecting the capacitor in series with the tip or ring wire and to short-circuit the output pulse in the dropped out Have relay status.

This effectively suppresses acoustic noise.

The following is a preferred embodiment of the invention explained in more detail with reference to a drawing. 1 shows an overall block diagram the dialing add-on including its connections to a conventional rotary dial telephone, 2 shows a circuit diagram of a preferred exemplary embodiment for an area 10a from the block diagram of FIG. 1, and FIG. 3A shows a block diagram with details and 3B to an area 10b of the block diagram of FIG. 1.

According to FIG. 1, the selection add-on 10 is via one of a-wire 11 and b-wire 12 existing pair of wires connected to a conventional dial telephone 13, which in turn via an a-wire 14 and b-wire 15 via exchange facilities with a remote one Telephone is connectable. In the preferred embodiment, the two are b-wires 12 and 15 are directly connected and are hereinafter referred to as the ring line.

The additional selection 10 is in operation via a power cord to the AC power supply connected and thus receives power for its internal digital circuitry.

A keyboard 16 of the additional selection 10 contains, for example, a total of thirty-two subscriber selection buttons, which are not shown individually here. If one of these selection buttons is pressed manually, the repertoire memory 17 gives in a conventional manner from digit dialing pulses. Corresponding to thirty-two subscriber selection buttons In the present exemplary embodiment, the repertoire memory 17 contains storage locations for thirty-two different phone numbers. Assume the first of these Thirty-two dial buttons corresponds to the phone number 795-5843. After pressing this The selection button is the repertoire memory 17 according to the regulations of the telephone company e.g. seven clock pulses with a certain pulse train (usually 10 pps) which form the first digit of the telephone number. According to the regulations the telephone company is then followed by an interval of, for example, 640 milliseconds (ms), which are then followed by nine clock pulses for the second digit. The remaining Numbers follow accordingly with pauses in between.

The clock pulses go to one input of a gate circuit, whose second entrance as a special feature of Repertoire memory 17 a Receives damping trigger signal. The latter is a logical signal and provides information about the operating state of a repertoire memory 17 belonging to and below explained converter circuit. One called an interrupter command signal The output of the gate circuit 18 goes to a driver circuit 19. A set Control of the driver circuit 19 operating output pulses 20 is used for production and interruption of a series connection path between the a wires 11 and 14.

A special feature of the selection add-on 10 is a current sensing circuit 21 connected in tandem with the output pulse 20 and the telephone 13. Usually the office or its central battery supplies a voltage that can be used when the Handset via the a and b wires through a line path within the telephone 13 flows and is sampled by the current sensing circuit 21 connected in series therewith will. The scanning circuit 21 preferably includes an optical coupler 22 (Fig. 2) to control a low-pass filter 23, the output of which is a hook switch status signal (HSS) to the repertoire memory 17 delivers. As will be explained below, this HSS signal used to reset a sequence circuit in the repertoire memory 17. If the user accidentally presses the wrong dial button, he can use the automatic Pulse output of the wrongly dialed telephone number simply by pressing it down interrupt the hook switch, the sequential circuit being reset by the HSS signal will. The attenuation trip signal also goes to a relay driver circuit 24.

As mentioned briefly above, the attenuation trigger signal is a Logical signal providing information about the operating state of the repertoire memory 17. In state 1 of this signal, the driver circuit 24 energizes a relay coil 25 of a with relay contacts 26 provided relays'. In the logic state 0 of the damping trigger signal the relay contacts 26 of the, which are designed as normally closed contacts, now close in the rest state located relay 'a short circuit pad parallel to the output pulse 20. At When the relay is energized, the relay contacts 26 connect a damping capacitance between them a-wire 11 and ring line. This damping capacity preferably consists of two tantalum capacitors 27a and 27b connected in series.

In the area 10a of the additional option 10, shown in wi. 1 is as transient protection a varistor 28 connected between a wire 14 and ring line.

An optical coupling diode 29 belonging to the current sensing circuit 21 lights up when current flows through a phototransistor 30 belonging to the low-pass filter 23 and controls accordingly. The coupling diode 29 is connected with a series resistance between the tip line 14 and a node 31, and for protection against overvoltage is the coupling diode 29 is also bridged by two diodes 32 and 33, while one is connected in parallel further diode 34 limits the maximum counter voltage.

In normal telephone operation there is about a voltage on the a-wire 14 of 50 volts across the ring line. When you pick up the handset a fork switch is closed by the lifting fork, and the internal current path between a wire 11 and ring line is made. That means a complete circuit branch from the tip 14 via the current sensing circuit 21, the relay contacts 26, a-wire 11, the internal telephone circuit to the ring line. In this case, current also flows through the coupling diode 29, so that the phototransistor 30 turns on.

When the transistor 30 is switched on, capacitors 35 and 36 charged, and thereby a transistor 37 is turned on, at its Collector the mentioned HSS signal is defined. In the switched-through state of Transistor 37 has the HSS signal a voltage level of about -5 volts, what corresponds to the logic state 0. When the collector level is at 0 volts, corresponds to this corresponds to the logic state 1. The HSS signal thus has the state 1 when the fork switch is down, and the state 0 when the hook switch is up.

A transistor 38 belonging to the output pulse 20 is controlled in such a way that that there is a series circuit path between node 31 and a wire 11 either establishes or interrupts. The emitter of transistor 38 is on the tip line 11, and the collector connected to node 31 via a resistor.

In the "production" state, relay contacts 39 close, so that the base current can flow and the transistor 38 can turn on. Are the relay contacts 39 against it open, no base current flows and the transistor 38 blocks, so that the series current path is interrupted. To protect the transistor 38 against transients and other voltage peaks is a smoothing filter 40 in parallel with the relay contacts 39 and a two les smoothing filter 41 between collector and emitter of transistor 38. Furthermore, a diode 42 between node 31 and a-wire 11 limits the possible reverse voltage at transistor 38.

The switching and interrupting operation of the output pulse 20 leads to cyclical changes of the current flowing through the current sensing circuit 21 Current, so that the coupling phototransistor 30 in the pulse train of the digit dialing pulses turns on and off. As a result of the filter effect of the capacitors 35 and 36 remains however transistor 37 is turned on as long as the telephone fork switch is not is depressed.

The driver circuit 19 includes a conventional two-stage transistor driver circuit for exciting a relay coil 43. The driver circuit 19 receives an interrupter command signal (BCS) from gate 18 designed as a NAND gate. In state 1 of the BCS signal the two-stage driver circuit of the relay coil 43 does not supply any current, the relay contacts 39 are thus open and transistor 38 is blocked. The gate circuit 18 speaks on to the attenuation trigger signal and that supplied by the repertoire memory 17 Clock pulses.

The attenuation trip signal also goes to the relay driver circuit 24, where a two stage transistor driver circuit energizes relay coil 25 when that Attenuation trigger signal has the logic state 1, and vice versa accordingly.

Fig. 3A shows inter alia. a sequence circuit 44 as part of the repertoire memory 17. A conventional clock pulse source 45 generates a clock pulse train CP-O.

In the present exemplary embodiment, the pulse sequence is 25,600 pps. Furthermore, a complementary clock pulse chain Cp-180 with the same pulse sequence, but generated out of phase by 1800 to the other clock pulse train CP-O. By these clock pulse trains become conventional digital circuits described later such as J-K flip-flops and the like. Such a conventional one J-K flip-flop is, for example, flip-flop 47; this type of flip-flop has a clock input, a J input, a K input, a set input S, a reset input R and two output ports Q and QP.

For clocked operation, the two inputs S and R have the status 0 supplied. Clocked operation is characterized by positive edge triggering, i.e., state 1 is present at the J input and state O is present at the K input and arrives the clock input a positive edge or a signal state change from 0 to 1, then this flip-flop responds in the following way: If it was in the reset state, so it is retriggered in the set state. However, the flip-flop was in the reset state, it remains there, so that in each case is then in the set state. In the set state, the signal is at the output Q = 1 and the signal at the other output QP = O. With signal state 1 at input K and state O at input J with a simultaneous positive edge is the Flip-flop in the reset state immediately afterwards. Im reset State of the flip-flop, the signal states at output Q = 0 and at output QP = 1 at both inputs J and K signal state 1 at the time of a positive edge, then the flip-flop changes its state to the opposite, regardless of the state previously existed. If both inputs J and K have signal state 0 at the same time positive edge, then the flip-flop does not change its state.

In direct set and reverse operation, a signal has 1 at the input S to set the flip-flop and a signal 1 at input R to reset the flip-flop. Thus, the status of the flip-flop can also be at a point in time between positive Change flanks.

In a conventional repertoire memory 50 there are several data words are stored, each of which is encoded according to a particular telephone number is.

Each data word contains several data bytes, each data byte in the data word is coded according to a digit of the telephone number. The writing of the data words in the repertoire memory 50 takes place conventionally, does not belong to the actual Operation of the special elements of the dial add-on 10 and therefore does not need any further details to be explained.

In the present embodiment, the contains as recirculating Repertoire memory 50 2048 formed by shift registers, not shown individually Storage locations for storing 2048 bits. When creating the clock pulse chain CP-O to the repertoire memory 50 moves the bits from memory to memory pushed, the last of which into an output signal line 52 flows out. Corresponding to the recirculating mode of operation of the repertoire memory 50 the memory output signal appearing on output signal line 52 is on Time division multiplexed signal. With 2048 stored bits and a clock frequency of 25.6 kHz, the total recirculation or multiplex period is 80 ms. The multiplex period comprises thirty-two frame intervals of 2.5 msec duration each, during each frame interval the memory output signal sequentially forms sixty-four forming a data word Bits that each represent one of thirty-two phone numbers stored in memory correspond. The sixty-four bits of each telephone number are in sixteen bytes divided into four bits each. The one for the sequential formation of the four bits of a Byte required time is 156.25 microseconds (cis).

In the case of CP-O, a memory address counter 53 is clocked, consisting of three sections: a frame counter 54, a byte counter 55 and a bit counter 56. The frame counter 54 is a five-stage counter and counts thirty-two cyclically different states FS-O to FS-31 through. Preferably the frame payer contains 54 shows a conventional decoding circuit for generating thirty-two different ones Signals that all equal 1 when the frame counter 44 is in a particular its thirty-two states. For example, the signal FS-O = 1 for every 2.5 ms interval while the frame counter is in the FS-O state. The byte counter 54 is a four-stage counter and counts through sixteen cyclically different states from DS-O to DS-15. Furthermore, it is preferably a conventional one Decoding circuit available, similar to frame counter 54. This decoding circuit generates signals DSO, DS1 and DS15 to identify the specific intervals in which the byte counter 55 is in the states DS-O, DS-1 and DS-15 is located. The bit counter 56 is a two-stage counter and counts cyclically through four different states B-O to B-3. Besides, it's a conventional one Decoder circuit included. A signal generated by this decoding circuit BO equals 1 for every interval that bit counter 56 is in state B-O. In total, as stated, the memory address counter 53 has 2048 different states corresponding to 2048 different bits stored in the repertoire memory 50, and the memory address counter 53 counts cyclically in synchronism with the cyclic shift process of the memory 50 through its states. As a result, the memory address counter 53 remains up to date which bit of which byte of which data word is currently on Signal line 52 is present.

For example, if the least significant bit is changed from the least significant Byte of the data word is generated, then the byte counter 55 is in the DS-O state (Signal DSO = 1) and the bit counter 56 in the state B-O (signal BO = 1).

An AND gate 57-0 generates a selection signal SS-O which indicates the state 1 if the frame counter 54 is in the FS-O state and the byte counter is at the same time 55 are in the DS-1 state. An AND gate 57-31 generates a selection signal SS-31, which corresponds to the state 1 if at the same time the frame counter 54 is in State FS-31 and the byte counter 55 are in state DS-1. Although not separately shown, there are thirty more AND gates 57-1 to 57-30 for generating Selection signals SS-1 to SS-30.

The overall term for the Boolean function of these gates is: SS-i = DS1 x FSi.

In the preferred embodiment, the keyboard includes 16 as stated thirty-two participant dial buttons.

In Fig. 3A only the switches 16-0 and 16-31 are shown, while the rest of the intervening switches are indicated by a broken line be represented. Each of these switches closes when the associated button is pressed Selector button and opens when idle.

For example, if switch 16-0 is closed, the selection signal goes SS-O to the J input of flip-flop 47.

Accordingly, for a period of 156.25 ßs during each Recirculation period of 2.5 ms when the switch is closed is that applied to the J input Signal = 1, and CP-O serves as a positive edge trigger for flip-flop 47 in its set state. Among other things, flip-flop 47 has a locking function to prevent that the telephone number is erroneously re-dialed while the Dial pulses go out. Flip-flop 47 also provides a status statement of the function by sending the attenuation trip signal to the relay driver circuit 24 of Fig. 1 gives up.

A conventional D-type flip-flop 58 receives the attenuation trigger signal its D input and is positively edge triggered every time the byte counter 55 State DS-O assumes. A D-type flip-flop has the peculiarity that its Q output whatever its D input was at the time of triggering. Short said, a D-type flip-flop copies its input. One input of an AND gate 59 is connected to the QP output of flip-flop 58 and the other input takes the attenuation trigger signal on.

AND flip-flop 59 generates a get command signal which is 1 in the period between setting flip-flop 47 and copying flip-flop 58.

The receive command signal is sent as a trigger signal to a receive register 60 supplied, which contains five not individually shown D-type flip-flops, the are connected to corresponding stages of the frame counter 54. Dependent on from positive fan triggering, the five D-type flip-flops copy from register 60 corresponding levels of the frame counter 54. The five in the receipt register 60 as Result of the copying process stored bits form a received frame address, which identify the data word selected by pressing the particular dial key. To common code expressions used in describing memory address operations belongs the phrase "point". For example, it is said to be the shift register 60 "points to a dialed telephone number". That is, the one stored in the receipt register 60 The received frame address identifies the data word in the repertoire memory 50, which corresponds to the telephone number selected by pressing the dial button.

Now to select a telephone number from the repertoire: When closing e.g. switch 16-0 sets flip-flop 47 during the interval in which counter 54 is in the SS-O state. It is in this state each of the five stages of the frame counter 54 in the reset state (00000). That Receive command signal positively edge triggers receive register 60 while the frame counter 54 is still in the FS-O state located, and thereby each of the five flip-flops in receive register 60 will be in its reset state retriggered (00000). In this case, the received frame address is called SRS-O identified. If switch 16-31 is closed instead of switch 16-0, then it would be Flip-flop 47 is also set, but during the interval in which the frame counter is 54 is in the FS-31 state.

Each of the five stages is in this frame counter state in the set state (11111). The receive command signal becomes the receive register again 60 positive edge triggering before the frame counter 54 changes its state, see above that in this case each of the five flip-flops of the receipt register 60 in its set State (11111) is triggered. The frame address received in this case is identified as SRS-31.

In general one can say for this process that the closing of a Switches 16-i to copy the frame counter 54 through the receipt register 60, while frame counter 54 is in state FS-i, and the general expression for the received frame address is SRS-i.

A comparison circuit 61 continuously compares the states of the Frame counter 54 and receipt register 60, and generates a selected Plort timing signal SWT, Is that = if the states are the same. This occurs during the chosen one Data word or telephone number corresponding frame time during each recirculation period or if frame counter 54 and receipt register 60 are on the same telephone number demonstrate. A proven comparison circuit 61 contains five exclusive OR gates and a NOR gate (not shown separately).

A similar comparison circuit 62 is used for continuous comparison the states of the byte counter 55 and a four-stage digit selection counter 63 and for generating a selected digit time signal SDT, which = 1 if the States are the same.

An OR gate 64 passes the get command signal to a reset input of the selection counter 63 to trigger a reset state in which it points to the first digit of a telephone number. The selection counter 63 has an up input C / U to which a REP signal is applied. Any positive Edge of the REP signal leads to an upward counting at the selection counter 63, so that this now points to the next digit of a telephone number. Preferably contains-the Selection counter 63 a conventional decoding circuit for generating a signal DCZ and a signal DCNZ, the former of which = 1 when the selection counter saves the value 0000 and the second = 1 if the selection counter deviates from it Saves values.

The REP signal is generated by a J-K flip-flop 65, whose J input the BO signal from the bit counter 56 receives.

An AND gate 66 with four inputs is connected to the K input on the output side of flip-flop 65 and having an input to the Q terminal of a J-K flip-flop 67 connected.

The other three inputs of AND gate 66 are used to receive the SWT, SDT or BO signals. For positive edge triggering of flip-flops 65 serves the complementary clock pulse train CP-180. A read trigger signal is output at the Q output RE created.

Flip-flop 67 receives the same get command signal.

on its J input via an OR gate 68, on its K input the RE signal and is positively edge-triggered by the clock pulse train CP-O.

An AND gate 69 receives the RE signal and the clock pulse train CP-O and, while RE signal = 1, responds to the pulses from CP-O with generation of read pulses, which are sent as shift pulses to a Shift register 70 go. Every time shift register 70 receives a read pulse, it has pushed in the bit which is then defined by the memory output signal will.

Now about the function of reading the first byte of a data word from Repertoire memory 50 based on the receive command signal w is the receive command signal = 1, the digit selection counter 63 is reset and the receipt register 60 is copied frame counter 54 to point to the telephone number dialed. With the following positive edge of CP-O after the receive signal has become = 1, the flip-flop becomes 67 triggered in its set state. This occurs while the byte counter is on 55 is in the DS-1 state. Thus at this point in time the SDT signal will be = 0, because the state of byte counter 55 (i.e. 00001) differs from the state of the selection counter 63 (which is 00000) differs. The memory address counter 53 then runs through a sequence for a period of time until three conditions are met: First is the state of the frame counter 54 again equals the state of the receipt register 60 (i.e. SWT = 1); second, the state of the byte counter 55 is the same as the state of the Select counter 63 (i.e. SDT = 1); and third is located itself counter 56 in the B-O state. Now the output of AND gate 66 = 1, so that flip-flop 65 from the next positive edge of the next occurring pulse from CP-180 can be reset. Resetting flip-flop 65 results in the signal RE = 1, and it will remain so until the next positive edge from CP-180 occurs, after BO = 1 again. Flip-flop 65 is now set again, and this leads to a positive edge in the REP signal. This in turn becomes the digit selection counter 63 caused to count up.

While the RE signal is in state 1, flip-flop becomes 67 triggered in its reset state because the RE signal to the K input of Flip-flop 67 is fed back. As explained below, flip-flop becomes 67 triggered again in its set state when after the pause between the digits a read command signal becomes = 1 again.

While the RE signal is in state 1, four consecutive Pulses from CP-O passed through to shift register 70 as shift pulses. Consequently becomes a four-bit byte representing the first digit of the dialed telephone number shifted into shift register 70 due to the receive command.

The sequential reading of the remaining bytes of a selected data word from the repertoire memory 50 takes place in a similar manner, of course of the following read commands. Shows during this sequential read the receipt register 60 permanently on the dialed telephone numbers. On the other hand, he shows Digit selection counter 63 gradually from the first to the last Digit this phone number.

3B shows the interconnections of shift register 70 with others Circuits which have the function, among other things, of each received from the shift register 70 and data word stored therein in parallel bit format in digit dialing clock pulses to shape.

A clock pulse counter 71 constructed in four stages (not shown) has an up input and a reset input. Via an AND gate 72 gate pulses reach the up input of counter 71 in a ten pps cycle Control of a pulse trigger signal.

The ten pps pulses thus supplied are suitably from a by-ten partial counter (not shown) obtained by one of the second of the five flip-flops of the frame counter 50 clocked 100 pps square wave signal is clocked. The pulses from AND gate 72 are the clock pulses that go to gate circuit 18 of FIG.

A comparison circuit 73 compares the count or state of the Counter 71 with the byte or status of shift register 70, and if they are equal the signal generated and labeled "Conversion Complete" (CC) = 1. In this context, consider an example in which byte 0001 is in the Shift register 70 is inserted. In this case, the counter 71 becomes after generation of a clock pulse also store 0001, so that the CC signal = 1 will be. As another example, assume that byte 1010 is in shift register 70 has been inserted, which is the binary value for the decimal number 10. According to the custom of telecommunications correspond ten pulses of the number O. In this case, after Generation of the ten clock pulses of the counter 71 also store 1010 and the CC signal becomes = 1 again.

Between the comparison circuit 73 and that by the positive edge the REP signal triggered J input of flip-flop 75 is an inverter 74. Man will remember that the positive edge of the REP signal occurs after assertion the fourth of the shift pulses associated with entering a data byte into shift register 70 into this shift register 70. If the byte inserted = 0000, then the CC signal immediately 0. This only-0 byte is a control byte, which indicates that none additional data bytes are involved in the selected data word. Except in conjunction With this control byte, the CC signal is always = 0 until at least one clock pulse is produced. In these cases, the flip-flop 75 is then activated on a positive edge of the REP signal is set.

The J input of a flip-flop 76 is connected to the Q output of the flip-flop 75 is connected, and the former flip-flop is positively edge triggered by a Pulse train 10-180 generated by inverter 77. The Q output of flip-flop 76 generates the pulse trigger signal.

An AND gate 78 receives the CC signal at an input while its other input at the Q output of flip-flop 75 and its own output at the J input from a flip-flop 79, the Q output of which is in turn to the direct reset inputs the flip-flops 75 and 76 and to a counting trigger input of an intermediate digit clock interval counter 80 is connected. Between counter 80 and an input one AND gate 82 is a decoder 81, while the other input of the AND gate 82 is the DSO signal receives. The output of AND gate 82 is at the J input of a flip-flop 83, which is triggered by CP-O positive edges and receives the DS15 signal at the K input. An AND gate 84 generates a first reset latch signal FRI which = 1 is when flip-flop 83 and the selection counter are set at the same time 63 stores the value 0000, which means that DCZ = 1. An AND gate 85 is generated the read command signal, which = 1 when flip-flop 83 is in its at the same time is set and the selection counter 63 is a different from 0000 Saves value, i.e. DCNZ = 1.

A flip-flop 86 generates a second reset latch signal at its Q output SRI. Flip-flop 86 is edge triggered by the REP signal, and its J input receives the CC signal. An AND gate 87 provides for the direct resetting of flip-flops 86 by passing one of the CP-O pulses when flip-flop 86 is in the set state is located.

We now consider the byte transfer operation when byte 0001 is inserted into the shift register 70 on the basis of the receive command.

At the moment of the positive edge triggering by the REP signal Shift register 70 stores the value 0001 and the counter 71 stores the value 0000. Thus if the CCP signal = 1, and flip-flop 75 is triggered in its set state. Before 50 ms have elapsed, the 10-180 signal triggers the flip-flop with a positive edge 76 in its set state, and the pulse trigger signal will = 1. After another 50 ms has elapsed, one pulse of the ten pps pulse chain goes through AND gate 72 through to the count up input of counter 71 and to the gate circuit 18 to define a digit dialing clock pulse.

The positive edge of this clock pulse leaves the counter 71 at 0001 rise. At this point in time, shift register 70 and counter 71 store identical ones Binary numbers, and the CC signal generated by the comparison circuit 73 is therefore = 1. This is the beginning of the inter-digit clock interval. After the first 50 ms of the inter-digit clock interval, a flip-flop 79 is activated by the 10-180 signal in its set state is positively edge triggered, and it leaves in this state count the counter 80 and cause the flip-flops 75 and 76 to be reset directly. After another 50 ms has elapsed, the ten pps signal becomes the up counting input of the counter 80 positive edge triggering. During the next 300 ms, the ten pps signal becomes trigger the up count input of counter 80 three times more positive edge trigger, see above that the counter 80 now stores the binary number 11. At this point it is from Decoder 81 generated signal = 1. During the next interval in which the byte counter 55 of FIG. 3A is in the DS-O state, which is within the 2.5 ms period of a frame interval occurs, the clock pulse train CP-O the flip-flop 83 in positive edge triggering of its set state. This process marks the end of the inter-digit clock interval.

At the end of the intermediate digit clock interval, flip-flop 83 sets the counter 71, the flip-flop 79 and the counter 80 back to the subsequent transmission of a others Prepare byte. Resetting the flip-flop also allows 83 the FRI signal or the read command signal = 1. One will remember that every time a byte is inserted into shift register 70, the selection counter 63 counts up. If all sixteen bytes of a data word are already consecutive entered into the shift register 7G and transferred one by one, then the digit selection counter 63 returns to a count value of 0000. Thus, the DCZ signal becomes = 1 when flip-flop 83 is set, in which case the FRI signal becomes = 1. If there are still more bytes of the data word to be transmitted, then DCNZ = 1, and in this one In the case of the read command signal = 1, and it remains so until flip-flop 83 is reset will. This reset takes place while byte counter 55 is in the DS-15 state. This read command signal has in relation to the second to the last digit of the dialed telephone number has the same effect as the receive command signal in relation to on the first digit of the dialed phone number.

If the byte to be converted represents more than one digit dialing pulse, there is no fundamental deviation from the operating mode described above. In any case, after generating a sufficient number of clock pulses the "conversion completed" signal = 1, thus the binary number stored in the counter 71 becomes equal to the binary number stored in shift register 70, and thereafter becomes Inter-digit clock interval defined.

If the control byte entered into shift register 70 is 0000, then saves at the moment of the positive edge triggering by the REP signal the shift register 70 0000 and the counter 71 also 0000. Thus if the CCP signal = 0, and flip-flop 75 is not triggered in its set state, as in the operating procedure described above. Accordingly, flip-flop 76 does not triggered in its set state, the pulse trigger signal remains = 0, and no clock pulses from AND gate 72 are allowed to pass. Also becomes a flip-flop 79 is not triggered in its set state, and the counter 80 is not triggered in the position offset to cause the time limit for an intermediate digit interval. on the other hand in this case, flip-flop 86 is edge-triggered positive, so that the SRI signal = 1 becomes.

Referring to Fig. 3A, an OR gate receives the SRI signal, the FRI signal and the HSS signal, and it generates a lock reset signal IR. This IR signal = 1 when one of the three signals received by OR gate 90 = 1 is. The IR signal directly resets flip-flop 47 and passes through the OR gate 64 so that it directly resets the selection counter 63.

Because of the resetting process of flip-flop 47, the attenuation trigger signal is reversed to 0 and the relay driver circuit 24 of FIG. 1 drops relay 25.

As a result, the relay contacts 26 return to their position shown in FIG. 1 Position back, short-circuit the output pulse 20 and disconnect the damping capacitance 27 from.

It is now assumed that the damping trigger signal = 1 through the whole conversion operation of converting a selected data word into Digit dialing pulses through and otherwise = 0. Is the damping trigger signal = 0 at the time a participant selection button is activated, then it becomes = 1 due to a selectively generated dial signal, and this change from 0 to 1 triggers the sequence of operations required for reading the repertoire memory 50 and for conversion of the sequentially read bytes belongs in corresponding pulses. If at the time pressing a subscriber selection button the attenuation trigger signal already = 1 there is no such change from 0 to 1. As soon as a first If the subscriber dial button has been pressed, there is a lock that prevents that another participant button is pressed by mistake.

Significantly, the damping capacity is throughout Time that the attenuation trigger signal = 1 between a wire 11 and the ring line connected. The value of the attenuation capacity is preferably approximately 25 alicrofarads. It has been shown that this capacitance value significantly reduces the clicking noises, which one perceives in the handset when the series circuit is alternately closed and is interrupted.

The resettable sequence circuit 44 is activated by the HSS signal perform the same automatic disconnection function as an erroneously selected one Dial button.

In particular, simply depressing the hook switch leads to that the current sensor circuit 21 acts on the low-pass filter 23 that the HSS signal = 1 becomes. The OR gate 90 of Fig. 3A responds to this by resetting from flip-flop 47 for re-election can be done. It sets also return the digit selector switch 63 to its original state, too in preparation for the next re-election. Since the damping trigger signal returns to the value 0, the relay 25 drops out. An AND gate also ensures 91 (Fig. 3B) that no further pulses from the erroneously dialed telephone number can go out of the output pulse 20.

Of course, the invention is not limited to the above embodiment described; in particular, other suitable Resettable sequencers and other repertoire memories can be used.

Claims (6)

Claims 1. Automatic dialing add-on for a conventional telephone set with a and b wires, characterized by a repertoire memory (17; 50) for storage several coded data words each corresponding to a telephone number, of which each consists of several bytes, each of which in turn is one of the the first to the last decimal digit of the telephone number is coded accordingly; a keyboard (16) for generating dialing signals for identifying a selected one Data word in the repertoire memory; a converter circuit with an input to Acceptance of coupled data bytes and an output for generating digit dialing clock pulses during operation depending on the receipt of the data bytes; a resettable one Sequential circuit for the sequential coupling of the data bytes of a selected data word to the input of the converter circuit; a controllable output pulse generator (20) for the creation and interruption of a series circuit diagram; one of the clock pulses dependent circuit for controlling the output pulse generator; a current sensing device (21); one of the current sensing means, the output pulser and the telephone set (13) Tandem-like connecting device, so that the a- and b-other at When the handset is picked up, current also flows through the series connection path and the current sensing device flows; one to that by the current sensing device Device responsive to flowing current for generating a logical fork status signal to the Detection of whether the handset is on the cradle or not; and through a circuit for coupling the logical fork status signal to reset the sequential circuit, when an open fork condition is recognized, so that a data word can be re-selected essentially immediately after the telephone hook switch is depressed is made possible. 2. dial additive according to claim 1, characterized by a resettable Interlocking means for temporarily preventing the keypad selection signals identify a selected data word, and through means for coupling the logical fork status signal to reset the locking device upon detection an open fork state. 3. dial additive according to claim 1, characterized by a logical Circuit for generating a logical converter status signal to detect whether the converter circuit generates timing pulses, and by one of the logic converter status signal dependent circuit for the attenuation of background noises resulting from the production and interruption of the series circuit path in the output pulse generator are generated. 4. dial additive according to claim 3, characterized in that the latter Circuit a capacitance (27), a relay (25) and a relay upon detection by the logical converter status signal that the converter circuit is working, has exciting relay driver circuit (24), and that the relay has switching contacts (26) for connecting the capacitance in series between a wire (11) and b-wires (12, 15) and for short-circuiting the output pulse generator (20) in the dropped out Has relay state. 5. dial additive according to claim 1, characterized in that the current sensing device (21) an optical coupler (22), and the device for generating the logical Fork state signal contains a low-pass filter (23), which depends on the optical Coupler generates the logic switch signal at a constant binary value, while the output pulse generator (20) establishes and interrupts the series circuit path. 6. dial additive according to any one of claims 1 to 5, characterized by a repertoire memory (17; 50) for storing several telephone numbers each corresponding coded data words, each of which consists of several bytes, each of which, in turn, has one of the first to the last decimal digit the telephone number is coded accordingly; a keyboard (16) for creating Selection signals for identifying a selected data word in the repertoire memory; a converter circuit with an input for receiving coupled data bytes and an output for generating digit dialing clock pulses during operation depending on the data bytes received; a sequential circuit for sequential coupling the data bytes of the selected data word to the input of the converter circuit; a logic circuit for generating a logic converter status signal for Determination of whether the converter circuit is working and emitting clock pulses; a controllable one Output pulse generator (20) for production and interruption of a Series connection path; a control circuit responsive to the clock pulses the output pulse in relation to the establishment and interruption of the series circuit path; a connecting device for connecting the output pulse generator in tandem and the telephone set (13) via a line (11) and ring line (12, 15); a capacity (27); a relay (25); a relay driver circuit (24) for energizing the relay, when the converter logic state signal determines that the converter circuit is operating, wherein the relay (25) switch contacts (26) for connecting the capacitance in series between a-wire and ring line while the relay is energized to attenuate background noise, which arise due to the production and interruption of the series connection path, which also short-circuit the output pulse generator (20) when the relay is not energized.