DE259444T1 - NON-VOLATILE STORAGE SYSTEM WITH TEST POSSIBILITY. - Google Patents

Claims (9)

Patent claims: A non-volatile memory system with a substrate (18) which contains potential wells (16) of a first impurity type in which field effect devices (21) of a second impurity type are arranged, which form non-volatile memory cells, the substrate (18) being of the second impurity type, characterized in that a reference potential generator device (6) is formed in the substrate (18) which is suitable for generating a reference potential; and that a control circuit (11) is provided for checking the threshold values and the read reference potential of the non-volatile memory cells (21), the control circuit (11) comprising: coupling devices suitable for selectively coupling the reference potential to the gate electrodes of selected memory cells (21) in temporal correspondence with a connection of selected potential wells (16) for the selected memory cells (21) to a first substrate node (VW) offering a first potential; first enabling devices suitable for enabling the measurement of the reference potential at a second substrate node (IN2) responsive to a control signal applied by a third substrate node (�I�N�Idigr;); and second enabling devices which responsive to a memory threshold test mode enable signal at a fourth substrate node (IN3) and adapted to selectively enable measurement of memory cell threshold potentials of a first polarity type corresponding to a first binary state stored in a cell (21) by applying a first well bias potential through the third substrate node (INI) to selected wells (16) and by applying a threshold test potential through the second substrate node (IN2) to the gate electrode of selected memory cells (21), and to selectively enable measurement of memory cell threshold potentials of a second polarity type corresponding to a second binary state stored in a cell (21) by applying a second well bias potential through the third substrate node (INI) to selected wells (16) and by applying a threshold test potential through the second substrate node (IN2) to the gate electrodes of selected memory cells (21). 2. A non-volatile memory system according to claim 1, characterized in that the threshold test potential varies both positively and negatively with respect to substrate mass. 3. Non-volatile memory system according to claim 2, characterized in that a plurality of memory cells are arranged in a common potential well (16), which potential well is electrically connected to the first substrate node (VW) through a first field effect switching device (M21). 4. Non-volatile memory system according to claim 3, characterized in that the first field effect switching device (M21) is responsive to the potential of the memory threshold test mode enable signal at the fourth substrate node (IN3). ■■" - " ■■ ·■■■'■' ^ 5. Non-volatile memory system according to claim 4, characterized in that the field effect switching device is a transistor (M21) connected in series between the first substrate node (VW) and the potential wells (16), which transistor (M21) is driven by a Schmitt trigger circuit (33) responsive to the memory threshold test mode enable signal. 6. volatile memory system according to claim 3, characterized in that the first enabling device comprises a second field effect switching device (M3) which is arranged between the reference potential generator device (16) and the gate electrodes of the memory cells (2l) and responds to an enabling signal at the fourth substrate node (IN3) 7. Non-volatile memory system according to claim 6, characterized in that the second enabling device comprises a third field effect switching device (M8) connected between the third substrate node (INI) and a potential well (16) *, the third field effect switching device ₍ M8) responsive to an enabling signal at the fourth substrate node (IN3). 8. A non-volatile memory system according to claim 7, characterized in that the first potential well bias signal is substantially substrate ground and the second potential well bias signal is negative for the p-type impurity potential wells and positive for the n-type impurity potential wells. 9. The non-volatile memory system of claim 8, wherein the magnitude of the second well bias potential is equal to or greater than the threshold test potential.