DE2534398A1 - MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR ARRANGEMENT - Google Patents

Description

Boeblingen, July 31, 1975

Applicant: IBM Deutschland GMBH

Pascalstrasse 100 7000 Stuttgart 80

Official file number: New registration File number of the applicant: GE 975 017

Monolithically integrated Kalbleiter arrangement

The invention relates to a monolithically integrated semiconductor arrangement with at least two components having a common zone, which have a transistor structure with a further Include component, one of which in cooperation with the Transistor structure a minority carrier injection current causing a parasitic thyristor effect, measures are provided which counteract an undesirable interaction between the components.

With increasing packing density and consequently also decreasing distances between the elements of an integrated In semiconductor circuits, it is becoming more and more important to pay attention to parasitic effects in such structures. This is especially true with monolithic ones Semiconductor circuits are the case in which all circuit elements are known to have the same method steps are subjected to manufacture. As a result, these components are to a certain extent dependent on one another. For example, you can do that Select the starting material and the various process steps in such a way that optimal NPN transistors are produced, although this is accepted must be that in general this choice will not be the most favorable for the other components. In practice it will compromises are therefore made with regard to the component properties

609885/0643

must strive for. But then one can no longer assume that individual ones are ideal in terms of their operating properties Components has in front of him, but must also under the aspect of the compromise made with increased, deviating from the ideal state calculate parasitic effects. On the current conduction process of a forward biased Schottky diode in However, in the form of an aluminum contact on N-silicon, to name an example already described in the specialist literature, no longer only exclusively majority holders involved, but

- at least in certain operating states - also in noteworthy conditions Scope of minority carrier injection flows to be taken into account.

In order to prevent interfering couplings between a jointly integrated one in Kalbleiter arrangements of the generic type mentioned above To suppress the transistor structure and another component, The following cash on delivery are available:

- Increase the distance between the NPN base and the hole injecting component to a multiple of the diffusion length of the minority carrier. The disadvantage here must be a relatively large Space requirements are accepted, since the diffusion length is often of the same order of magnitude as the transistor dimensions lies, which is the case in particular with low-doped epitaxial regions.

- Between the NPN base and the hole-injecting component, a component is placed in depressions in the semiconductor body Insulation layer, e.g. made of silicon dioxide, is provided. However, this is only possible if the manufacturing process in question is such Provides (dielectric) isolation zones, which generally means an increased outlay on the process. In addition, this is also the case Solution requires additional semiconductor area.

- A collecting P-area is provided between the NPN base and the hole-injecting component to which a

GE 975 017

(309885/0643

suitable potential is laid. Here, too, an increased space requirement must be accepted, which is usually highly undesirable is. With regard to the last-mentioned possible solution, DT-AS 1 809 687 is mentioned in relation to the state of the art.

In contrast, the object of the invention is to provide improved measures for suppressing disruptive couplings and, in particular, parasitic couplings Specify thyristor effects in semiconductor arrangements of the type mentioned, which are at least as effective how the previously known solutions manage without or with significantly reduced additional expenditure on semiconductor area.

To solve this problem, the invention provides in the claim 1. Advantageous further developments of the invention are indicated in the subclaims.

The invention is explained in more detail below on the basis of exemplary embodiments with the aid of the drawings.

In Fig. 1 is a cross section through a conventional monolithic Semiconductor arrangement shown, which contains an NPN transistor structure, with which together using a common Zone another component, in this case a Schottky diode, is integrated. On a semiconductor substrate 1, e.g. P-doped silicon, for example, a weakly N-doped layer 2, preferably applied as an epitaxial layer. In In the illustration shown, a relatively highly doped and per se known sub-collector zone 3 is also provided. In of the epitaxial layer 2 are one by means of conventional photolithography, etching and diffusion or ion implantation methods P-doped base zone 4 and in this in turn a heavily N-doped emitter zone 5 formed into a known transistor structure. The NPN transistor is thus acting through the collector zone Epitaxial layer 2 and the doping region 4 acting as the base zone and the doping region correspondingly acting as the emitter zone 5 shown. With B and E are the outer

GE 975 017

Ü09885 / 0643

Denoted for base and emitter. Adjacent to this transistor is in its collector zone, namely the epitaxial layer 2, a Schottky diode in the form of a metal / semiconductor contact with the metal contact 6. The production such Schottky dioden and especially the respective material composition a metal and a semiconductor material is known per se and is not the subject of this invention. The rectifying transition of such a diode occurs in the Area of the interface 7 between the metal contact 6 and the respective semiconductor area. The one external connection of the Schottky diode, in this case the anode connection, is labeled A. The associated cathode is made of the semiconductor material the epitaxial layer 2 is formed.

The very common monolithic semiconductor arrangement shown in FIG. 1, from which the invention proceeds, can in a further known manner compared to other circuit areas in the the same semiconductor body through (frame-shaped) isolation areas using blocked PN junctions and / or by means of dielectric Isolation techniques be isolated, but this is not essential in the context of the present invention. Farther the outer connections, as well as the shape, the relative distances and the proportions of the Doping areas only roughly for easier understanding shown schematically. Because the invention, which is yet to be explained, is based on such a known structure, are already here made some typical material and doping information. So can For example, 6 aluminum can be used for the metal contact.

The surface doping concentration of the emitter zone 5 can

2O 19

typically about 4 χ 10 and those of the base zone 4 about 10 atoms per volume unit. The epitaxial layer 2 may have a doping concentration of approximately 2 × 10 atoms per unit volume.

The semiconductor arrangement shown in FIG. 1 with a jointly integrated transistor-diode circuit can be used

GE 975 017

609885/0643

for example in the context of a monolithic memory cell circuit find, as shown in Fig. 2 partially schematically. The memory cell circuit indicated there is known per se and consists essentially of a flip-flop with two directly cross-coupled transistors, for example on the emitter side connected to one another are connected to a (not shown) first selection line (word line), and their collector-side Circuit nodes Nl, N2 connected on the one hand to an operating voltage via load elements (not shown) could be. The Schottky diodes are used to couple such a memory cell to the further selection lines (bit lines) BO, B1 Dl, D2 provided. These diodes are each connected to one of the normally operated NPN transistors in the manner shown above Tl or T2 integrated, so that the collector zone of the NPN transistor is fused to the cathode of the Schottky diode. Fig. 1 can therefore as a cross section through a Circuit elements Dl and Tl realizing semiconductor arrangement are considered.

It has been found, however, that an arrangement shown in the example of FIG. SCR effect (silicon controlled rectifier) can result, although the current flow of the Schottky diode mainly from the Electron injection into the metal (6 in Fig. 1) is formed. With the high current densities in the However, the diode structure, due to the requirement for a small area requirement and high writing speed, can The proportion of hole injection (minority carriers) from metal 6 into N-area 2 (collector zone of the NPN transistor) increases so much, that a considerable collection current can appear at the base of the NPN transistor. This hole injection flow is shown in Fig. indicated schematically with arrows; the aforementioned collection stream at the base of the NPN transistor is denoted by I ,, there.

coil

Thus there is effectively a laterally formed PNP transistor before, whose emitter is the (Schottky) metal 6, whose

GE 975 017

609885/0643

Base through the collector of the NPN transistor, namely the epitaxial layer 2, and the collector of which is formed by the base of the NPN transistor, namely the N-doped region 4. This results in the electrical equivalent circuit shown in Fig. 3, which corresponds to that of a semiconductor thyristor.

The switch-on condition for the parasitic thyristor thus formed reads:

^ß NPN * ⁰ W> ^{X for 01} PNP ^{<K X} -

In this case, α and β represent the current amplification factors of a transistor operated in base or emitter circuit. With a perfectly realistic value of β _NPN = 100, an extremely low value a _pNp > 0.01 is sufficient to switch on the thyristor. In the conductive state, said thyristor acts like an undesirable short circuit between the Schottky diode and the emitter of the neighboring NPN transistor. This thyristor effect is caused by minority carriers, which are injected at high current densities by the Schottky diode operated in the forward direction and partly collected by the base zone of the adjacent NPN transistor (FIG. 1). For the case, assumed as an example, of using such a transistor-diode configuration in a memory cell circuit, as shown in FIG. 2, this means an extremely disruptive effect when writing the memory cell. The task for this example is therefore to suppress the current gain ρ without significantly increasing the transistor area and thus the memory cell area, so that the highest possible packing density of the regularly many memory cells of a memory arrangement formed in this way can be maintained.

GE 975 017

609885/0643

In FIGS. 3A and 3B is a cross-section and a plan view of the embodiment of FIG. 3 improved according to the invention shown in Fig. 1 shown monolithic semiconductor device. As far as these representations agree with Fig. 1, the same reference numerals are used. In particular, again lies an NPN transistor structure (zone sequence 5-4-2) with an adjacent Schottky diode having a common semiconductor zone in the form of a metal / semiconductor transition (layer sequence 6-2). In addition to the illustration in FIG. 1, there is also the possibility of isolating the component configuration mentioned indicated by a particularly advantageous combined, namely dielectric / electrical insulation, which is preferably Is arranged in a frame (Fig. 3B). The areas provided for this purpose consist of depressions in the semiconductor material arranged oxide regions 30 over the heavily P-doped regions

According to the invention, the two are now integrated with one another Components (here transistor, Schottky diode) common semiconductor zone 2 between the base zone 4 of the NPN transistor and the area in which the Schottky diode is implemented, one higher than the common (collector) zone doped area 32 of the same conductivity type is arranged, which at the same time is the connection area of this which is required anyway Represents semiconductor zone. This separation and connection area can be made by means of known diffusion or ion implantation processes be introduced. Furthermore, it can advantageously be used together with the formation of the emitter zone (s) 5 or others identically or similarly doped regions are produced on the semiconductor wafer. As in Fig. 3A in broken lines is indicated, the separating and connecting area 32 can, however, also with a greater depth extension, if necessary up to the touchdown be provided on the possibly provided sub-collector 3. For such a structure it has been found that a Such an area 32 extremely effective as an artery for the minority carriers (holes) diffusing laterally from the Schottky contact can be used and thus the above-described parasitic thyristor effect in such or similar

GE 975 017

Ü09885 / 0643

structure is excellently suppressed. The lateral N + / N transition an opposing field for the holes develops between the epitaxial layer 2 and the separating and connecting area 32, which are largely reflected in this. This mode of operation is indicated schematically with arrows in FIG. 3A.

To illustrate this barrier effect with regard to the minority carriers, FIG. 4A is again based on that in FIG. 3A The arrangement shown, the area between the transistor base zone 4 and the Schottky diode is shown enlarged. The order 4A is mirrored about a vertical axis compared to FIG. 3A, so that the x-coordinate direction with the associated Corresponds to the diagram of FIG. 4B. This diagram shows qualitatively the minority carrier concentration ρ (χ) im N-area 2 between the Schottky contact (metal 6) and the base zone 4 of the NPN transistor. The one marked (a) The course of the concentration results from the assumption that there is no separation and connection area 32, whereas this is the case the course (b) shown in broken lines is achieved with the insertion of such an area according to the invention will.

It should also be noted that the hole current to the base and thus the parasitic current I to be suppressed is proportional to

tional to the minority charge carrier gradient dp / dx (law of diffusion) . This relationship is also shown in Fig. 4B. There where there is a transition from one doping to another is present (e.g. at the edges of the N + region 32), the minority carrier concentration ρ changes according to the doping ratios according to the relationship

P ₁ ZP ₂ = ^N 2 ^{/ N} l *

This relationship results from Boltzmann's law. With · N and N ₂ , respectively, are the doping concentrations, ie the number of doping atoms per unit volume in the involved

GE 975 017

6Ü9885 / 06A3

Designated areas. The continuity of the current requires that dp / dx be the same in all areas. With this consideration is the influence of recombination neglected; their consideration would also emphasize the usefulness of the measure according to the invention even more. From the above results that overall the ratio dp / dx or the inclination of the concentration profile and thus the current I when passing through the N + barrier in the form of the doping region 32 becomes smaller, which is very clear from the illustration of FIG. 4B. Of the The reason for this is that in the N + region there is a relatively greater decrease in the minority carrier concentration at a given dp / dx than must take place in the N region (epitaxial layer 2) because the p concentration is absolutely lower in the N + region.

In summary, it can therefore be stated that the treated Embodiment without additional expenditure in terms of semiconductor area and thus of space required for the memory cell the described parasitic thyristor effect is effectively suppressed by the interposition of the collector connection area. The invention is of course not limited to two jointly integrated elements, but it can be used in particular for monolithic integration technology usually several elements and circuit structures with each other a common Divide the semiconductor zone, in order to prevent the parasitic minority carrier currents in their expected path for this common zone anyway necessary doping area of the same conductivity type with only increased doping is to be provided as a connection and separation area.

The problems dealt with in the invention and the solution measures are furthermore not limited to in the above exemplary embodiment injecting Schottky diodes. Rather, the invention relates generally to integration a bipolar, preferably NPN transistor structure with others using at least one common semiconductor zone.

GE 975 017

609885/0643

seen holes or minority carrier injecting components while avoiding parasitic SCR or thyristor effects. Such other components of this type can be:

- PN diode (s)

- NPN transistor (s) in saturation mode

- NPN transistor (s) in inverse operation (generally for normal operation

- PNP transistor (s)

- Components that primarily carry majority carrier currents, but degenerate at high current densities, and one lead minority carrier currents that are small but no longer negligible in terms of parasitic effects, which would also include the Schottky diode on which the exemplary embodiment is based.

Finally, it should be noted that the measures according to the invention their meaning and effectiveness even when reversed respective conductivity types and corresponding consideration of the associated physical and electrical Keep (operating) parameters.

GE 975 017

809885/0643

Claims (11)

PATENT CLAIMS 1.? Monolithically integrated semiconductor arrangement with at least two components having a common zone, the a transistor structure with another element include, one of which, in cooperation with the transistor structure, causes a parasitic thyristor effect Minority carrier injection stream can go out, measures are provided that an undesirable Counteracting coupling between the components, characterized in that in the the two or several integrated components common semiconductor zone (2) between the base zone (4) the transistor structure and the area for the rest Semiconductor component a more highly doped than the common semiconductor zone (2), at the same time the Connection area of this semiconductor zone (2) representing and with regard to said minority carrier injection stream a barrier-forming doping region (32) is provided. 2. Semiconductor arrangement according to claim 1, characterized in that that the transistor structure is designed as an NPN transistor is, in whose collector zone the further semiconductor component is integrated, and that said doping region the collector connection region, which is more highly doped than the collector zone, is of the same conductivity type as the collector zone. 3. Semiconductor arrangement according to claims 1 or 2, characterized characterized in that said doping region (32) extends from the surface of the semiconductor body to approximately the depth the preferably simultaneously produced emitter zone (5) of the transistor structure extends. GE 975 017 609885/0643 4. Semiconductor arrangement according to claims 1 or 2, characterized in that said doping region (32) through the semiconductor layer up to and including the transistor structure, which is preferably embodied as an epitaxial layer (2) towards or in the vicinity of a so-called sub-collector zone (3), which may be provided. 5. Semiconductor arrangement at least according to claim 1, characterized in that the further semiconductor component is a an integrated diode is in the collector zone of the transistor structure. 6. Semiconductor arrangement at least according to claim 1, characterized in that the further semiconductor component is a Primarily leading majority carrier flows, with high flows however, it is a degenerating component that carries a minority carrier current that is no longer negligible. 7. Semiconductor arrangement at least according to claim 1, characterized in that the further semiconductor component one integrated in the collector zone of the transistor structure Schottky diode is. 8. Semiconductor arrangement at least according to claim 1, characterized in that the further semiconductor component a transistor operated in the saturation region, preferably of the NPN type. 9. Semiconductor arrangement at least according to claim 1, characterized characterized in that the further semiconductor component is an inversely operated transistor, preferably of the NPN type is. 10. Semiconductor arrangement at least according to claim 1, characterized in that the further semiconductor component is a to the transistor structure mentioned is complementary transistor. GE 975 017 ί · 0 ') π 8 5 / ο π / ₄ 3 11. Semiconductor arrangement according to one of the preceding claims, characterized in that it is the transistor structure to a transistor of a memory cell circuit, preferably a flip-flop transistor, and in the further Component is the associated switching element for selecting the memory cell via the selection line (s). GE 975 017 6Ü9885 / 0643