DE252931T1

DE252931T1 - LEVEL SHIFT FOR CMOS TO ECL LOGIC WITH TEMPERATURE COMPENSATION.

Info

Publication number: DE252931T1
Application number: DE1986907216
Authority: DE
Inventors: Keith Donald Poway Ca 92064 Lauffer; Jimmy Ikuo San Marcos Ca 92069 Sanwo
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1985-12-16
Filing date: 1986-11-24
Publication date: 1988-09-22
Also published as: DE3678439D1

Claims

PATENT ATTORNEYS KAHLER & KACK european patent attorney

DlPL-ING. KURT KAHLER,

PATENT ATTORNEY, MINDELHEIM

DIPL-ING.DIPL.-WIRT.-ING. JÜRGEN KACK,

PATENT ATTORNEY, MUNICH

Patent Attorneys Kahler & Käck, PO Box 248, D-8948 Mindelheim

Postfach 248PO Box 248

Applicant: NCR CORPORATION Gerberstraße 3

D-8948 Mindelheim DAYTON, OHIO USAD-8948 Mindelheim DAYTON, OHIO USA

Phone:(0)8261-3027

Fax: 8261-6563

Telephone: 52 20 54

Your reference: Our reference: Date:

N3821/EPC 28 May 1988

European patent application 86907216.5 (PCT/US86/02532)

Patent claims:

1. A CMOS to ECL interface circuit with:
Input devices adapted to receive CMOS logic level signals; interface devices (14, 16)
coupled to the input devices and are suitable for
Convert CMOS logic level signals into ECL logic level signals,
and a pair of supply voltage terminals (VA, VB);
and output devices adapted to supply the ECL logic level signals to served ECL devices,
characterized by an ECL circuit device (20) which
is arranged in the same temperature environment as the
operated ECL logic devices and with the pair of
Supply voltage terminals (VA, VB) are coupled to
Supply voltages for the interface devices (14,
16) to determine which supply voltages the changes
in which ECL output logic levels of the served ECL logic devices track as a function of temperature.

2. A CMOS-to-ECL circuit according to claim 1, characterized
characterized in that the ECL circuit device (20) is a
OR-NOR gate (20) with a first and second output
corresponding to the first and second

' · ■ '..■&rdquor;. . ■,. ■ Π ^&eegr; S 2 ^C J &Iacgr;

Supply voltage terminal (VA, VB) are connected to create the supply voltages for the interface devices (14, 16).

3. A CMOS to ECL interface circuit according to claim 2, characterized in that the first output is an OR output and is adapted to output a low ECL logic level signal and that the second output is an NOR output and is adapted to output a high ECL logic level signal.

4. A CMOS to ECL interface circuit according to claim 3, characterized in that a pair of resistors are respectively coupled between the OR and NOR outputs and a source of supply potential.

5. A CMOS to ECL interface circuit according to claim 4, characterized in that a pair of capacitors are coupled between ground and the pair of supply voltage terminals (VA, VB).

6. A CMOS to ECL interface circuit according to claim 1, characterized in that the interface means comprise a pair of complementary field effect transistors (14, 16) having their source-drain paths connected in series between the supply voltage terminals (VA, VB), that the gate electrodes of the pair of transistors (14, 16) are connected in common to the input device and that the junction point between the source-drain paths of the pair of transistors (14, 16) is connected to the output device.