DE2511716C2 - Optical printer with serial buffer memory, which processes binary words of different lengths - Google Patents

Description

25 1

groups of points from a point matrix is a , well-developed technology.

Ölest technique has been used in various forms [Or teletype printers, CRT Datenausgabestalionen of computers, Computerzeilendruokern and phoiosetzmaschinen, _to name just a few. The term "characters" used here means a large number of visible symbols, which also include vectors and alphanumeric characters.

Processes and devices used in electrophotographic copiers have been proposed For some time also for use in the production of original text or images directly from electronic ones Signals and not suggested by the usual optically projected image.

A preferred embodiment of such a device exposes a page image in succession Column side segments that are parallel to the axis the copy drum run. Conventional text is read in the shorter dimension of the page, and this type of text is called common typesetting. Certain other types of text are usually used with Lines of text are printed and read lengthways across the page. An example of such a text is the computer printout. This type of text is called rotated typesetting.

An optical printer should be able to selectively produce lines of text either lengthways or run across the page. This generation of lines should be based on the choice of the binary words of the font are made, which a character matrix according to the desired line orientation represent. When printing e.g. B. should be done in the usual typesetting, in which the lines of text run over the short dimension of the page, this printing can be done by a first database of the Type font which defines the characters by means of column spacing. To generate the in Writing lines running lengthways to the page can be another database in the rotated font be provided, the pattern for raster strokes that run along the writing line of the page. When printing in the paper is fed to the printing press in the same way for both sets of documents. The difference lies in the way the electronic control system throws the image onto the drum.

An optical printer has synchronization devices in order to generate the first clock pulses for the position assignment of the scanning light point on the scanning path to the raster scheme for the column segments of the printed characters and in dependence thereon, second clock pulses for controlling the operating cycles of the character generating circuit derive. A first memory device (page memory) is provided, which the to characters to be printed as binary-coded data at memory addresses, which addresses are assigned to the spatial arrangement of the characters on the page to be printed. Furthermore is a second memory device (font memory) is provided, which for each of the characters to be printed able to output binary signal sequence, which determines the light / dark control of the scanning beam.

ün US-PS 32 93 614 an arrangement for the representation of characters in the Kasterzeiienverfahren is described. This known arrangement contains a serial buffer memory which consists of a number of N shift registers with M stages, the

1 716 * /

Readout control for the continuous output of binary signals for light / dark control to the modulation device of the scanning beam is set up in such a way that the first stages of the shift registers mentioned are read out sequentially and cyclically. This arrangement also has a load control device for loading said shift registers with binary words, the first bit of a word being loaded into the first stage of one of said shift registers, the bit N + \ into the second stage of the same shift register and the second bit into the first stage of the following shift register, the bit N + 2 in the second stage of this following shift register and the remaining shift registers are loaded in a corresponding manner until bits 1 - N are distributed in the first stages of the shift register in the cyclical readout order and the other bits are distributed accordingly .

It is the object of the invention to provide a data conversion arrangement for optical printers of the said type provide, loaded cyclically and serially in the shift register with binary words of different lengths can be read out.

According to the invention, this object is achieved in an advantageous manner in that the serial buffer memory to be stored data words have variable length and that the bits of the data words in the following Way to be assigned to the shift register stages

Word X (e.g. consisting of N + 2 bits)

Bit 1
Bit 2

Bit N

Bit N + 1
Bit N + 2

First stage
First stage

First stage
Second stage Second stage

Register 1 Register 2

Register N Register 1 Register 2

Word X + 1 (e.g. consisting of N bits)

Bitl
Bit N-2

Bit N- 1
Bit N

Second stage Second stage

Third stage Third stage

Register 3 Register N

Register 1 Register 2

and that for the loading and shifting processes in the shift registers for the next word to be loaded X + 1, the word length of the preceding word X can be added to the register number at which the storage of this preceding word X begins Number N of the existing shift registers is divisible, that with the integer division result,

s5, which determines the number of shift cycles for word X before the loading cycle for word X + 1 takes place, a clock-controlled (clock 3) down counter can be acted upon

and that when the counter reading 0 is reached, a signal is available from a detector circuit, by means of which a ring counter circuit on the one hand and a clock-controlled (clock 1) delay circuit can be acted upon, which also controls the ring counter circuit through which the loading and advancement of the individual shift registers 1 to N is controllable,

and that the division remainder can be used to generate a signal for the numerical designation of the shift register, at

which the loading process for the bits of the next word to be loaded X + 1 has to begin,
and that each shift register stage is assigned a control circuit which consists of a logical combination for the individual bits of the word to be stored and the possible residual division signals,
and that the ring counter circuit contains a number of holding circuits which corresponds to the number of output clocks of a read clock controlled modulo-n counter, with one holding circuit being controllable by a residual division signal and by a clock (clock 1-clock 4) available from the modulo-n counter is, wherein the first hold circuit (s) can be controlled by the output signal of the zero detector and the further hold circuits can be controlled by the clocks delayed by the delay circuit, and the load and shift pulses can be supplied by the hold circuits.

The associated advantage is the variability, i. h., the better utilization of the storage space and avoiding redundancy in characters that require less storage information.

In general, the invention relates to the field of matrix printers and image display devices in which alphanumeric Characters are generated by controlling a dot forming device which has a Copy area covered. In particular, the invention relates to the control of these dots Device when it sweeps over a scanning path in raster form, the area of an entire page of text is captured by the grid. The invention is preferably used in a sheet electrophotographic printer used, in which sides are generated by a modulated point of light that is parallel to the axis Web on the outer surface of an electrophotographic copier drum with a modulated light point swept to selectively discharge the background or white area of the page to be generated and so to leave on the photoconductive layer an electrostatic latent image of the text characters which developed with toner and transferred and fixed on paper.

The present invention provides an improved means for controlling the conversion of the die Character identifying parallel binary data words of variable length into a serial binary Bit stream that defines the light / dark contrast pattern used to generate printed pages in the preferred embodiment of a sheet electrophotographic printer is needed.

The document store contains z. B. a large number of 18-bit binary words with constant Length that can optionally be addressed according to the character content of the page memory. These words with constant length are then optionally modified by additional bits, according to the desired Pleading and according to the number of lines desired per unit of length in the finished Hard copy. The result is a font memory word of variable length. But it can also be Words stored in the font memory can be of variable length to accommodate both the character type and the also define the pleading.

This variable lung word is used in uniquely manipulated and controlled in such a way that this and the following words are read serially that they are sequentially a binary clock pulse modulator control for each bit.

In particular, N shift registers, each with Λ / bit storage stages, are provided so that, on the basis of shift control signals, the bits stored therein can be shifted cyclically in stages to the first stage of each register.

The registers are loaded with the above variable length font storage words so that the first bit of word X is stored in the first stage of a selected shift register, bits 1 + N of word X in the second stage

ίο this shift register and progressively so on is stored. The shift register adjacent in the readout order receives the second bit of the word X, while its second stage receives the bit 2 + N and so on. This loading process continues until word X is completely loaded. The first bit of word X + 1 must be read immediately after the last bit of word X. To determine the correct register position in which the first bit of the word X + 1

jo has to be loaded, the bit length of the word X must be determined, since this length is related to the quantity N. Once this value has been determined, this length relationship is compared with the numerical designation of the shift register into which the first bit of word X was loaded. These two relationships, namely the bit length of word Λ "and the shift register pointer for the first bit of word X, are used to machine the shift register into which the first bit of word X + 1 is to be loaded, ie the shift register pointer for to deliver the word X + 1 as an output signal.

In order to determine the correct register position into which the first bit of the word X + 1 must be loaded, the bit length of the word X is given by the amount A / (the

.15 number of shift registers) divided to determine the remainder of this division. The remainder is added to the numerical designation of the shift register into which the first bit of word X was loaded. This sum forms a pointer which designates and controls the register into which the first bit, the bit 1 + N etc. of the data word X + 1 is loaded. The quotient of the division mentioned above also gives a measure of the number of shift cycles before the load cycle for the word X + 1.

In the event that the summation of the remainder and the shift register pointer for word X is greater than N , a second division of N is performed. In this case the remainder resulting from this second division is the pointer for the word X + 1 and the number of shift cycles before the load cycle for the word X + 1 is increased by the amount one.

In this unique way, the parallel binary words described above become variable with Length as a continuous serial bit stream at da; Given a point formation device.

The term shift register includes in the vorlic lowing use basically equivalent Einrich Hingen such. B. a N ■ M matrix of readable and writable memory locations, whose memory stcllcn I

fto to N are addressed in a circulating clocked order and their load data under the control one; Load / shift time or clock can be loaded and shifted. This clock is for the parallel! Data words of different lengths are receptive, dii

f'5 serially from said specific memory locations gclcsei will.

Advantageous further developments of the invention are characterized in that

a) the charge control circuit consists of a number of AND elements acting on an OR element, which each one of the possible division residual signals with one of the bit signals of the to be stored Link word that

b) the length of the generated by the modulo-n counter Clock signals (clock 1-clock 4) is a multiple of the read clock signals that

c) during a clock signal (clock 1 - clock 4) 2 shift registers are loaded or their Content is moved.

An embodiment of the invention is shown in the drawings and will be described in more detail below described. It shows

1 schematically shows the essential parts of an optical printer with a character generator according to the above-mentioned proposal and with a serial buffer constructed according to the present invention,
. F i g. 2 shows the pattern of a page in common typesetting on which the text from a printer of the type shown in FIG. 1 type shown was printed,

F i g. 3 the pattern of a page in the rotated font, the text of which is printed by a printer in F i g. 1 type shown was printed,

FIG. 4 shows a diagram of components and data flow of the main devices of the in FIG. 1 shown device,

F i g. 5 Components and data flow of the output part of the in FIG. 4 device shown,

F i g. 6 in a detailed representation of one of the 24 logic networks, ie M ■ N, which are contained in the loading subcircuit of FIG. 5, the network shown controlling the loading of the first stage of the shift register SR 7,

F i g. 7 in a diagram the shift registers and in particular the bit content of the word X + 1 of the first stage, as it is under the control of the in FIG. 5 is loaded,

F i g. 8 shows a more detailed representation of the ring counter of FIG. 5,

F i g. 9 shows the pulse trains of five clock signals generated by the optical grid and photodetector of FIG. 1 derived and for the control of the reading, loading and shifting of the in F i g. 5 shown Shift registers are used,

10 shows examples of the operations in a table the shift register shown in Figure 5 over 30 clock cycles,

F i g. 11 shows in a diagram the shift registers at the end of the clock or time period T2 (FIGS. 9 and 10), the data content of the shift register being shown after bit 16 of the word X-1 has been read from the shift register SR 6 and all three stages of SR 1 and SR 2 have been loaded with the corresponding bits of the next word X,

F i g. 12 the shift register at the end of clock period Γ8 with the data content after reading bit 4 'of word X from shift register SÄ 4 and loading the 22-bit word / Y completely,

F i g. 13, the shift register at the end of the cycle or time period 724 with the Datcninhall after two displacement of the shift registers SR1 to SR 6 relative to the in F i g. 12, whereas the shift registers SR 7 and SR 8 were only shifted once and then loaded with the corresponding bits of the data word X + 1, identified by a double line. At the end of the period 7 "24, A., _c 1 neon dor bits 20 ', shift register SR 4, has ended.

F i g. 14 two 40-bit font storage words,

one after the other in the shift register of FIG. 5 loaded as 18-bit word XI, 22-bit word X, 18-bit X + 1 and 22-bit word X + 2

S will and

F i g. 15 the cyclical reading of the first stages of the shift registers of FIG. 5, which is a serial, the 14 provides a bit stream comprising words X-I, X, X + 1 and X + 2.

ίο Fig. 1 shows schematically a xerographic Sheet printer 10, the components of the image generation controller used in connection therewith as Block diagram are shown. F i g. Fig. 2 shows a page 20 in the customary sentence arrangement as presented by the Printer 10 is generated. In the page 20, the characters 21 are arranged in lines of text 22, which in the usual direction of the short dimension 23 of the page.

The sheet printer 10 in FIG. 1 contains a copy

2c drum 11, which has a photoconductive layer 12 to Recording the image owns. This layer 12 is successively at a charging station 13, an exposure station 14, a development station 15, a transfer station 16 and a cleaning station 17 turned over. At the exposure station, that at the loading station 13 on the layer 12 is uniform applied electrical charge selectively derived by optical exposure with a binary on and Switchable light point 30, which runs through the path 31 parallel to the drum axis 11a. This selective Exposure through the light spot 30 creates binary elements of an electrostatic latent image 32, which consists of discharged white or background areas 33 and charged image areas 34. The electrostatic latent image 32 is brought in front of development station 15 where colored thermoplastic Resin powder of opposite static charge, called toner for short, on the charged image areas 34 is knocked down. The image so developed is electrostatically applied to sheet 35 at station 16 transfer. The thus printed sheet 35 is then passed through the fixing station 18, where by the action of heat the resin toner is temporarily softened so that it adheres to the sheet after cooling and a forms a permanent image. The finished printed sheet 35 is then fed to a tray 19, where it is the Machine can be removed. Eventually on layer 12 when leaving transfer station 16 Remaining toner is removed at station 17 before the cleaned surface 12 is further removed Operation is being recharged.

Mechanical details of a xerographic printer are well known and do not form a part of this invention.

The controlled point of light 30 is preferably generated by a source of high-energy coherent light, as it is a continuous laser 36 which emits a laser beam 37 over a light path through a binary Light point control modulator 38, via a deflection

(M) mirror 40, a lens 41, a scanning mirror 42, cine Lens 43, a beam splitter mirror 44 and a cutting blade 45 project onto the surface 12. the Modulator 38 is an acousto-optic Bragg element, as it is well known in specialist circles. the

<is modulator 38 reacts to the binary state (1 or 0) of the electrical information bit on its input line 46 and then sends the beam 37 in one of two closely spaced but somewhat

different, exit tracks 39a or 39b. When the beam 37 is sent over the exit path 39a, it is finally guided just past the cutter diaphragm 45 and hits the photoconductive layer 12 as light point 30. It discharges it there and so finally calls a white background area or a white point on the sheet 35 emerges. Light sent over the path 39b is emitted by the cutting diaphragm 45 blocked and therefore does not hit the photoconductive layer 12. The resulting Area of undischarged surface 12 results in, developed, a toned pixel as part of the Image area on sheet 35.

The scanning mirror 42 receives the laser beam 37 via both paths 39a and 39b and guides it over the Scanning path 31, whereby the laser beam creates a so-called column segment 24 (see Fig. 2) of the image of the page 20 generated. The mirror 42 is designed as a regular polygon and is driven by the motor 47 with a constant Speed driven related to the rotational speed of the drum 11 and the size of the point 30 is chosen so that the individual scanning strokes of the light point 30 are immediately adjacent Cover areas of layer 12 in a full side exposure raster.

The beam splitter mirror 44 intercepts a fraction of the laser beam 37 from both paths 39a and 39b, while the beam is scanned through mirror 42 and directs this fraction through the optical grating 50 onto the elliptical mirror 51, from which the light onto the photodetector 52 is reflected, which lies in one of the focal points of the mirror 51. The scanning mirror 42 is optically in the another focal point of the mirror 51, so that the grating 50 is at the same distance as the exposure station 14 appears. The photodetector 52 thus generates a train of clock pulses 53, i. H. a reading clock that a is a direct measure of the scanning movement of the laser beam 37 relative to the photoconductive layer 12. The on Pulses generated by photodetector 52 occur at the same rate at which picture elements or dots occur are to be defined by the modulator 38, so that the photodetector 52 directly a master or read clock signal to control the modulator 38 can generate. Furthermore, a continuous transparent part 54 of the Grid 50 is provided in order to be able to sense the end of each raster scan.

The point density of a scan along the trajectory 3t, with which the column segment 24 is to be generated, for. B. 240 points per unit length, so that a grid 50 with 120 opaque lines per unit is required. The orthogonal point density measured in direction 23 in FIG. 2, can also be 240 points per unit of length.

A Tcxtscitc with original data, as z. B. comes from a magnetic card or tape unit 55, delivers the text data to be printed to the Datcnvcrarbeilungsgcritl 56. In this way the text data is composed and stored in the page memory 57, each character or symbol to be printed, as well as the space to be set between the characters stored in the page memory 57 at individual memory addresses, which in turn belong to the sclireib / .eilen der Page and the back position of the character within the Schrcib / .cilc belong. For example that in I'ig. 2 shown several liits comprehensive data word for the definition of the character »/ * < im her 57; stored in an address which, through the eighth line of writing (provides seven blank lines the upper margin) and the 17th character position is defined (the left margin in this example is defined by 5 Spaces formed).

Once the text is composed in the page memory 57, the character generating circuit delivers 58 the necessary binary dot control pattern for the modulator 38 to reproduce the text page. Besides the page memory 57 also have the

ίο data processor 56 and the character generation circuit 58 Access to a further memory 59, which has a page memory address saver register 60 and a Reference address and step value table or a translation table 70 contains.

The page memory address control register 60 is schematic in Fig. 4 shown. This register is preferably an associated part of a read-write memory 59 (Fig. 1) and in particular contains a plurality of individually addressable memory cells, each of which can store a data word which is divided into a page memory address part and a step control part The addresses of these memory cells are sequentially assigned by a page memory address control line count register 65 (Fig. 4) addressed to their addressing with the line scan through the point of light 30 to synchronize. During the addressing, the register 60 supplies a data word via a divided one Data path and sets the address part of the data word in the page memory address register 67 and the step control part into the current step register 68.

The translator 70 is formed by a read-only memory which has a number of individually addressable Contains data words, each of which is uniquely identified by a character identification code from the page memory 57 is addressed. Each of these data words contains a first part which is a reference address for the document memory 92 forms and a second part indicating the total number of column segments 24 (Fig. 2), which is required for the complete generation of the character.

The data words contained in the translator 70 can be individually stored in the page memory 57 through the Address register 75 can be addressed. The address register

75 contains one or more status bits 76, which are used to select a specific document or a Type of printing, such as Represented by Tables A, B and C described later, previously can be set. When the font store 92 output one of these three different fonts ν · soll, the font to be used is replaced by the Data output from the document address and step memory 70 according to the position of the status bits

76 elected.

The data path 80 originating from the translator 70

ss is divided into two parts, namely into a reference address path 81, which leads to the register 82, and

into a total step value path 83 which is connected to the total step register 84. If the value is zero in the current step register 68, the

i> o recognition circuit 85 via data path 86 den

Contents of the register 84 to the Rcstschrittrcistcr 87, from

where the content with the content of the register 82 to the

Font protection memory address subtraction logic90 supplied will. Through this operation a certain

f.s Sehriftsal / .speieheradiesse generated in the address register 91.

When the data in the current step register 68 has passed

circuit 85 cannot be determined to be zero, then the data from the register are sent via the communication path 86

68 and not that from register 84 to register 87.

Each binary data word in the document memory that is created by an address applied to the address register 91 is controlled, defines the light / dark contrast pattern for generating the small part of the column segment 24, which corresponds to a character such as character 21 in FIG. 2 heard. The creation of each symbol requires several column segments 24. An equal number of data words is therefore in the document memory 92 and thus forms a whole group of data bits that form the contrast pattern for the Define associated characters under correlation with a corresponding grid pattern. The addresses adjacent data words correspond in this example to adjacent character column segments 24 and therefore differ by the constant one. Instead of a single binary bit for each light / dark point A wide variety of code compression methods can of course also be used.

The binary word retrieved from the document memory 92 via the register 91 is transmitted via the output lines 96 passed to the issue control serial buffer 97. The individual bits of the in the output buffer 97 Conducted binary words are switched through to the modulator 38 by means of the read clock pulses 53.

The part 99 outlined with a broken line in FIG. 4 symbolizes the output part and is in detail in FIG. 5 shown

The device for buffering binary words with different lengths and for serial reading without a discontinuity between the last bit of a word and the first bit of the next word, im In connection with three different pleadings. However, this example is not intended to be This is a limitation, but merely demonstrates the usefulness of the present invention.

The three pleadings selected are the common typeface arrangement with six lines per 2.5 cm; the common format with 5V ₃ lines per 2.5 cm and the rotated format. The two common formats include the option of underlining characters. The common format is shown in FIG. 2, the rotated format in FIG. 3.

The binary words of different lengths that the modulator 38 (Fig. 1) serially for these three Exemplary briefs control are outlined in Tables A, B and C.

Table Λ

2nd word

I. Won

Bit 1
Bit 2

Bit 17
Bit 18
0

1 I. 0

Bit 1
Bit 2

Bit 17
Bit 18

not used
not used
not used
not used Table A shows the first and second binary words of several bits which are necessary to generate the small part of the segment 24 (FIG. 2) which belongs to a character 21, if a common format with a line density of six lines per 1 inch is produced. As shown, each binary word contained in the font memory 92 is 18 bits in length. To produce a character in this particular format, each character sample must be 40 bits or dots in length. The first font word is used in unchanged 18-bit form. The second written word comprises the 18 bits, followed by an additional pattern 0110 of four bits. With this additional bit pattern z. B. an underline can be displayed. On the other hand, this four-bit pattern in the form of 0000 can indicate the absence of an underline. In either case, the second font word is modified to a bit length of 22 bits and thus results in the total required value of 40 points for the character scan.

Table B.

2nd word

1st word

Bit Γ 0 per 2.5 cm Bit 2 ' 0 Bit 3 ' 0 Bit 4 ' 0 Bit 5 ' Bit 1 Bit 6 ' Bit 2 Bit 17 ' Bit 13 Bit 18 ' Bit 14 0 Bit 15 0 Bit 16 0 Bit 17 0 Bit 18 Common format 5 ^! / 3 lines

Common formal
Six lines per 25 cm Table B shows the first and second binary word made up of several bits, which are derived from the font word and then modified to the character scan required _{to generate a common format with a line density of 5V 3 lines per 2.5 cm} the binary font / memory word is also 18 bits long. In order to generate a character in this special format, however, j cd ι character scan must be 44 bits or points long. Before the first written word of 18 bits, dcshall always has an additional pattern 0000 made up of four bits. This additional Bitnuislcr provides a white or background field for adaptation to the larger line spacing. The second 18-bit font word comprises the 18 bits and an additional pattern 0000 made up of four bits. As explained above, the character underlining is displayed with this additional bit pattern given more than one font word. In this case, the bit pattern 0000 indicates the absence of an underline, mg. The addition of a four-bit pattern at the beginning before the first font word and at the end after the / wide font word results in tl ^: required total length of 44 points for the character scan.

25 Π

Table C.

Wurl

Bitl
Bit 2

Bit 17
Bit 18

not used
not used
not used
not used

rotated typesetting

Table C shows the single 18-bit binary word that is derived from the font memory and is then used unchanged for a character scan in the rotated font. That from the Binary word received font store is always 18 bits long. There is no change and that to everyone raster stroke belonging to rotated font characters is 18 bits long.

As can be seen from Tables A, B and C, the binary word is of variable length between one 18-bit word (the first word in table A and all words in the rotated font) and a 22 Bit large word (the second word of table A and the first and second word of table B) variable. As already mentioned, these words can already be stored in the font memory with variable or variable length 92 instead of using the modification procedure described.

In Fig. Figure 5 shows the output of the font memory 92 as an 18-bit parallel word to the word length modification circuit 110. This circuit is provided by line 76 controlled, d. H. by the status or control bits contained in register 75 (FIG. 4), so that the length of the brief memory word corresponding to the selected brief after the representation in the exemplary tables A, B and C is changed. This pleading word is then either in his unchanged length of 18 bits or in the changed length of 22 bits in buffer register 111 saved. F i g. 5 contains designations in brackets that indicate that the word X + 2 is the next in the Modification circuit 110 is word to be entered while the word X -t- 1 is in the buffer register 111.

At the same time, the word X is in the eight shift registers with the designation SR 1 to SR 8. Each of these eight shift registers is formed by a three-stage register, the data of which is read cyclically from the first stage under control of the read clock signals 53 and sequentially from the second to the first Stage and moved from the third to the second stage.

The loading and shifting of the binary words of variable length in the shift registers SR 1 to SR 8 is controlled by the signals from the photocell 52 (FIG. 1), that is to say by the reading clock signal 53. This timing operation can be best illustrated by the example of FIG 10, where the reading clock is formed from a signal 53 and the clocks 1, 2, 3 and 4 are supplied by the modulo-eight counter 112 (FIG. 5). These four counters are fed by the signal 53 and, as shown in FIG. 9 four

35

40

45

so

do phase-shifted output pulse trains.

FIG. 10 tracks the reading clock 53 (FIG. 9) over 30 time intervals, that is to say 15 cycles. Each interval T is a relatively short time, such as 100 nanoseconds. The five columns in FIG. 10 indicate the control action which takes place on the shift registers SR 1 to SR 8 during each time interval and during each clock pulse 1, 2, 3 and 4 (FIG. 9). The active clock pulse of each clock lasts 200 nanoseconds, just like one cycle of the reading clock generator 53.

FIG. 10 is best viewed in conjunction with FIGS. 11, 12 and 13 to be understood. F i g. 11 shows in a diagram the eight shift registers SR 1 to SR 8 at the end of the period Ύ2. This figure shows the data content of the shift register after bit 16 of word XI has been read from shift register SR 6 and all three levels of SR 1 and SR 2 have been loaded with the corresponding bits of the next word X. According to the illustration in FIG. 10 bit 15 of word X- 1 is read during period 71. Bit 16 of this data word is read during the time interval T2. During the clock pulse 100 (FIG. 9) of the clock 1, the shift registers SR 1 and SR 2 are loaded with the corresponding bits of the data word X , which are marked with a line.

According to this principle, bit Γ is loaded into the first stage, the register SR 1. Since the number N of registers is eight, the N + 1 bit, ie bit 9 ', is loaded into the second level of register 1, and bit 2Λ / + 1, bit 17', is loaded into the third level of the Register SR 1 loaded.

Correspondingly, bit 2 'is loaded into the first stage of the register SR 2, bit N + 2 or bit 10' into the second stage of this register and Dit 2N + 2 or bit 18 'into the third stage of this register.

While the reading clock continues from time interval Ύ2 to time interval 78, the first stage of shift registers SR 7 and SR 8 and then SR 1 to SR 4 are read progressively and thereby bits 17 and 18 of data word X- 1 and then bits Γ to 4 'of the data word X is read out. The shift registers SR 3, SR 4, SR 5, SR 6, SR 7 and SR 8 are loaded with the corresponding bits of the data word X until the word X is completely loaded at the end of the time interval 78.

F i g. 12 shows a diagram of the shift registers at the end of period 78 with their data content after bit 4 'of word X has been read out from the first stage of shift register SR 4 and after the 22-bit word X has been fully loaded. This figure shows indicates that the first level of a particular register has been loaded with a given bit position of the word X , whereas the second level of this register has been loaded with the bit position increased by the amount N, in this case eight, and the third level of this register with the bit position which is 2N greater than the bit position with which the first stage was loaded. Since the word X is assumed to have a size of 22 bits, the third stage of the register SR 6 receives the bit position 22. Loading the registers SR 7 and SR 8 results in no value-representing or significant data in their third stages.

While the read clock cycle continues, the first stages of the shift register are read cyclically. In addition, the shift registers SR 1 and SR 2 by the clock 1, the shift registers SR 3 and SR 4 by the clock 2, the shift registers SR 5 and

(O

SR 6 shifted by clock 3 and the shift registers SR 7 and SRS by clock 4. At the end of time 716, all registers have experienced a shift cycle. During the period 717 to 724, the shift registers SR 1 to SA 6 experience a second shift cycle and the shift registers SR 7 and SR 8 experience a load cycle. During this second shift cycle, the first and second bits and the corresponding bits N + 1, N + 2.2N + 1 and 2Λ / + 2 of the word χ + 1 are loaded into the shift registers SR 7 and SR 8.

F i g. 13 shows in a diagram the shift registers at the end of the period T24. This figure shows the data content after the shift registers SR 1 to SR 6 have been shifted twice compared to the state shown in FIG. 12 and after the shift registers SR7 and SRS have been shifted once and then loaded with the corresponding bits with double bars of the data word χ + 1. At the end of period T24, bit 20 'of data word X (first stage of SR 4) has been read.

The shift register SR 7 was used as the place for loading the 1.9. and 17. bits of word X + 1 denotes the machine implemented algorithm that performs calculations based on knowledge of the bit length of word X and of the shift register into which the first bit of that word was loaded. Specifically, this algorithm requires that the length of the previous word X (22 bits) be divided by the total number N of shift registers (8) to derive a remainder (6), which remainder is then added to the numerical designation of the shift register which received the first bit of the word λ "(the register SR 1 as shown in FIG. 11) in order to identify the shift register (SR 7) whose first stage receives the first bit position of the word χ + 1. For in the case where the summation of the remainder and the pointer is greater than N, a second division is carried out by N. In this case, the remainder resulting from this second division is the new pointer.

F i g. 5 shows an equivalent machine implementation of an algorithm which requires that the bit length of word X (22 bits) is added to the previously calculated pointer value for word X (SR 1) and where the sum (23) is divided by the total number N of shift registers ( 8) is divided to derive a remainder (7) which designates the shift register (SR 7) whose first stage receives the first bit position of word X + 1.

In both cases, the quotient of this division controls the load / shift cycles shown in FIG. The quotient indicates the number of shift cycles for the word Xan that are necessary before the load cycles for the word X + 1 are enabled.

From the above detailed description of the cyclical reading, loading and shifting of the shift registers SRi to SRS , the sequential conversion of parallel binary words of different bit lengths into TV bit-sized binary words follows, which are converted cyclically into an uninterrupted serial bit stream at the output 46.

Fig. 14 shows two 40-bit font storage words that are sequentially loaded into the shift registers in four load cycles. During the first load cycle, the 18-bit X- 1 is loaded into the shift register. This word continues to be bit-serial as shown in FIG. 15, read out. While the bits of word X- 1 are being read out, the 22-bit word X ( FIG. 14) is loaded. At the end of time 718 (Fig. 15), word X- 1 has been read completely. During time interval 719 the first bit of word X is read and then word X continues to be read as described above while word X + 1 (FIG. 14) is loaded at the same time. At time 740 (FIG. 15) the last bit of the word X has been read out and is therefore there: the 40-bit word has been completely read, and the modulator 38 has been controlled accordingly.
ίο According to Table A, the 40-bit character word, represented by the words X- 1 and X, defines a character in the usual format with a line spacing of six lines per 2.5 cm. The bit pattern 0110 represented by bits 19 through 22 of word X indicates that this character should be underlined.

The first bit of word X + 1 in FIG. 15 is read out during period 741. The word X + 1 continues to be read out until the end of the time 758, until the last significant bit 18 has been read out and the reading out of the word X + 2 begins. The font character represented by the words X + 1 and X + 2 has no underlining as defined by the definition 0000 by the bits 19 to 22 of the word X + 2.

According to the illustration in FIG. 5, the bit length of the word X is entered in the register 114 and given as the first input via the line 116 to the adder 115. The information present on the line 116 states that the word X is 22 bits long (see FIG. Dog 15).

A previous logical calculation with regard to the word X- 1 identified the shift register SR 1 as the one which receives the first data bit and the corresponding subsequent data bits of the word X. This load pointer information is given as output 117 from pointer register 140 and the numerical designation of this shift register, namely "SR 1", is added to the information on line 116 in order to produce output 119 from adder 115 which shows the sum "23" .

This signal, namely the "23", is divided by eight by the division circuit 120. the The quotient of this division, namely 2, is given as one output on line 121, while the remainder the division, namely 7, is put on line 122 as the second output.

The pointer generation circuit 118 in FIG. 5 comprises part of the load control device and supplies a pointer for the word X + 1 on the output line 123 which the shift register SR 7 designates as the shift register which has received the first and the corresponding subsequent bits of the word X + 1 zi.

The quotient output of this division is stored in down counter 124. This is one of the following:

Control of the clock pulse 3 downwards from a Wer 2, this clock input being supplied by the line \ 2i. From FIG. 10 it can be seen that the counter 124 counts down from 2 to 1 at time 76 and from 1 to 1 at time 714. The circuit 126 checks the contents of the counter 124, and if this is 0, the output conductor 127 is energized and thus the ring counter 12 is enabled. The ring counter 128 is switched on at time 72. It is shown in detail in FIG. This ring counter contains a load / shift control and controls the shift registers SR 1 to SR S so that the load / shift functions shown in FIG. 10 are carried out.

A second release signal, the function of which is evident from the description of FIG. 8, is provided by the Output of delay circuit 152 on line 150 is given. This delayed switch-on signal is four periods relative to the turn-on of the signal on line 127 in accordance with the first Clock input on line 151 is determined.

The load cycle for word X + 1 begins at times 723 and 724, as shown in FIG. 10, when the specific bits of the word X + 1 are loaded from the ι ο buffer register 111 into the shift registers SRi to SR 8 under the control of the load control circuit 153. This circuit directs the loading of the first bit of the word X + 1 into the first stage of the shift register SR 7, as shown in FIG. 13. In addition, the 9th bit of the word X + 1 into the second stage of the shift register. SR 7 and the 17th bit loaded into the third stage of this shift register. As already explained, the shift registers SR 7, SR 8, SRi, SR 2, SR 3, SR 4, SR 5 and SR 6 progressively in time during the intervals 723 and 730 as shown in FIG. 10 loaded.

F i g. FIG. 6 shows one of FIG. 24 logical networks making up charge control circuit 153. Each of the 24 logical networks clearly belongs to one of the 24 shift register stages. The circuit shown in FIG. 6 belongs, for example, to the first stage 159 of the shift register SR 7 (see FIG. 7). As already explained, the word load pointer X + 1 on the line 123 (FIG. 5) points to the shift register SR 7. The line 154 thus switches the AND gate 155 on. The first bit 1 "of the word X + 1 is put on the line 156 and loaded into the first stage of the shift register SR7 via the line 157 and the OR gate 158, whether it is a binary one or a zero 7 shows this bit loaded into the first stage 159 of the shift register SR 7.

The 23 other charge control circuits differ from that in FIG. 6 only in that the IJND element inputs are placed in such a way that loading takes place in the correct manner. The load control circuit belonging to the first stage 160 of the shift register SA 8 is, for example, with the one shown in FIG. 6 is identical, where the four AND gates with bits 4 ", 66", JS "and 2" of the word X + 1 are provided. When the pointer SR 7 is active, the bit 2 "runs through the associated OR element and is loaded into the first stage of the shift register SÄ 8.

Similarly, the subsequent bits of word X + 1 are loaded into the first stage of all shift registers, and similarly the second and third stages of the shift registers are loaded under the control of load director 153 until all bits of word X + \ are loaded. According to FIG. 10, this charging process is completed at the end of period 730.

The in F i g. Ring counter 128 shown in FIG. 8 contains four hold circuits 129 to i32. Each of these hold circuits is provided with a clock input which is correspondingly connected to the outputs for the clocks 4, 1, 2 and 3 of the modulo-eight counter of FIG. In addition, each of these hold circuits is controlled by one of the unique fin pointers SR 1, SR3, SR5 or SR 7 , which are generated by the pointer generator 118 as output signals on the line 123. Since the variable word length in the buffer register 111 is always an even number in the exemplary description of the present invention, you either include IS and 22 Bib, and loading always begins at the shift register SR 1, only the pointers for the shift registers SR 1, SR 3, SR 5 or SR 7 required. These pointers control the holding circuits 129, 130, 131 and 132. In addition, the enable lines 127 and 150 enable the operation of the ring counter 128, ie in detail, the switch-on line 127 controls the operation of the hold circuits 129 and 13C, whereas the switch-on line 150 operates the hold circuits 131 and 132 controls. The D input of the hold circuit 129 receives its control signal from the OR gate 133, while this gate is controlled by the AND gates 134 and 135. There; AND gate 134 is switched on when the pointer generator 118 has generated a pointer to the shift register SR] and the counter 124 is at zero. There; AND gate 135 is switched on when the Q output of the hold circuit 132 is excited (a binary one and a pointer other than SR 1 is generated. The latter function is performed by the inverter 161.

The output 136 (FIG. 5) of the ring counter controls there; Loading / shifting of the shift registers SR 1 to SRi as shown in FIG. 10. The Q outputs of the hold circuits 129 to 132 in FIG. 8 form the load / shift control of the shift registers as shown in FIG. 10. If (is blocked or a binary one is present, the output forms a load command. If Q is never energized or a binary zero is present, the output forms a shift command. From FIG continues from time 79 to time T22, whereupon the SR 7 pointer 162 on line 123 controls the latch circuit 132 so that the ring counter 128 generates four (? excitation output signals which form the four charge output signals taken from the Q> outputs of hold circuits 132, 129, 130 and 131. Thus, word X + 1 is loaded from time 722 to time Γ30.

Similarly, it can be shown that the pointer to be generated for word X + 2 (FIG. 14) would indicate that word X + 1 is 18 bits long and since the load pointer for word X + 1 is SR 7 , the quotient output 121 of the circuit 120 would be a "3" and the remaining output would be a "1", which would point to the shift register 1 as the loading point for the word X + 2 .

The shift registers SR 1 to SA 8, of generally known type, have a shifting load input and a clock input, so that the loading and shifting of the data is controlled by a switching element under the control of the input line 136. The first stages of these shift registers are also read out via the output 46 under switching element control of the reading clock generator 53. This function is shown at 141.

When considering the operation of the in Fig. 8 In the ring counter shown, it is assumed that the pointer generator circuit 118 (Fig. 5) has the SÄ 1 pointer line 163 has excited in order to prepare the AND gate 134. It is further assumed that the Down counter 124 (FIG. 5) contains zero after it has been counted down by clock 3. So the Line 127 energized, and the AND gate 134 is now switched through. An excitation signal, i.e. H. a binary One, runs through the OR gate 133, whereby the (^ output 164 of the hold circuit 129 during the Cycle of the clock 4 is excited, which immediately precedes the period Tl, which is shown in Fig.9. As a result, line 172 of load / shift control 136 provides an active signal to the shift / load gates the shift registers SÄ 1 and SÄ 2 and

j thus prepares these registers for a load cycle. The clock input switching elements of the shift registers SR 1 and SR 2 are controlled by the clock 1. During the time interval 71/72 (see FIG. 9) the shift registers SR 1 and SR 2 are thus loaded with d ^ n corresponding bits of the word X (see FIG. 10).

Furthermore, the active signal on the line 164 runs through the AND gate 166 (the output of the inverter 165 is active) and the OR gate 176, so that the O output 167 of the hold circuit 130 during the cycle Ti, 72 of the first cycle gives an active output on ladder portion 173 of loader / slide controller 136. When energized, the line 173 controls the shift / load switching elements of the shift registers SR 3 and SR 4 and prepares them for a loading operation.

The clock input elements of the shift registers SR 3 and SR 4 are controlled by the clock 2 so that the correct bits of the word X are loaded into the shift registers SR 3 and SR 4 during the cycle 73, 74 controlled by the clocks 2 and 3 so that active output signals (binary ones) _s on the INTR 174 and 175 of the load / shift control 136 Leeben. The signals on these lines control the loading of the shift registers SR 5, SR 6 and SR7 SR8 accordingly to enable the correct bits of word X to be loaded so that at the end of period 78 word X is fully loaded as shown in FIG is. <-, «, ·,

At the end of time 78, line 171 is active and prepares AND element 135. Since the SR 1 pointer line 163 is energized at this time, the output of the inverter 161 still holds the AND gate 135 disabled. The calculation of the pointer for the word X + \ (SRJ) has also set a number in the down-counter 124 (FIG. 5) so that the line 127 is now switched off and the AND element 134 blocks. As a result, the output of OR gate 133 is not energized or contains a binary zero. During cycle 77, 78 of clock 4, the O output 164 of the hold circuit 129 changes from the excited to the non-excited state. The binary zero now appearing on line 172 controls the shift / load circuits of shift registers SR 1 and SR 2 so that the content this register is shifted and not loaded during cycle 79-710 of clock 1. Similarly, an inactive signal (binary zero) passes through lines 173, 174 and 175 of load / shift control 136 so that the load / shift controls of shift registers SR 3-SR 4, SR 5-SR 6, SR 7-SR 8 through the clock 2 shifted cycle 3 and cycle 4 accordingly during the time interval 711-716

The O output 171 of the hold circuit 132 becomes made inakt.v during cycle 713-714 of measure 3. During cycle 715-716 of, clock the AND gate 135 is thus blocked. While the (F i 5) jtt i active signal

If the AND element 135 is thus energized, the counter test circuit 126 (FIG. 5) now gives an active signal on the line 127 (the down counter 124 was reduced to zero by 713714, as is known), the pointer generator circuit 118 (FIG. 5) has an SR 7 Pointer generated for word X + 1 and line 163 is therefore not energized. Cycle 715-716 of clock 4 therefore generates a second inactive signal on line 172, which supplies shift cycle 717-718 for shift registers SR 1 and SR 2 (see FIG. 10).

In a similar way, inactive signals again run through the hold circuits 130 and 131 and thus ensure the correct shift control of the shift registers SR 3-SR 4 and SR 5 -SR 6 during cycles 719-720 or 721-722 of clocks 2 and 3 , as can be seen from FIG.

The circuit 152 of the ι? ! 'ig.5 received a switch-on signal from the output of the Counter test circuit 126 at the end of time segment 714, when clock signal 3 shows the content of the down counter 124 had counted down to "zero". During the next clock cycle 1, namely cycle 717-718, jo the delay circuit receives a switch-on signal on line 151 and then generates a delayed enable signal on line 150.

At the beginning of time 721, AND gate 177 (FIG. 8) is switched through by a signal on line 150 and by a signal on line 162, the latter input signal representing the SR 7 pointer part for the word X + 1. The Q output of latch 132 is then energized during portion 721-722 of clock cycle 3. The load / shift control 136 now changes on line 175 from a binary zero to a binary one. Thus, the shift register SR 7 and SR 8, the charge / Schiebetorschaltungen be prepared, reindeer a load operation during the period of 723- 724 of the clock 4 durchzufüh-W. In this way, the corresponding bits of word X + 1 in the stages of the shift register SR 7 and SR 8, as in FIG. 13 shown, loaded.

During the time 723-724 of the clock cycle 4, a switch-on signal now appears as the output of the OR gate 133 (by means of the AND gate 135), and as a result, signals run in a time-staggered sequence through the lines 172, 173 and 174, which the charging the shift registers SR 1 - SR 2, SR 3 - SR and SR 5 - SR 6 effect during the corresponding cycle times 1, 2 and 3 in the period 725 to 730 (cf.

Fig. 10).

In this way, the ring counter 128 (Fig. 5) controls the loading and shifting of the shift registers under control by the output signals of the shift registers

50 pointer 123 derived from pointer generator 118 and what is under the control of the clock signals derived from the modulo-eight counters 112 until 4 expires. The transition between load and shift cycles is controlled by a number zero in the

ss down counter 124, because this counter by the clock is lowered. Two Frcigabignals 127, are given to the ring counter! 28, of which the second signal is a delayed switch-on signal triggered by clock 1.

by cycle 713-714 of measure 3 is known

Hiei / Ai S sheet drawings

Claims (4)

Patent claims: 1. Optical printer with serial buffer memory in the output control of the character generation circuit, in which the characters to be generated by a binary-controlled scanning beam are put together in several raster strokes from column segments like a mosaic and in which, in addition to a first saliva device, which the characters to be printed are able to receive as binary coded data at memory addresses which correspond to the spatial arrangement of the characters on the page to be printed, a second memory device is provided, dip is able to output a binary signal sequence determining the light-dark scanning of the scanning beam for each of the characters to be printed and in which the serial buffer memory contains N shift registers with M stages each for the continuous output of binary signals for light-dark scanning of the scanning beam, the first stages of the shift registers being read out sequentially and cyclically and the last Stu fen the shift registers are loaded sequentially and cyclically, characterized in that the data words to be stored in the serial buffer memory are of variable length and that the bits of the data words are assigned to the shift register stages in the following manner Word. ^ For example consisting of N + 2 bits) Bitl
Bit 2 Bit N
Bit N + 1
Bit Λ / + 2 First stage
First stage First stage
Second step
Second step Register 1 Register 2 Register N Register 1 Register2 Word X + 1 (e.g. consisting of N bits) 35 40 through which the loading and shifting of the individual shift registers 1 to A / can be controlled, and that the division remainder can be used to generate a signal (123) for the numerical designation of the shift register in which the loading process for the bits of the next word to be loaded X + 1 has to begin and that each shift register stage is assigned a routing circuit (153) consisting of a logical Link (155,158) for the individual bits of the word to be stored and the possible residual division signals consists, and that the ring counter circuit (128) contains a number of latch circuits (129-132) which of the Number of output clocks of a read clock-controlled (53) modulo-n counter (112) corresponds, with One holding circuit in each case by a division residual signal and by one that can be supplied by the module η counter (112) Clock (clock 1 - clock 4) is controllable, wherein the or the first hold circuit (s) from the output signal of the zero detector (126) and the further hold circuits by the delay circuit (152) delayed clocks can be controlled, and that the load and Shift pulses are available. 2. Arrangement according to claim 1, characterized in that the charge control circuit (153) consists of a Number of an OR element (158) acting on AND elements (155), each of which is one combine the possible residual division signals with one of the bit signals of the word to be stored. 3. Arrangement according to claim 1, characterized in that the length of the modulo-n counter (112) generated clock signals (clock 1 clock 4) is a multiple of the read clock signals. 4. Arrangement according to claim 1, characterized in that during a clock signal (clock 1 cycle 4) 2 shift registers are loaded or their content is shifted. Bit N- 2 Bit N-1
Bit N Second step
Second step Third step
Third step Register 3 Register N Register 1 Register 2 and that for the loading and shifting operations in the shift registers for the next word X + 1 to be loaded, the word length of the preceding word X is added to the register number at which the storage of this preceding word X begins, that the addition sum is added in a division circuit (120) is divisible by the number N of existing shift registers, that with the integer division result, which determines the number of shift cycles for word X before the load cycle for word X + 1 takes place, a clock-controlled (clock 3) down counter (124) can be acted upon and that on reaching the counter country 0 from a detector circuit (i2S) a Signa! is available, through which on the one hand (127) a ring counter circuit (128) and on the other hand a clock-controlled (clock 1) Delay circuit (152) can be applied, which also controls the ring counter circuit (128), The invention relates to an optical printer with a serial buffer memory in the output control of the Character generation circuit in which the characters to be generated by a binary controlled scanning beam can be composed of column segments like a mosaic by light-dark scanning in several grid strokes and in addition to a first memory device which stores the characters to be printed as binary is able to accept coded data at memory addresses that depend on the spatial arrangement of the characters: correspond to the page to be printed, a second memory device is provided which is able to output a binary signal sequence determining the light-dark keying de: scanning beam for each of the characters to be printed and in which the serial buffer memory f ¹ do shift register with M stages each contains for the continuous output of binary signals for bright / dark scanning of the scanning beam, whereby the first stages of the shift register are read out sequentially and the last stages de (15 shift registers sequentially and cyclically loaded who the. The generation of characters for printing or pictorial representation through selection was predetermined