DE2511679A1 - MULTI-TIME SWITCHING SYSTEM FOR BINA-CODED DATA WITH DIFFERENT TRANSFER SPEED - Google Patents

Description

Patent attorney
Dipl.-Phys. Leo Thul

Stuttgart

JT m j_j, » tJ ·

Chatelon

■ SAL STANDARD ELECTRIC CORPORATION, NEW YORK

Time division switching system for mary-coded data with different transmission speeds.

The present invention relates to a time division switch for binary-coded data with different transmission speeds, i.e. one Switching system, the binary-coded signals from transmission channels with different transmission speeds receives, especially from time division multiple channels. The switching system transmits these coded Signals to similar transmission channels on the output side as a result of switching processes that essentially by an orderly time delay of the respective data.

There are many introductions from the area of telephone transmission known. After the amplitude of a speech inioma ^ ion has been sampled and PCZi-coded, a telephone channel composed in this way consists, for example, of an 8-bit word that repeats every 125. On a

7.3.1975
Fk / Mr

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Kultiplex line has space for 32 such channels. To this The purpose is to divide the time course into frames of 125 / U-s each, which in turn contain 32 time slots. During each time slot of about 4, us will transmit a 3-bit word. Time slots with the same Nurraer in successive frames form a time division multiple channel and are assigned to a telephone connection. Such a time division channel can also be used for Data transfer are used and then transfers eight bits every 125 / US i.e., 34 kilobits per second. In the case a data transmission, however, 2 bits of such a word must be used for special purposes (synchronization, parity) be kept ready so that the transmission rate is reduced to 48 kilobaud. That would be the transmission speed Always suitable for data transmission, there would be no special concern in conveying this data Problem arise; the same switching technology as the PCM time division telephone exchange could be used will.

The transmission speeds, which are widely used today for data transmission, are much lower than 48 kBd; In the case of the invention, it is assumed, for example, that the transmission channels in question have a transmission speed of either 9j »£, 2 ₃ i or 0.6 kSd. Such channels can easily be transmitted on the above-mentioned time division multiplex; this can be done by interleaving five 9 _s o> 3d channels, or 20 2.4 kBd channels or -ΞC C, 5 k3d channels, creating a 45 k3i channel

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arise. This channel then occupies an entire time division multiple channel on the time division multiplex line. In the application described below, five consecutive frames accordingly form a frame group with a duration of 625 / US and 160 time slots. Time slots with the same serial number in successive frame groups form a 9 _S 6 kBd data channel. Such a data channel can be either a 9 _S 6 kBd channel or interleaved four 2, ² J kBd channels or l6 nested carry 0.6 channels KBd.

The result of this interleaving is accordingly a time division multiplex line which is used to transmit channels at different transmission _{speeds, either 9 5} 6 kBd, or 2.4 kBd or 0.6 kBd, depending on the data channel under consideration. More precisely, each data channel is assigned a single specific transmission rate, but such an assignment does not constitute a fixed assignment for a given multiplex line. These assignments are time-dependent according to the data transmission requirements. In addition, if, for example, a transmission speed of 0.6 kBd is assigned to a data channel, this data channel can carry up to 16 channels, which do not necessarily all have to be used at the same time; as expected, the actually veri-greare transmission capacity will only rarely be utilized to more than 7Ci.

There are various procedures from the telephone time diversity technology known to carry out the Zextvxelfachvermittlung. One of the easier methods is, at least

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one storage space per connection that is established is supposed to provide and incoming information to be saved on this memory location. The information is later read out from this memory location and assigned to an output channel of the time division multiplex output line which belongs to this channel. The memory locations which are required for the various connections are addressable memory locations in a so-called Speech memory. Addressing means are necessary to address the memory locations of the voice mailbox; to this An address memory is mostly used for this purpose. This address memory has as many storage locations as there are Time quadruple channels on the input or output time division multiplex line gives. The memory locations of the address memory are read out cyclically and synchronously with the time slots of a multiplex line. In this way, each location in the address memory gives one. Address that designates a memory location within the voice mailbox. One arriving at this time Information is stored under the memory cell designated in this way in the speech memory. A corresponding one Address memory is assigned to the output time division multiplex line to indicate which memory location in the speech memory su a specific tent should be read out. The one in the. Save the saved data with the respective connections and will be accordingly deleted when a connection is terminated. A control unit is provided for the provision of these Aare data, which is outside the scope of this invention.

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An alternative to the solution just described is to provide only one address memory, on the other hand the voice memory is occupied with as many memory locations as there are channels on the input time division are; in this way each memory location of the voice mailbox becomes a channel on the ingress timing multiplex assigned. In this case, the memory locations of the voice mailbox are addressed cyclically and although synchronously with the time slots on the input time division multiplex line. In this way, the memory locations of the voice mailbox receive the information one after the other, arriving on the input time division multiplex line. The address memory associated with the output time division multiplex line is is retained; the memory locations of the address memory still contain the information which are required to establish a connection from an input channel to an output channel.

In principle it would be possible to apply this procedure to the Transferring data to be used, this data arriving at different transmission speeds. At the first addressing method (two address memories) would have shown r. the voice memory a number of memory locations, that would be required to process the traffic volume, i.e. corresponding to the maximum number of simultaneous Links. On the other hand, every address memory must have more than 2560 Storage locations have, because a frame group contains 160 lapses of time. The same time slot can in the maximum case up to l6 0.6 kBd channels are used. That's why one must Arrangement of 16 consecutive frame groups or Superframe group to be considered and the address

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a storage space in the speech memory must be available for each of the 2560 time slots within the superframe can be asked. However, such a solution is too expensive.

The second addressing method must for the same reasons the speech memory have 2560 memory locations, just like the one assigned to the output time division multiplex line Address memory.

The task of the present invention is therefore to reduce the amount of memory required.

The invention solves this problem in that at least a first table is assigned to the multiplex lines, which contains the associated transmission rate for each channel and indicates how many channels occupy the same time slot in successive frames ₃ and that a sufficient number of memory locations are assigned to these channels in the speech memory, which are partially addressed with the help of the first tables.

Further refinements of the invention can be found in the subclaims.

The invention will now be explained with reference to figures. Show it:

Fig.-1: a block diagram showing the principle of a ce> annten Represents the time division switch from which the present invention is based,

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Fig. 2: an illustration of how the data channels are interleaved by time multiplexing are constructed

rig. 3 '· a general block diagram of a Zeitvielfachvermlttlungsstelle according to the present £ Lndung _s

Fig. 4: an exact representation of an address circuit, which is assigned to the input multiplex lines and which is shown in connection with that shown in FIG Switching center is to be used,

Fig. 5: Pulse trains to show how the input address circuit works according to Fig. ^,

Fig.6: the representation of circuit which is to be inserted or to remove memory locations from the speech memory in Fig. 3,

Fig. 7: Pulse trains showing the mode of operation of the circuit according to Fig. 6 represent

5: an embodiment of a circuit for correction the content of the address memory according to Figure 3, after either insertions or splits from the Voice memories have been made,

Fig. 9: a table to illustrate how the Circuit CRA according to Fig.

The principle of a known time division switch will first be described with reference to Fig.l. the

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The basic task of such a system is the receipt of coded signals from an input multiplex line KE ₃ and the transmission of these coded signals to an output multiplex line MS. In the following it is assumed that both multiplex lines ME and MS sirEt time division multiple channels for telephone transmission. "The" coded signals that are to be switched represent the speech amplitude in each case. These signals are accommodated in frames of 125 / US, each frame containing 32 time slots. Time slots with the same serial number in successive time frames form a time division multiple channel. Time division multiple switching consists essentially of the optional assignment of different time division multiple channels. In other words, a time division channel Va belonging to the input multiplex line ME must be connected to a time division channel Vx of the output multiplex line MS. The switching system receives the coded information of the time channel Va during the time slot ta in each frame on the time division multiplex input line ME. This voice information must be transmitted to the time division multiple channel Vx, ie it must arrive in the time slot tx of each frame of the output side multiplexing line MS.

For the sake of simplicity, it is assumed in the following that the transmission speeds are essentially for both timing lines ME and MS are the same, so that the time ta lie is assigned to the time division multiplex line ΚΞ :, is always followed by the time tx. The mediation principle used consists; in providing a voice memory MC which contains addressable memory locations, such as z.3. cc, and to allocate such a storage space to each connection.

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At time ta, the encoded speech information or the coded word coming from the input multiplex line IiE stares, written in the memory space cc. While of the time slot tx, the word stored in the memory location cc is read out and transferred to the output time division multiplex line MS transmitted. In this way, each memory location in the voice mailbox MC becomes a different one Connection assigned. In this way it is possible to make up to 32 connections. In Fig.l are also the facilities shown that allow everyone Connection to allocate a memory location, which also allow, for example, the memory cell, cc during the Timeslot ta is addressed to a write operation and during the timeslot tx for a readout operation will. As a first embodiment, two address memories MTE and MTS were chosen, the ones Provide addresses that are required for the writing and reading operations with the voice memory MC will.

The address memory MTE has as many memory locations - as many time division channels on the input time division multiplex line - ir.g ME. Each memory location of the address memory MTE is assigned to a time division multiple channel and stores the Address eir.-ΞτΞ memory location of the voice memory MC, the this time division channel is assigned. In this way the memory location cta stores the time division channel VA ctigecrcnet is the address acc of the memory location cc. The memory locations of the MTE address memory are read cyclically and synchronously with the Time slots of the input time division multiplex line ME to

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thereby defining the address of that memory cell of the speech memory in which the coded combination is to be stored, which arrives at the respective time on the input time division multiplex line ME. The address store MTS has a similar structure to the MTE address memory. Only its content is different. The memory location ctx which is assigned to the time division channel j thus also contains the address of the memory location cc. In this first embodiment, the number of storage locations in the voice memory MC can be the same be as large as the maximum expected number of simultaneous connections. The time division channels used of the input and output time division multiplex lines occupy these memory locations. For unused time diversity channels the address memories emit specific information that prevents switching operations. A second embodiment provides that the voice memory MC has as many memory locations as Time division channels are present on the input time division line. It follows that every input time division multiple channel a memory cell can be assigned, with the address memory MTE by means of a simple Time multiple channel counter can be replaced. The counter is switched forward by one step for each time interval and thus supplies the address of the memory cell which is assigned to that time slot that is in the next Time slot is included. The output address storage MTS, on the other hand, is retained and is used to store switching information. The address storage device MTS can of course be replaced by a counter and the address memory MTE can be retained if this.

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seems necessary. If this is carried out, this means that the memory locations of the voice memory MC correspond to the output multi-channel channels be assigned.

Eas shown in Fig.l switching system is based on Multiplex lines, whose channels each have a time slot occupy a frame. The present invention maintains these principles but is concerned with individuals with multiplexed lines carrying time division data of more complex structure, in particular whose structure changes constantly. Fig. 2 shows the time division structure a multiplex line. On the line T 80 successive frames T1 to T80 are shown. The frame T1 is represented in more detail by the line V. The frame T1 consists of 32 time slots V1 to V32. Of the Time slot V1, for its part, is again shown by line W. It consists of eight bit positions wl to w8, which are used to form a word that consists of eight bits. Bid here corresponds to the structure under consideration the structure of a usual time management with 32 Telephone channels.

For data transmission use, five consecutive Frame summarized and form a frame group Ml. The frame group Ml thus contains 160 time slots and · kar.r. tiani-IcO data channels. If, as with Telefonar.weniur.gen usual, a frame a duration of 125, us has: a frame group Ml has a duration of 625.us and the same time slot reverses cyclically 10000 times per Second again. This time slot becomes eight bits transfer. As with the consideration of data transmissions

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usual, it is assumed that among these eight bits there are- ' at least one bit is used for synchronization purposes, while the other, generally the last, is used for transmission a parity signal is used. It follows that a data channel of the Rahsiengruppe Ml at a transmission speed of 5 χ l600 = 128OO bits per second a data transmission channel with 9600 bauds or 9.6 kBd.

Such a transmission speed is with regard to on data transmission is relatively high, therefore transmission channels must have lower transmission speeds to provide. Suitable transmission speeds for such channels would be e.g. 2.4 or / and 0.6 kBd.

For this purpose, a new frame group M2 is formed from four frame groups M1. Accordingly, there is a frame group M2 of 20 frames, e.g. frames T1 to T20. A time slot of the frame group Ml appears . accordingly four times in frame group M2. However, it is not assigned to a data channel with 9.6 kBd, but rather serves four data channels with 2.4 kBd each at the same time.

A second group formation provides that 16 frame groups Ml Eusanm-en are included ₃ and form a frame group M3, A same urine group M3 contains 80 frames, e.g. the frames Ti eis Tc-O► A time slot of the frame r.gruppe Xl appears accordingly l6 Time in the Rahner.gr up pe j-13. However, it is not connected to a data channel with 9.6 kBd, but also serves 16 data channels with 0.6 kBd each.

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Based on the group formation carried out here. the data transfer carried out here on a Frame group consisting of five telephone frames with l60 Time slots. Each time slot can be assigned to a data channel, which either has a data stream of 9 * ά kBd or 2.4 kBd or 0.6 kBd is used. In foreseeable typical applications, some data channels cannot be permanently assigned to one of these transmission speeds. The transmission speed depends on the specific requirements of the particular transmission. A possible However, there is a restriction that a data channel has a transmission speed that is specified once and does not fully utilize the capacity made available.

In this way one can imagine that on such a multiplex line 80 data channels with 9.6 kBd 80 Channels show that ΐ6θ data channels with 2.4 kBd 40 Occupy channels and that 640 data channels with 0.6 kBd occupy the last 40 channels. Each channel would include one of the three possible transmission speeds can be operated, but without a systematic order egg? Iar.algru? pation to perform.

Ξ3 will only. ~ r. £ assumed that of the total of 880 for Available data channels a maximum of 700 channels can be used simultaneously. The number can be of the data channels with 9.6 kBd or 2.4 kBd under certain circumstances can be increased, but not the number of 640 data channels with 0.6 kBd, thus the maximum number

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of 700 is not exceeded. It is in the following It will become clear that this limitation is of only minor importance Meaning is. If one now looks at the switching system again der Fig.l and its application to input and output time multiplexing lines that have just been described became, divers, immediate trouble. In connection with the first exemplary embodiment the voice memory MC can be adapted to the number of available channels, i.e. up to 700 connections can be produced. In contrast, the address memory requires at least 256O memory locations, namely one Storage space for every possible data channel as it is not possible to predict which data channels will be used. One must therefore assume that each data channel is available for 16 channels with 0.6 kBd.

In the second exemplary embodiment, both the voice memory and the address memory require 256O storage locations.

Such elaborate memories caused corresponding costs, it is therefore also an aim of this invention to reduce the costs due to an excessive number of memory locations su * The system shown in FIG and an address memory MI ¹ S contains. In this case, however, it is ge lunger. To slow down the number of memory locations in these two memories to the number of assignable channels; lies is explained in more detail below.

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The voice memory MC has 160 sectors STO to ST159 Each sector is a data channel of the input time division multiplex line Assigned to ME.

It will first be explained how the coded data are written into the voice memory MC from the time division multiplex line ME. Furthermore, in order to emphasize the principle of the invention in more detail, it is assumed that each sector in the voice memory MC has as many memory cells as there are channels conveyed on the assigned data channel, regardless of whether this channel is occupied or not.

The main problem is addressing. A table TVE to identify the input transmission speed is used to solve this problem
Address circuits CAE.

The TVE table has as many storage locations as
Data channels. Each memory location contains information about the information assigned to the respective data channel
transmission speed, ie, either 9.6 or 2, ^ or 0.6 k3d. During each time slot of the
'Eahr.er.gruppe Mi of the input multiplex line ME , the assigned memory location is read out and its content is transferred to the address 33 5r.3 2Haltung CAE.

The addressing circuits CAE essentially contain a channel counter CV, a channel group counter CM and a selector pointer PS.

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The channel counter CV has l60 position and is increased by " advanced one step for each time slot of the Rahngruppe Ml. Accordingly, it specifies the number of the currently available time slot, in other words, it specifies the number NV of a data channel between 0 and 151.

The frame group counter has 16 different positions and becomes the input time division multiplex line for each frame group Ml ME switched by one level, i.e. with each cycle of the channel counter CV. He gives one Frame group number NM3 from 1 to 16, corresponding to the rank of frame group Ml in frame group M3. He gives likewise a frame group only NM2 from 0 to 3 according to the rank of the frame group Ml in the frame group M2.

The following explains how these components work together.

At the time of the first time slot within the first frame group, both counters CV and CM and also the sector pointer PS at level 0. The counter CV is now used to store the first memory location tveO from table TVE. This memory cell contains an Ir.fomation with which transmission speed that data channel is operated, which this first. Guide slot occupied, e.g. 2.4 k3d. From this Information follows that the considered data channel as a whole carries four channels and therefore the sector STC contains four memory cells. At the same time the counter CV to the. Position 1 switched.

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The address of a memory location in the voice memory MC is obtained from the status of the sector pointer PS (0) and the value NM2 (0) are added, which is due to the information from the TVE table. In order to the first memory location of the STO sector is occupied.

The information that arrives from the time division multiplex line ME is written into this memory location.

The information regarding the transmission speed, which was given by the table TVE, causes at the same time that a value 4 aim counter reading of the Sector pointer PS is added, whereby the address of the first memory location in the next sector ST1 is determined is.

During the next time slot, the counter CV causes the memory location tvel (not shown) of the table TVE to be read out and it is now assumed in the following that the information contained therein _{indicates a transmission speed of 9 9} 6 kBd and thus at the same time a number of an individual Storage space in Sel-ctor STl, since the corresponding data channel only carries one information channel. The counter CV is then switched to position 2. The address in the voice memory MC is similarly determined that a value 0 is added to the value of the sector pointer (4) as a result of the information about the transmission speed; this is the address of a single memory location in the sector STl. The incoming information is stored under this address in the spray memory MC.

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According to the information about the transmission speed a value 1 is added to the content of the sector pointer PS at the same time (4 + 1 = 5).

The method runs in this way for all subsequent time slots. It is thus possible to address a memory location of each sector per time slot of a frame group of the input time division multiplex line. The first memory location of each sector is always addressed in the first frame group. The second memory location of the sector is addressed in the second frame group, unless the sector concerned contains only one memory location that is used in each frame group, ie, a transmission speed equal to 9 ₃ 6 kBd. In the fifth frame group, the number NM2 is again 0. The addressing always relates to the first storage location of sectors that have only four storage locations, while the fifth storage location of those sectors that have a total of 16 storage locations is addressed. Storage locations of sectors that are assigned to data channels, which serve a total of four information channels with 2.4 kBd each, are accordingly occupied alternately. The same applies to sectors that are assigned to data channels, each of which has 16 information channels nit - _s £ kBd, such sectors containing 16 storage locations.

The arrangement according to the invention, which has been described above, allows with a channel arrangement on the input time. Multiple line ME with 80 information channels nit 9, ο kBd

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160 information channels with 2.4 kBd and 640 information channels with 0.6 kBd that the voice memory MC only needs 8S0 memory locations. The addressing devices described allow each of the 880 memory locations of the voice mailbox MC to use one of the 880 data channels and control the time allocation of the channels to the memory locations.

These stored data are to be passed through the switching process to channels of the output time division multiplex line MS are transmitted. For this it is first necessary that for each channel on the output time division multiplex line a memory location of an address memory has to be read out. The Address is the address of a memory location within the voice mailbox on which the information to be conveyed is stored is stored. The problem of access to the memory locations of the address memory in accordance with the Ausgar.gszeitfachleitung corresponds to the problem of access to the memory cells of the speech memory in Match with the input timing multiplex as described above. Accordingly, they are the same Solvent provided, namely a table TVS, the information about the output transfer speed stores, as well as output addressing circuits CAS. The mode of operation of these circuits does not need to be explained in more detail to become.

The switching system shown in Figure 3 allows it perform time-division switching for data that is transmitted at different transmission speeds

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Switching system arrive. There are only two Memory used (voice memory and address memory), the capacity of which is limited to the maximum number of usable Information channels on the two multiplex exhibitions is limited, regardless of whether they are occupied or not.

However, the switching system shown encounters difficulties when there is a change in the transmission speed of the information channels involved. If, for example, the transmission speed of an input _{information channel changes from 9 9} 6 kBd to 0.6 kBd, the assigned sector in the speech memory must be expanded from one memory location to 16 memory locations. It follows that if the above-described arrangement of the sectors within the voice memory MC is retained, each subsequent sector within the voice memory MC must be advanced by 15 memory locations. Such a process is possible in principle, but if carried out there would be the risk that already existing connections would be disturbed. In addition, it must be taken into account that the memory SSG have memory spaces available for a maximum number of 700 connections, which enables further savings in terms of the memory design.

Therefore, provides an advantageous embodiment of the invention proposes that the number of storage locations in each sector is limited to only that many storage locations as for the caching of a maximum of 700 connections

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is required. For this purpose, the invention provides two further tables, namely an input table TTE and an output table TTS. These tables are also shown in Figure 3. The table TTE contains how the table Τ7Ξ l60 memory locations simultaneously and using the same devices as the memory locations from table TVE. As a result, each storage location in the TTE table becomes a data channel assigned. A memory location stores a 16-bit word, each bit indicating which time slots among the a total of 16 time slots of this data channel are occupied.

In other words, if a considered data channel in frame group 0 is occupied, the corresponding bit is equal to 1. If this is not the case, this bit is equal to 0. The same applies to the other bits that are assigned to the other 15 frame groups, that is, If a data channel is occupied by a 9 _S 6 kBd channel, the value of each bit is equal to 1. If the data channel is occupied by 4 2.4 kBd channels, of which only the second is active, the bits with the serial numbers have 1 , 5, 9 and 13 have the value 1, the other bits the value 0. If the data channel is occupied with 16 0.6 kBd channels, each active channel is characterized with a bit with the value 1.

If several channels are active on one data channel, can they be arranged like the Rahn groups, to which they belong. The storage locations in the corresponding

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Sectors in voice mail are assigned accordingly,

The introduction of the tables TTE and TTS make a change in the address calculation necessary. The number of storage locations required in each case within a sector is produced in that either 1, 4 'or 16 bits are selected in the corresponding word within this table in accordance with the information about the transmission speed. This corresponds to a transmission speed of 9 ₃ 6, 2.4 or 06 kBd, which is specified in the TVE table. The number of bits with the value 1 in the table TTE or TTS is the number of memory cells in the sector concerned and this number is added to the respective content of the sector pointer PS in order to advance it and, at the required time, the address of the first memory cell in this sector.

The following numerical example is intended for a better understanding of the invention are given: on the assumption that the data channel under consideration has a total of 16 0.6 kBd channels two questions arise:

Is the relevant channel, the rank of which is indicated by the number NM3, active?

At which point within the assigned sector is the storage cell belonging to this channel, if do you consider that only active channels are allocated memory locations?

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The answer to the first question is obtained from that Bit in the word within the table TTE or TTS is determined, which corresponds to the number NM3.

The answer to the second question is obtained from the fact that the number of bits in this 16-3it word corresponds accordingly of the number NM3 are selected and that the number of i values of these bits is counted, i.e., the number of the active channels up to the channel in question. This obtained number becomes the content of the sector pointer PS added.

The means for acquiring addresses will be described later in detail with reference to FIG.

The arrangement according to the invention limits both the capacity of the speech memory and the address memory to what is absolutely necessary. This reduction outweighs the introduction of tables. These tables have also the advantage that, through their use, the channel division and subdivision on the time division multiplex lines can be changed without disrupting existing connections.

Fig. ¹ + shows; an embodiment of the address circuits CAE using the table TVE and the table ΤΊΞ, which is shown in Fig.3. The pulse trains shown in FIG. 5 represent the control signals which occur in the circuits of FIG.

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In FIG. 4, the two tables TVE and TTE are in a singang memory MPE summarized. The input memory MPE has an input ent, an output stt and two control lines Ii and 11. If the line Ii is a control signal which consists of the signal int and the address adin, the information pending at the input becomes written in the storage cell of the memory, which is indicated by the address adin. When the line 11 receives a readout control signal lect, as well as an address adl, the content of the memory location specified by the address adl is read out and delivered to the output stt. As has been described in connection with FIG. 3, each memory location is structured in such a way that it provides information about the transmission speed stores (in the TVE division) and a 16-bit word (in the TTB division). The memory MPB contains l € 0 storage locations, that is, one storage location per Time slot of the input frame group.

An input register RET is assigned to the memory M? B, which in turn is loaded from a register RTMT with the aid of a pulse cct, as described below as well as an output register RST, which can be opened with the help of of a lect pulse is loaded when a readout operation should take place in the MPE memory.

The register ΕΤ.-ΓΓ is in turn loaded by an Ieri ^ raleir.-unit UC, and in turn loads a further register RAHT with the aid of a pulse csr. Furthermore, an address register ADI is provided, a channel or time slot _{counter CV 5} a fiainaengroup counter CL "tvsr-

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same Pig.3), a circuit TOT, an adder circuit ADDj of the sector pointer PS and various logic circuits (Decoders, gates).

The operation of the arrangement shown in FIG
a clock HGT controlled, which is normally a
Receives signal syit and responds to it by emitting signals sit, lect, tcal, tea2, tspl and tsp2. Receives
the clock HGT also sends a signal cct, it also emits a signal int. These different signals are shown in the form of pulse trains in. Fig.5.

First of all, it is assumed that no rearrangement of the channels is required on the multiplex lines. As a result, the cct signal is absent. At the beginning of a
Frame group on the input multiplex line ME (see FIG. 3) j are the two counters CV and CM and
the sector pointer PS in its O-Posfcion. Reset devices, not shown, can be used in a known manner
and restore this state at the beginning of each frame group in order to eliminate any errors.

Each pulse syit that is received from the clock generator HGT corresponds to a time slot that arrives on the input timer multipiex line. When such a pulse occurs, the clock generator HGT emits a signal lect that
is transmitted via the line 11 to the memory NPE, whereupon a readout operation begins. The address ail is the position (0) of the counter CV. This address assesses

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that the first storage location of the MPΞ memory is read. At the same time, the register RST, which also receives this signal lect, is able to record the content of this memory location. When the lect pulse stops, the clock HGT emits a signal sit which switches the counter «CV to the next position (1). This change takes place at the end of the impulse.

As mentioned above, the memory cell contains the has just been read out, information iv about the transmission speed and a word mt. The word mt consists of 16 bits and is assigned to the time slot ITO, this is the data channel VDO. The data channel VDO contains further time slots ITO in the next Frame groups and thus divides the 16 time slots ITO into the 16 frame groups, which in turn form a frame group form. Each bit of the word mt is assigned to one of these time slots ITO. The value of such a bit equals 0 if the time slot is not from one active channel is busy. The value of such a bit but is equal to i if the time slot is from one active channel is busy. The information iv about the transmission speed consists of two bits with following interpretation:

C3 = error Oi = O ₅ 6 kBd

IC = ^ - kBd 11 = 9 * 6 kBd

In the following it is assumed that the time scale ITO is used for 0.6 kBd channels. That means that the € Time slots ITO in each frame group one separate 0.6 kBd channel are available.

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The left of the currently pending frame group is indicated by the position of the counter CM (0); a DMO decoder marks one of 16 lines mtm (in this case the first). Gate circuits pac test this information and the word mt bit by bit. In this way the first bit gets on a line vai. If the value of this bit is equal to 1, the relevant channel is active and the data arriving on the input time division multiplex line must be stored in the speech memory. The signal vai controls this write operation, but the address of that memory cell ₃ which is to receive the incoming information must still be calculated.

The position cm of the counter CM also becomes a decoder DVS made available, which also receives the information iv about the transmission speed. the The working principle of the DVS decoder is defined in the following table:

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It can be seen that the decoder DVS outputs a word dvs which consists of Io bits with the fourth 1 if the transmission speed is 0.6 kBd * whose first 4 bits have the value 1 if the transmission speed is 2 _g ^ KBd and from only the first bit has the value 1 if the transmission speed is 9 _t 6 kBd. ■

As an example, assume that only one bit has the value gate circuits trs switch. The word dvs together with the word mt through ₅ after they have been activated by a signal tcal. The result is a word that has only a single bit with the value i contains * This word is sent to a TOT circuit that adds the bits with the value 1. When the circuit TOT receives the tcal signal, it determines the number of bits with the value 1 within the pending word and subtracts one unit from the total. As will be described below, this correction must be made in order to take into account the position of the index counter. The circuit TOT outputs a 4-bit word, which is labeled tot and in the example under consideration necessarily has the value 0000. The adder circuit ADD receives this word tot and a binary value bis, called the sector index, which is equal to 0 in this example. The sum output by the adder circuit AZD consequently has the value 0.

At the end of the tcal signal, after the TOT and ADD circuits have had enough time to perform their operations, the sum add is transferred via gate connections pad, which are activated by a signal tca2. the

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Sum add is then written into the address register ADI, to which the language memory NC has access.

In the example under consideration, the value of the address adi calculated in this way is equal to 0. This is then the address of the first memory location in the STO sector of the MC voice mailbox. This space is used because the accompanying signal vai is present.

If the channel under consideration were not active, the result of adding the circuit TOT would be the same, namely a Signal with the value 0000, but a signal vai would not occur.

If the considered time slot is available to a channel with a different transmission speed, Regardless of whether this is active or not, the address calculation described above still remains valid, because the word dvs is composed of one bit with the value 1 and 15 bits with the value 0 in both cases so that the circuit TOT cannot produce a value other than 0000.

J by He synchronization of the clock HGT with the occurrence of the time slots on the Eirigangszeitmultiplexleitung Ι-ΙΞ (Figure 3 "'it is ensured that the signals arrive vai and adi at the appropriate time to the voice memory MC to the ankcr ^ ner.den data in to register this ..

In addition, the clock provides a signal in this case tspl. Furthermore, the information about the transmission speed processed by a decoder DS, whose

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Operation shown in the following table:

011111111111111111

10 1111000000000000

11 1000000000000000

Gate circuits ps switch the word mt and ds "through, if these were made available by the decoder DS and if the isolating circuits are activated by the signal tspl have been. In the example under consideration, the entire word mt is accordingly transmitted to the circuit TOT. In the second Pail receives the circuit TOT a signal tpsl and adds the number of bits with the value 1 in the received word without subtracting a value. That way will the number of 0.6 kBd channels found in the data channel VDO are active. The circuit TOT accordingly outputs a value tot, e.g. 13. The adding circuit ADD therefore outputs the sum 0 + 13 = 13 at its output add, because the sector counter PS is in the position 0.

If the time slot ITO had carried a maximum of 4 2.4 kBd channels, only the first 4 bits of the word ds would have been allowed through the gate circuit ps, which characterize the state of these four channels. A ^r 3r_r - if a 9 ₃ 6 k3d channel were assigned to a time slot, only the first bit of the word rat could have passed through the gate circuit ps.

Finally, the signal tsp2 controls the inclusion of the value add (13 in the example) 'in the sector pointer PS,

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which then makes this value available as a new index. This is the processing of the time slot ITO closed. As can be seen from Figure 5, the next time slot ITl already started before these operations are finished.

Since the counter CV has now moved one step forward has been, the next word is read out from the memory MPE. In contrast, the counter CM is still there in position 0. The address calculation of the address adi remains unchanged until the adding circuit ADD.

Since the time slot ITO serves 13 active channels, there are therefore 13 storage locations in the STO sector of the voice mailbox MC assigned (Fig.3) · The sector STl begins at Address 0 + 13 = 13, which is indicated by the sector pointer PS. The adder circuit ADD receives this position and counts them dead for information. This creates the address adi.

The sector pointer PS is advanced by a certain number of steps that corresponds to the number of channels corresponds, which occupy the time slot ITl. This process makes sector indices available, which specify the first memory location within a sector, this value is included in the calculation of the address adi is received, according to the time slot to which this Se> ~ cr assigned.

In the last time slot of the first frame group there is the Counter CV from a signal rzm which resets the sector pointer PS. The calculation of the sector indices is repeated

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accordingly from frame group to frame group. In the first time slot of the second frame group, the counter gives CV a signal sim from (being switched to the next position by a signal sit), and the counter CM becomes moved one step further.

During the second group of frames, the first two bits of each word mt are affected by the address calculation. This is an effect of the operation of the decoder DVS, as already mentioned above, except in the event that the Time slots can be used for a 9 »6 kBd channel. In in this case the circuit TOT will generate either a value 0 or a value 1, which is used for addressing either the first memory cell or the second within a sector which is assigned to this time slot.

In contrast, the setting for the sector pointer PS does not change.

During the next frame group, the described operation is repeated, the counter CM advances step by step and thereby takes into account an increasing number of bits in the word mt, this number changing four times from 1 to U for data channels with 2.4 kBd channels and only once from 1 to 16 for data channels with 0.6 kBd channels.

Finally, it must now be considered how a change in the composition of the time slots affects the input time-specific line. Such a change, as described below, only affects one channel at a time. This channel will either

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switched on or off. A change in the transmission speed is a special case that is handled when the relevant channels are not active are.

As far as the memory MPS is concerned, such a change (see Pig. 4) only affects a write-in operation. This information is first written into a register RTMT by the control unit UC. if the relevant rearrangement must be carried out in the memory MPE, the voice memory MC emits a signal cct. The content of the register RTMT is then partially stored in the register RAMT, namely the address of a word MT to be replaced and another part, entered in the register RET, namely the Word to be saved.

In response to the signal cct, the clock HGT gives a pulse int on the during the next cycle Line on line Ii. The word stored in the RET register is then changed to that of the register RANT registered address given.

In the above description it was indicated how the input addressing circuits CAE the Pig.4 an address adi and a confirmation signal during each time slot vai make available in order to facilitate the feed-in on the input time multiplex line ME ar.kc-ler.den To cause data to a suitable storage space within the voice memory MC.

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As already mentioned in the description of Fig. 3, it is by similar devices possible in output addressing circuits CAS adlt an address for each time slot and to receive an acknowledgment signal valt for doing so read out one of the memory locations of the address memory MTS. The information of this memory location gives for each time slot an address adr and a confirmation signal val with the help of which data is stored from the suitable memory locations of the voice memory MC can be read out.

These processes are analogous to those described above and therefore do not need to be explained in more detail here.

Fig.6 shows an embodiment of the circuits that the Memory MC are assigned (see Fig. 3) · These Circuits are used to determine the number of storage locations in a sector corresponding to the number of data channels either to increase or decrease if one of the channels carried by this data channel is grounded is either turned on or off.

For this purpose, the memory MC has an input EN which is used to write data into the voice memory MC serves as well as an output ST for reading out this data.

The memory MC carries out a readout operation in a known manner through when it receives a readout control signal lec. This signal lec must ceglide from an address A3 which indicates the memory cell whose content: must be read out »At the end of the time slot, the *

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was determined by the signal lec, is the information stored in the affected memory locations of the speech memory available at output ST.

Correspondingly, a write operation is controlled by a signal ins which is coupled to an address AD is. The information applied to input EN is then written into the addressed memory cell.

Two registers RD1 and RD2 are assigned to the memory MC, which are used for the intermediate storage of data. For one Readout operation in the memory MC, the register RDl also receives the signal lpe and is designed such that it receives the information that is available at the output st after the end of the signal lec.

A read-out operation is always followed by a write-in operation. When a gate circuit prn through a Signal crn is prepared, the stored in register RDl Information is sent back to input EN and can be recorded in the same memory cell of memory C. if the address has not changed.

During the write-in operation described, the register RD 2 can receive a control signal dec and in this In this case, the transmitted information under consideration is read into register rd2.

The register rd2 "is connected to a gate circuit prd, which is opened by a signal crd during a write operation, so that the data contained in register RD2

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return to the Eil input in order to be stored in a memory location in the memory MC (instead of the information in the register RD1).

The arrangement of the two registers RD1 and RD2 allows information from an address X in the memory MC read out and transfer this information 'to the register RD1. During the next step these Transfer data to register RD2. During the next readout operation at address XM, a second Data information stored in register RDl. Finally, during a subsequent write operation that the second readout operation is followed by the first data combination that was previously read out under the address and was temporarily stored in register RD2, “rewritten under address X + I. These bodies allow, starting from address X, a storage location with address X step by step to make available that the content of all subsequent memory cells is pushed forward by one space, and although by the fact that the information of a memory location on the respectively by the method described above next memory location is brought. These devices serve to divide a storage space into a sector insert, including the postponement of all following Storage space is required.

Conversely, to withdraw a Speieherplatz from a sector, a backward shift of all following storage locations is required, but none are required for this special devices provided. It is enough

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for this purpose, to read out a data combination under the address X + 1 during a readout operation, they thereupon to be written into the register RD1, and then, during the next write operation, the gate circuit pm to activate by the signal crn, while the address X replaces the address X + 1. By the step-by-step procedure from the address X + 1 becomes the memory location with the address X from the relevant one Sector removed and the end result is a general shift back of all of the following Storage locations with direction to the removed storage location.

Furthermore, the multiplex lines ME and MS are assigned to the voice memory MC for switching purposes. More accurate In other words, the input time division multiplex line ME is assigned to the input EM via a gate circuit PIN, which can be activated by a signal on during a read operation. Then the data combination, which arrives from the multiplex line ME, are brought to a memory location in the voice memory MC corresponding to the address AD. The output time division multiplexing line MS receives the data combinations from a transmission register RM. This register RM is supplied by the register RDl, via a gate circuit tem, the prepared by a signal acir. In this way, a data combination arrives as a result of a readout operation in the voice memory MC under a specific address AD first in the register RD1. Via the gate circuit pem it arrives at the register REI-I ur.i afterwards it is transmitted to the output time division multiplexing IiS.

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It should also be noted that up to this point it has been assumed that both multiplex lines ME and MS are bit-parallel Transmission of the data combinations are designed, although above (see Fig. 2) by serial transmission was assumed. Therefore, they must be in suitable places Transfer devices are inserted, e.g. can the register REM be a shift register that is loaded in parallel, but its contents serially on the output multiplex line MS is read out.

The device according to FIG. 6 also contains a buffer register RTMC which is loaded by the central unit UC and is used for rearrangement purposes (insertion or separation of a memory location). A control register IRMC, which is loaded from the register RTMC, a counter CIR, which is advanced by pulses acir, a register RAR, which is loaded from the counter CIR, as well as address circuits LCA and several gate circuits and comparison circuits are also provided.

The operation of the entire arrangement of Fig. 6 is controlled by a clock HGC, which receives the signal syit and in turn signals leir, inir, led, ind and acir provides. These signals are shown in Fig.7 shown.

As long as no clutter on the input or output time division multiplex lines are made, the operation of this device is relatively simple.

Each pulse syit corresponds to both a time slot on the input time division multiplex line and a time slot

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on the output time division multiplexed line. That's why im Speech memory both write-in operations and read-out operations are carried out. These operations are controlled by the signals led and ind of the clock HGC.

During each time slot the address memory gives MTS an address adr and a confirmation signal val (if a data combination is read out, and then to be transmitted to the output time division multiplex line MS). The input address circuits generate accordingly CAE an address adi and an acknowledgment signal vae (if a data combination from the incoming time division multiplex line ME should be enrolled).

The address circuits LCA receive the signal led. If the signal val is also present, the circuits generate LCA a signal lec. At the same time, the address adr is transferred on like an address AD. The readout operation is carried out. However, if there is no confirmation signal val, a signal red is sent from the address circuit LCA generated; the signal rzd resets the register RDl, whereupon an O-combination on the output time division multiplex line MS is transmitted. This operation can be described with respect to the address look-up LCA as follows using known logical link symbols;

les = led.val

AD = led.adr (1)

rzd = led.val

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The read out data combination (or O-combination) is stored in register RDl. A little later, when the signal acir. Arrives, it is transferred to the register RM and stands there for the onward transmission on the output time division multiplex line MS available.

The address circuit LCA receives the signal ind when a confirmation signal vai is present at the same time, the address circuit LCA generates a signal ins. At the same time, the address adi continues like the address AD transmitted and a signal provided.

The write-in operation is then performed. This can be represented as follows:

ins = ind.vai

AD = ind.adi (2)

a = ind.vai

After the gate circuit pin has been activated, the incoming data configuration from the input time division multiplex line ME can be written directly into the voice memory MC.

If e.g. 3. one channel on the input time division multiplexed line the register RTMC is to be activated a corresponding command from the central unit UC. To simplify the description, the following is used assumed that äa_3 transferred this command to the IRMC register via a gate circuit prm which is activated by a signal dmm (this signal becomes

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provided by synchronization devices associated with the input time division multiplex line ME and here cannot be described in more detail). The signal dmm is before the beginning of a frame group and can possibly be the Reset the CIR counter and the RAR register.

The corresponding command (compare FIG. 6, box IRMC) contains an address AIR and a command CI ₉ but no command CR. The command CI indicates that a memory space must be made available in order to be able to switch a new channel to active. The address AIR specifies the position that must be assigned to this memory cell to be newly inserted within the speech memory MC; it is now assumed that the address AIR has the value X, as already mentioned above. For this reason, each subsequent storage space must be shifted by one space.

In order to achieve this goal without endangering existing connections, all contents of Storage locations from the storage location with address X including moved while the addressing circuit LCA corrects the addresses used for the mediation process are required (adr and adi). As soon as the content of the memory location with the address X on the memory location nit the Airesse X + 1 has been transmitted, is the closer data connection via the same connection mediate the memory location with the address X + 1, whereas the addressing circuit CAE and the address memory MTS continue to reduce addresses adi and adr with the value X ^.

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The principle for shifting the storage locations was As already described above, the registers RD1 and RD2 are essentially involved in this. This process is carried out by the addressing circuit LCA is initiated as soon as it has received the signal ei, which reports the command OI.

The clock HGC emits a first signal leir. the Addressing circuit LCA receives this signal and emits a signal when the signal ei is present at the same time lec from .. At the same time, the address circuit LCA outputs the information cir (equal to 0) from the counter CIR as an address AD continues. A readout operation now takes place. These can be represented as follows:

lec = leir.ei
AD = cir.leir.ei ^ '

The information read out from the first memory location of the voice memory MC is stored in the register RDl, Then the clock generator HGG emits a signal inir »Since the signal ei is still present, the addressing circuit reacts LCA by sending a signal to the. At the same time, the address AD is retained and the signal crn is output, in the. Link the output of the register RDl with the input EN su. A write-in operation is now performed. Tlese can be represented as follows:

ins = inir.ci

AD = cir.inir.ci crn = inir.ci

The information read out when the signal leir occurred

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is rewritten at the same address when the inir signal occurs. These operations have the Switching process not affected and a data combination is selected according to the signals led and ind, .. then another data combination is generated by the in the Porael groups (1) and (2) represented relations inscribed. The counter CIR is incremented by the pulse acir.

The operations shown in formula groups (3) and (4) are carried out for each time slot, until the counter CIR reaches a position X which corresponds to the address AIR, which is stored in the register IRMC is. This state is detected by a comparison circuit CIR / AIR, which receives the information cir and air, and emits a signal cppa if cir is less than air, a signal cega if cir equals air, and a signal cpga, if cir is greater than air. A gate circuit pepg connects the two signals cega and epga and forms them from them a signal ddc which indicates that cir is greater than or equal to ari.

The signal ddc is transmitted to the address circuit LCA until cir is equal to air. The by the formula group (3) The readout operation described is not changed. The following interest chopping operation, which was previously carried out according to the Forme1 group (4) has been carried out is changed, however, wsil a signal crd is generated instead of the signal cm. Through this the output of the register RD2 is linked with the input EN. Since this register up to this point in time was not used, an O information will be sent to the address X.

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enrolled. The modified operation is described as follows:

ins = inir.ci

AD = cir.inir.ci (5)

crd = inir.ddc.ci

Of course, the use of the formula group (5) includes the use of the formula group $) in this respect when there are differences. The same also applies vice versa. The formula group (4) must also have exclusion conditions included that are not mentioned in order to simplify the description; any logical condition was therefore only mentioned insofar as it made a positive contribution to the operation in question perform. This type of description is also retained in the following.

After that, the signal led controls a readout operation, that of a write-in operation controlled by the signal ind is followed. If address X is not affected by these operations, there is no reason to deviate from their logical course given in formula groups (1) and (2). Only to the formula group (1) There is still the fact that a signal dec is generated by the signal led in the address circuit LCA becomes, which can be summarized as follows:

lec = led.val

AD = led. Adr _fezy

(ο)

rzd = led.val
dec = led.ddc.ei

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This enables the when of the signal inir to retain the information read at address X and to rewrite it at address X + 1.

If, on the other hand, these switching operations relate to the address, the logical combination according to formula group (6) and / or (2) must be deviated from. The match is discovered in the comparison circuit CIR / AD, which in this case receives one of the addresses adr and adi via an OR circuit pali in the form of an address ali and a value cir. The comparison circuit CIR / AD outputs either a signal appc (ali ζ cir), or a signal aegc (ali = cir), or a signal apgc (ali> cir).

If the corresponding operation is a read-out operation, the information to be read is already in the register RDl. Therefore, upon receipt of the signal aegc, the address circuit LCA blocks the read-out operation, in that no signal lec is generated in order to leave the content of the register RDl unchanged, and also by no signal rzd, which can be represented as follows:

AD = led.adr.aegc.ei (7)

The IniOmazion maintained in this way in the register RD1 then normally becomes the output multiplex line MS transmitted.

If the operation concerned is a write operation, the address X no longer needs to be written and the address X + 1 has not yet been registered.

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It is necessary to write directly into register RD2; as a result, the address circuit LCA inhibits the write-in operation upon receipt of a signal aegc and instead generates a signal eis, which activates the gate circuit pis, whereas in turn a signal dec is generated so that the register RE2 the data combination stores that arrives from the input multiplexing ME. The transmission from the input multiplex line ME to the register RD2 is pod via an OR circuit carried out. This process can be summarized as follows will:

AD = ind.adi

eis = ind.vai.aegc.ei (8)

dec = ind.vai.aegc.ei

The counter CIR is incremented by the pulse acir.

The signal ddc is applied to a gate circuit pepg which at the same time receives the signal cpga. The ones in the formula groups Operations shown in (5) and (6) are performed. As a result, the contents of the storage space Transferred to the register RD1 with the address X + 1. Of the The content of the memory location with the address X is transferred from the register *? 32 to the memory location with the address X + l transferred (except those shown in the Forael group (8) Operations have replaced this content with a data combination that has just arrived).

Then the clock HGC gives a pulse and a led Impulse ind from. As a result, the shift takes place

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Storage spaces instead. In the following it is now assumed that X + l = Y. Four cases must now be distinguished; the currently considered address A (either adr or adi) is either smaller than X ₃ or larger than X but smaller than Y, or equal to Y, or larger than Y. The comparison circuits provided allow these four cases to be distinguished:

a) k < X- * ali <air-> appi,

b) X ^ k < Y - »- air ^ ali <cir - * - (aegi + apgi) appc,

c) A = Y - »ali = cir - ^ - argc,

d) A> Y - * ali 7 cir- »apgc.

Cases a) and d) are equivalent: the memory location with the address in question has not or has not yet been moved been; a gate circuit pipg combines the signals appi and apge in order to derive a signal ndc, that the address storage LCA initiates read-out and write-in operations to be carried out, the logical sequence of which is described by the formula groups (1) and (2).

Case c) corresponds to the state of a memory location that was read out in order to be moved, but its Content has not yet been rewritten (it is on the way from register RD1 to register RD2). To the Signal aegc is used to display this state. As already described above, the write-in and read-out operations then run controlled by the address circuit LCA according to formula groups (7) and (8).

Case b) corresponds to the status of a storage space that has already been completely moved (in which up to this point

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From the approach used, this is only the case with ali = X, since only the value Y = X + l is considered). This status is ensured by the gate circuits pjpg and pkpg discovered, which then emit a signal dca.

The addresses must then be corrected by adding
a unit is added without, however, affecting the operation as such. It is therefore sufficient
indicate that the address circuit LCA interacts in such a way that the following readout operation takes place:

lec = led.val
AD = led (adr + l) .dca.ci - ^

In addition, the following enrollment operation should take place:

ins = ind.vai

AD = ind (adi + l) .dca.ci
a = ind.vai

If these conditions are met, the respective
Operation performed without the mediation of the data
by moving storage spaces. Eventually the counter reaches the CIR
last memory location of the voice mailbox MC. The CIR counter remains; thereupon exist in this position and no longer take into account incoming impulses acir, but in turn emits a signal fmc which resets the register RTMC.

The shifting process carried out up to now has affected as many time slots as there are storage locations in the memory MC

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available. Because this process started with the beginning of a Rahn group M3, it is already before them End finished. Only the devices for address correction as a function of the shift remain in operation, because the command CI and the address AIR are maintained.

At the end of the frame group M3, the content of the register RTMC (0) is transferred to the register IRMC by the signal dmm transfer. The CI command and the AIR address are deleted. The address correction devices are used in the addressing circuit LCA switched off. At the same time there is a gate circuit PTCA, which is triggered by the signals fmc and dmm is activated, a signal cct. With reference to the addressing circuit CAE (Fig.4) and to the pulse trains in Fig.5a it can be seen that the signal cct from Memory MC initiates an entry process into the memory MPE.

That is sufficient, the addresses which are supplied by the addressing circuit CAE and .the new order of the Storage locations within the voice mailbox MC in agreement provided that the central unit UC has the appropriate information available posed.

However, the addresses from the address memory must still be used MTS must be brought up to date. This operation is first considered accomplished viewed and only described below. Under these conditions, the new arrangement of the channels has emerged

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the input time division multiplex line already in the cprach memory HC enforced accordingly.

After the insertion of a storage space has been considered above, the splitting off of a storage space will now be described. The write command in the IRMC register is handled in the same way as for the insertion of a new memory location. The CR command is selected instead of the CI command. It is also assumed that the start address AIR has the same value X.

The process begins as described above, so that the Formula groups (1) and (2) are valid for data transfer and formula groups (3) and (4) are valid for the beginning of the scanning of the memory MC remain valid in accordance with the operation of the counter CIR with which the only difference is that the signal replaces the signal ei, from which the following logical relationships result:

lec = leir.cr (H)

AD = cir.leir.cr
and

ins = inir.cr

AD = cir.inir.cr (12)

crn = inir.cr

When a signal acir reaches the counter CIR, if this is in a position that CIR = air = X, the comparison circuit CIR / AIR generates the status signal cega.

This status signal is from the addressing circuit LCA obtain. The readout operation carried out by the signal leir

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was initiated, but will not be changed. This will make the memory location with address X corresponding to the formula group (11) read out. The next write operation performed by the addressing circuit LCA is described as follows:

AD = cir .inir .cega.cr M ^)

crn = inir.CR.cega.cr

The addressing circuit LCA then receives a signal led, then the signal ind, if these operations address the address X do not have to be changed, the processes according to formula groups (1) and (2) do not have to be changed.

However, if these operations concern address X of the remote memory cell, they may not be carried out will. In this case, the comparison circuit AIR / AD only outputs a signal aegi. The addressing circuit LCA, which receives the aegi signal, is designed to carry out the operations in this case can prevent; this can be represented as follows:

AD = 'led.adr.aegi.er rad = led.aegi.er

as well as through:

AD = ind.adi.aegi.er

• j (15)

zzn - md.vai.aegi.cr λ- ^;

In both cases, the absence of the signals ins and lec prevents these operations from being carried out. In first In this case, the aforementioned signal rzd is generated, and that Reset register RDl so that a 0 infernalion

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A.E.J. Chatelon 37-1-4

is transmitted on the output time division multiplex line.

In addition, the gate circuit pdc was activated by a signal ddc. The gate circuit pdc transfers the information cir, which is identical to X, into the register RAR. In this way, the pulse acir causes the counter CIR to increment and produce a value cir = X + 1 and, on the other hand, to store the value X in the register RAR.

From this point in time on, the comparison circuit CIR / AIR delivers a new signal cpga, which indicates that cir is greater than air is. This signal cpga is also applied to the addressing circuit LCA in order to enable it to operate to change and to arrange for a storage space to be split off.

The address circuit LCA then receives the signal leir. The readout operation is carried out unchanged according to the formula group (11). The memory location with the address X + 1 is read out and its content is transferred to the register RD1. The address circuit LCA then receives the signal inir. The write operation is carried out according to the signal cpga according to the formula group (12), but the value cir (X + 1) is replaced by the value rar (X) ₅ when τοπ register AR was output. This operation is represented as follows:

ins = inir.er

AD = rare. inir. cpga. er - (16 ") - crn = inir.er

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A.E.J. Chatelon 37-1-4

This results in the rewriting of the data combination read out at address X + 1 in the memory location with the address X. The move process is continued accordingly.

To complete this process, you have to go through the signals led and ind initiated the look-through processes as in the case of inserting a memory location, there are four possible poles: the address A concerned (either adr or adi) is smaller than X; or it is smaller than X; or they are larger than X but equal or smaller as Y (position of the counter CIR); or it is greater than Y. The comparison circuits allow the four Differentiate cases:

a)

b) A = X- * ali = air - »- aegi _}

c) X <A ^ Y- »air ^ ali ^ cir-» apgi (appc + aege),

d) A> Y- * ali> c ir - * apgi.

Cases a) and d), which correspond to the situation in which the address concerned has not or has not yet been moved are equivalent and are indicated as before by a signal ndc. The address switching LCA performs the normal read-out and write-in operations indicated by formula groups (1) and (2) will.

In case b), the affected memory cell is the cell that was split off. This process has ended and was limited to preventing operations

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A.E.J. Chatelon-37-1-4

Concerning the Fömel groups (14) and (15) like this one Storage space.

Finally, in case c), the relevant storage space is moved. This process is plpg via gates and pmpg controlled, which emit a signal eac. This signal dac reaches the addressing circuit LCA, where the Address is corrected in the same way as described above in formula groups (9) and (10) with the difference ^ that a unit is subtracted instead of added. This is represented as follows:

= led.val
AD = led (adr-l) .dac.cr

as:

ins = ind.vai

AD = ind (adi-l) .dac.cr (18) a = ind.vai

The split-off process is continued as described above. During each time slot, the counter CIR is incremented and is finally stopped when the last memory location within the speech memory KC is reached. The split-off process is terminated like an insert process: resetting of the RTMC register, the IRMC register, transmission of the cct signal to bring the table TT3 up to date and requesting an address correction in the address memory> ITS

The above description has so far dealt with how the number of memory locations in the voice memory MC to the arrangement of the channels on the input

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gangszeitmultiplexleitung ME is adapted.

Obviously, the same devices can be used to calculate the number of locations in the address memory MTS (compare FIG. 3 and the associated description) to the arrangement of the channels on the output time division multiplex line MS adapt. Thus, when establishing a connection, a channel must be on both the input and the can also be switched on on the output time division multiplex line. Furthermore, a storage space must be at a suitable Position of the voice mailbox MC (corresponding to the position of the first channel on the input time division multiplex line ME). The facilities provided for this have been described. In addition, there must be a new storage space at a suitable place within the address memory MTS are inserted (corresponding to the place of the second channel on the output time division multiplex line MS). For this serve the same means that have already been described above.

Nevertheless, the address memory MTS and the devices which are used to insert or split off storage locations in the Airessenspeicher MTS, additional Features which will now be explained in connection with FIG will.

Fig.S shows a device EMT, which the memory XTS contains, similar to the device of Fig. f, which includes the voice memory MC. The establishment EMT is assigned to another facility, ECR; that serves to correct read-out addresses (adr,? ig.5) after a memory location has been inserted in the voice memory MC

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or was split off.

The ECR facility is only within correction times active. In this case the device EMT works exactly like the arrangement shown in FIG. In Fig. 8 only certain elements are shown (the corresponding elements in Fig. 6 are indicated in brackets) as follows:.

- MTS (MC) memory,

- Register RTl (RDl),

- Register RT2 (RD2),

- gate circuit ptn (prn),

- gate switch pet (pem),

- RMT (REM) register.

If the device ECR is not working, the circuit CRA is via the output adt of the register RT1 with the gate circuits ttn and pet connected, which is equivalent to the direct connection, in the arrangement shown in FIG is. The structure of the arrangement in FIG. 6 is therefore identical to the arrangement EMT in FIG. 8.

As far as the functioning of this device is concerned, only one difference has to be taken into account. It is supposed to be remembered that the arrangement of Figure 6 is a readout operation controlled by the address memory MTS (address adr and confirmation signal val) and a write operation controlled by the address management CAE (address adi and Authorization signal vai). The arrangement according to Fig. 8 performs a readout operation controlled by the Addressing circuit CAS (similar to CAE) through the one

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Address adt and an authorization signal vat generated. The normally following write operation (pulse trains 7) is then again controlled by the address circuit CAS, in particular by the address adt and the authorization signal vat. In this way the write operation becomes a rewrite operation, whose usefulness will later become clear.

The readout operation has generated an address ADT in the register RT1. In addition, a bit BC is generated, its use will be described below. The address ADT is transmitted to the gate switch pet via adt and ade, it then arrives at the RMT register on the basis of an acit signal (identical to acir), which then contains the address adr to the voice memory MC.

At the same time, the gate circuit pvl in the Device ECR issued the authorization signal vat. Normally there is no signal inh at the gate circuit pvl. During the pulse acit, the signal vat a flip-flop circuit RV supplied, which forwards the authorization signal val to the voice memory MC.

Some parts of the device EMT allow in the same way as described under FIG
I'ITS address store. Since the addresses are only given to the addressing circuit CAS as soon as
a signal czt (similar to cet) is transmitted, the change is carried out in the memory and the addressing of the address memory MTS is completely normal again.

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A.E.J. Chatelon 37-1-4

It should also be noted that changing the storage location (splitting or inserting) at the same time as a corresponding change in the voice memory MC can take place, with an output channel always at the same time as the corresponding input channel is switched on or off.

If a storage space is inserted, it must an address ADT can be written to the relevant memory location. The address to be registered is the Address AIT, which was already used during the insertion process with regard to the voice memory MC. The newly inserted Storage space in the address memory MTS only enables access to the newly inserted memory cell in voice memory MC. It must therefore contain the address of this memory cell. This write operation for Establishing a new connection path is equivalent to writing the required information in the register RD2 at the appropriate time. This is a variant of the method described in connection with Fig.6 and that does not need to be described further here.

What remains to be seen _s is the correction of the read address that allows the adjustment of the device ICR to the means EMT. These operations must be carried out when the voice memory MC emits the signal cct. The insertion or deletion of a memory space that has taken place during a frame group in the speech memory MC has no effects beyond this frame group. As soon as the next frame group begins, the address sources must

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A.E.J. Chatelon

(CAE addressing circuit and MTS address memory) match the new arrangement. It has been described above that this result is achieved without delay of the circuit CAE. What about the addresses of the address memory As far as MTS is concerned, a systematic change must be made here. This consists in being a unit added to each address or subtracted from each address of the address memory MTS, the value of which is above the value of AlR, that is the address for the voice memory MC (see Fig. 6) under which the Insertion process or splitting process should take place. This is achieved by adding the addresses that have been read out this correction is inserted. Since the addresses are rewritten immediately, both a correction of the address which is transmitted to the voice memory MC is achieved, as well as a corresponding change the content of the MTS address memory. Within a frame group each memory location becomes the address spexchers MTS addressed at least once. But since some cells in a frame group are addressed several times (these are those belonging to channels, their transmission speed is either 2.4 kBd or 9.6 kBd), bit BC is generated to ensure that this Corrections have been made and to avoid unnecessary repetition.

For this purpose, the device ECR contains a register CTMT, which at the same time as the register RTMC (cf. Fig. 6) is loaded with the same information (CI, CR, AIR). The gate circuit ppet transmits its content to the CRMT register if the voice mailbox

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AEJChatelon 37-1- ¹ »

MC emits the signal cct. Then the CRMT register issues one of the two signals cit (insertion) or crt (separation) as well as an address aicr.

The device ICR also contains a comparison circuit CP and an address correction circuit CRA.

If the signals cit and crt are missing, the connects Address correction circuit CRA adt with ade, as already mentioned above. It must be noted, however, that Such a method is not intended for the cable that transmits the BC bit, making this bit persistent is stored in any memory location of the voice mailbox MT.

As soon as the CRMT register is loaded, the cit signal (insert) is generated, for example. This signal is confirmed the operation of the circuits CP and CRA in the following way:

a) if adt aicr, no signal,

b) if adt aicr, only a signal cor.

If there is no signal cor., The circuit CRA not active.

If it receives the signal COR together with the signal cit and a bit BC with the value 0, the circuit CRA, the mode of operation of which is shown in FIG. 9, outputs an address ade = adt + i and a bit BC. 'because the input bit value is equal to 1, the address ade output by the circuit CRA is equal to that

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Address adt, whereby the value % of the bit BC is retained.

This method, as just described, is sufficient to carry out the address correction and the address memory Rearrange MTS in case of insertion.

If the arrangement is changed by splitting off a memory location, a signal crt is generated as soon as the CRMT register is loaded.

For any address adt that is stored in register RT1, the comparison circuit CP gives the following away:

a) if adt aicr, no signal,

b) if adt = aicr, only signal inh,

c) if adt aicr, only signal cor.

In the first case the circuit CRA remains passive (see FIG. 9) - in the second case it is already passive again. This case only occurs if initially only a change in the channels on the input time division multiplexing was taken into account in the switching system, but the associated output channel is not switched off until later. When the signal inh occurs, the gate circuit pvl is blocked; accordingly, no authorization signal val is generated. This prevents a memory cell that has already been split off from being re-addressed. In the third case, the circuit CRA receives the signals crt and cor and reacts to them as a function of

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the bit BC also received. Palls the value of the bit BCl, the CRA circuit remains passive. If the value of the bit is 3CO, it changes this bit value to the value and provides the information ade- with the value adt-1.

In this way, address corrections and corrections are made In the memory In the event of a split-off of a memory space carries out.

8 claims

609840/0733

Claims (1)

A.E.J. Chatelon 37-1-4 Claims jl.yTime-division switching system for binary-coded signals of different transmission speeds, with an input multiplex line, with at least partially the same time slots in successive frames (frame group) being assigned to different channels with different transmission speeds, as well as a corresponding output time-division multiplex line, a voice memory for synchronous storage of the coded signals and optional readout of the signals to the output time division multiplex line, and with an address memory for storing addresses of memory locations of the voice mailbox, characterized in that at least one first table (TVE, TVS) is assigned to the multiplex lines, which contains the corresponding transmission speed for each channel and indicates how many channels the same Occupy time slots in successive frames, and that a sufficient number of memory locations are allocated to these channels in the voice memory (MC), which are partially addressed with the help of the first tables (TVE, TVS). 2. Time division multiple switching system according to claim 1, characterized in that second tables (TTE, TTS) are provided which contain a bit location for each channel, the value of which indicates whether the associated channel is active (occupied) or not, and that in the voice memory ( MC) only the active channels are allocated a memory location, the addressing being carried out by combining the contents of the second tables (TTE, TVS). 509840/0733 - / - AEJ Chatelon 37-1- ² * 3- time multiplication system according to claim 2, characterized in that each memory location within the second tables (TTE, TVS) consists of as many bits as a maximum number of channels can be assigned to a time slot in successive frames at the lowest transmission speed. k Zextvielfachvermittlungsanlage according to claim 3 _5, characterized in that addressing circuits are provided, which determine the total number of active channels from the data of the first and second tables. 5 · digit multiple switching system according to claim 4, characterized in that a counter is provided which indicates the consecutive number of a frame within a frame group. 6. digit multiple switching system according to claim 4 and 5, characterized in that the addressing circuits also determine the number of the channel occupying a particular time slot from the serial number of a frame and the information from the first and second tables. 7. Zeitvielfaehvermxttlungsanlage according to claim 6, characterized in that a sector counter (PS) is provided which adds the Anzar.l of channels in the same time slots of successive frames, and that the voice memory (MC) is divided into sectors, each with a sector consecutive time slots of the same rank in a frame group is assigned and so many storage locations 5 0 9 3 4 Q / 0 7 3 3 A.E.J. Chatelon 37-1-4 includes how channels of these time slots are allocated, with the sector counter (PS) during each time slot generates the address of the first memory location belonging to the next sector. 8. Time division multiple switching system according to claim 7, characterized in that the addressing circuits add the value received from the sector counter (PS) and the number of the active channel of a time slot, this number being read from the memory location of the second table, which is also used for addressing the voice memory ( MC) is used.