DE2507632A1 - ARRANGEMENT FOR DETERMINING THE PRESENCE OF A VEHICLE IN A SPECIFIC AREA OF A ROAD - Google Patents

Description

Patent attorneys Dipl.-Ing. RV / iickmanü

Dipl.-Ing. H. Weickmann, Dipl.-Phys. Dr. K. Fincke Dipl.-Ing. R A.Weickmann, Dipl.-Chem. B. Huber

8 MUNICH 86, DEN

PO Box 860 820

MÖHLSTRASSE 22, CALL NUMBER 98 3921/22

Canoga Controls Corporation, 216o9 Parthenia Street, Canoga Park, Calif., U.St.A.

Arrangement for determining the presence of a vehicle in a certain area of a road

The present invention relates to an arrangement for detection the presence of a vehicle in a certain area of a road with a loop of wire near the road surface in the specified area.

For several years, induction loop detectors are used for various applications to determine the presence or the passing of a vehicle. Such detectors are used for example in controlled by traffic control systems to

509835/0728

2 b O 7 6 3 2

_ ο -

generate the input data required for a controller, which controls signal lamps (traffic lights). In another typical application, a detector can be connected to a Counter are coupled, which only counts the vehicles passing a certain point.

Various types of induction loop detectors are available for traffic purposes known. The detectors generally contain electronic circuits with a loop (i.e. a line loop) work together under the road surface in a plane running parallel to it are arranged. These circuits contain components which, together with the loop, form an oscillator, its Vibration frequency depends on the loop inductance. The loop inductance in turn depends on whether the Loop is burdened by the presence of a vehicle or not. A vehicle above the loop reduces the loop inductance and thus increases the oscillator frequency. The circuits monitor the oscillator frequency and generate a "call" signal (a signal indicating the presence of a vehicle) when a sufficient frequency change is detected. With known detectors there are various possibilities for monitoring the oscillator frequency has been exploited, generally analog circuits with filters and phase detectors be used.

It is an object of the present invention to provide an improved arrangement of the type in question, which works to monitor the loop inductance on a digital basis.

To solve this problem, an arrangement of the type mentioned at the beginning is according to the invention by the following features marked:

509835/0728

an oscillator coupled to the line loop, which operates on one of the inductance of the line loop dependent frequency oscillates, a clock circuit for measuring the duration of a fixed number of periods of the Oscillator signal, a reference signal stage which supplies a signal corresponding to a reference duration, a comparison stage for determining the difference between the measured Duration and the reference duration, and a threshold value stage, which reacts to a difference signal exceeding a threshold value responds and generates a signal indicating the presence of a vehicle in the specified area the street.

In a preferred embodiment of the invention lays the arrangement (detector) fixes sequential detector periods. A digital counter counts during each detector period (hereinafter referred to as loop counter) denotes periods of the loop oscillator signal. At the same time a second one measures digital counter (hereinafter also referred to as continuous counter) the duration of a predetermined number of loop signal periods by counting pulses supplied by a very accurate clock pulse source. The measured duration is then compared to a reference duration (its value on the measured duration during previous detector periods based), the difference being a measure of a change in the loop signal frequency and thus also of a change is the loop inductance. A threshold level then determines whether the change is of a sufficient size Generating a "call" signal is.

According to another important aspect of the invention, the difference (hereinafter also referred to as the deviation) between the measured duration and the reference duration as an error

509835/0728

input signal used to set the reference duration in the direction of to modify the measured duration, thereby allowing the detector to tune itself or to different ones Adapts to environmental conditions. The value of the adjustment depends on the size and direction of the deviation.

According to a further feature of the invention, the reference duration is slowly changed as a function of small deviations or differences between the measured duration and the reference duration. Furthermore, the modification of the reference duration always takes place slowly if the deviation occurs in a first direction, ie in a direction to generate a "call ¹¹ signal. On the other hand, the modification of the reference duration takes place as a function of large deviations in a second" non-call "- Therefore, the detector can detect the continued presence of a vehicle for a relatively long period of time, and it can also quickly detect a following vehicle that enters the loop immediately after a first vehicle has left the loop.

Further features of the invention emerge from the following description of exemplary embodiments on the basis of FIG Characters. It shows:

Fig. 1 is a block diagram of an embodiment of the invention;

Fig. 2 is a detailed block diagram of a preferred embodiment of the invention;

3 shows a table from which the various states can be seen in which an adaptation stage performs a slow or a fast adaptation according to FIG. 2; and

509835/0728

Figure 4 is a block diagram of one embodiment of the adaptation speed stage according to Fig. 2.

Fig. 1 shows an arrangement according to the invention for monitoring the frequency determined by an induction loop 1o. In the main applications of the arrangement according to the invention, the induction loop 1o by several turns (for example 3) of an electrical line formed, which is directly under a road surface is arranged parallel to this. Typically, a rectangular gutter about 1.8 1.8 m will be in the Cut a road surface into which the line loop is inserted and which is then bonded with an epoxy resin is closed. In a manner known per se, loops of various sizes and configurations can be used will.

For a typical case of traffic monitoring, the loop 1o is in a left-hand pocket under the Road surface arranged to determine the presence or passage of a vehicle. Any great mass of metal such as a vehicle entering the area above the loop changes the loop inductance. By monitoring the loop inductance, the presence can therefore be detected in a manner known per se a metal mass can be determined either directly or indirectly.

To notice changes in loop inductance very easily To be able to, the loop 1o is coupled to an oscillator circuit 12, which is usually in a housing is arranged on one side of the street. The oscillator

509835/0728

circuit 12 forms in a known manner together with the loop 1o an oscillator, which on a frequency, which is dependent on the loop inductance, oscillates. The circuit values are normally chosen so "that the center frequency of the loop and the oscillator circuit is, for example, 3o KHz. The through one to the The frequency change caused by a vehicle approaching a loop naturally depends to a large extent on the properties of the vehicle. A typical passenger car can change the oscillator frequency by about 2%. A narrow one Motorcycle can only change the loop frequency by 0.05%. By monitoring the frequency of the Loop oscillator signal can detect frequency changes and interpret them as a vehicle to be detected will.

According to the embodiment of FIG. 1, the Loop oscillator signal fed as an input signal into a multi-stage loop counter 14. In order to explain it is assumed that the loop counter 14 comprises ten stages and therefore 1024 periods of the loop oscillator signal can count. The loop counter 14 supplies an overflow signal on an output line 16 when 1024 periods of the loop oscillator signal are counted.

To measure the length of time (TD) required for the loop counter to count 14 1o24 periods, a clock pulse source 18 is provided which has a clock stage or controls a counter 2o. Both the counter 2o and the counter 14 are reset at the point in time when the loop counter overflow signal is on the Output line 16 occurs.

509835/0728

A comparison stage or a subtraction stage 22 compares that supplied by the timing stage 2o Time period TD with a reference time period TR, which is stored in a memory 24. Fig. 1 shows that the subtraction stage 2o activated by the loop counter overflow signal occurring on line 16 will. If this is the case, the subtraction stage 22 determines the difference between the measured duration TD and the Reference period TR.

The output signal of the subtraction stage 22 is in an adjustment speed stage 26 is fed, which is in turn coupled to the memory 24 to change the reference duration. Specifically, the speed adjustment stage closes 26 a servo loop to adjust the reference duration in terms of reducing the difference between the measured Change duration TD and the reference duration TR.

A signal S supplied by the subtraction stage 22, which is a measure of the difference between the measurable duration TD and the reference duration TR is fed into the input of a threshold value logic stage 28. Exceeds the difference S an externally selectable threshold value (for example a or b) the threshold value logic stage generates a Call signal on an output line 3o, whereby the presence of a vehicle is indicated above the loop. To explain the mode of operation of the arrangement according to FIG. 1, a situation is initially assumed in which there is no Vehicle is in the vicinity of loop 1o. The loop counter 14 counts cyclically from zero to 1023 and supplies each counting cycle, i.e. once for 1024 oscillator signal periods an overflow signal on line 16.

509835/0728

The measured time period TD and the reference time period TR are equal, so therefore the difference S between them is equal Is zero. Therefore, the adjustment speed stage 26 does not change the contents of the memory 24. Also is the signal S not so great that the threshold logic stage 28 generates a ringing signal on the line 3o.

Assume now that a vehicle is on the loop opens, which reduces its inductance and the frequency of the oscillator signal fed into the loop counter 14 is enlarged. Therefore, the loop counter overflow signal becomes with respect to the above counting cycle delivered earlier, thereby reducing the measured time period TD. The signal supplied by the subtraction stage 22 As a result, S jumps from zero to a larger number. If this signal is above the input to the threshold logic stage 28 If the threshold value jumps, this stage 28 delivers a ringing signal on line 3o. Furthermore, the adjustment speed stage begins 26 to change the content of the memory 24 in the sense of reducing the value S to zero. If the content of the memory 24 is changed relatively slowly during many cycles of the loop counter 14, the Threshold logic stage 28 continues to generate the ringing signal for a large period of time. In this way it can be continuous Presence of a vehicle above loop 1o in a large interval (typically over ten minutes) to be established. If the vehicle has been present over loop 1o for a large period of time, then the continuous incremental change of the reference duration content of the memory 24 possibly the presence of the Vehicle and thus switch off the call signal supplied by the threshold value logic stage 28.

- 9 ~

509835/0728

Let us now assume the other case, in which no vehicle drives onto loop Io, but the loop inductance changes changes due to a slow change in environmental conditions. Such a change in the Loop inductance naturally also changes the frequency of the loop oscillator signal determined by the loop counter 14. Therefore, the signal supplied by the subtraction stage 22 jumps from zero to some higher level Value. If this higher value is smaller than the threshold value entered in the threshold value logic stage 28, the Line 3o generated no ringing signal. However, the adjustment speed level changes depending on the value of the signal S 26 the reference duration content of the memory 24, whereby the reference duration is adapted to the changed environmental conditions.

In the above explanation of the arrangement according to FIG. 1, only the case was assumed that the loop inductance decreases and the loop oscillator frequency increases. The reverse case can also be done either by changing the ambient conditions or by a dated Loop area driving away vehicle are caused. In this case, the value of the signal S becomes at that shown in FIG assumed polarity negative. Therefore, the threshold logic stage 28 does not respond to the change, even if it exceeds the predefined threshold. So no ringing signal is generated Ea. To between the two states decreasing and increasing loop inductance and corresponding To distinguish increasing and decreasing loop frequency, it is said in the following that the loop frequency in one call direction (increasing Loop frequency) and in a non-calling direction (decreasing loop frequency). The speed of adaptation

- 1o -

509835/0728

- 1ο -

Capacity level 26 closed servo loop works for deviations of the value S supplied by the subtraction stage 22 in both directions to obtain the reference duration content of the memory 24 in the sense of reducing the value * S to zero. As can be seen from the following still results, the adjustment speed stage 26 changes the reference duration either relatively slowly or quite fast. The adaptation, i.e. the change of the reference duration stored in the memory 24, takes place specifically in an initial interval1 if the arrangement is initially is switched on, and also in the case in which the frequency deviation given by the value S is in the non-calling direction is big, fast. On the other hand, the adaptation takes place as a function of small frequency deviations and each deviation slow in call direction. As can be seen from the following remarks, this enables asymmetrical adjustment a continuous determination of the presence of a vehicle in a relative to frequency deviations long period of time, for example from 10 to 12 minutes; At the same time, however, a following vehicle can also be identified very quickly if one was previously available Vehicle has driven away from the area above the loop.

Fig. 2 shows a preferred specific embodiment of the in Fig. 1 schematically shown arrangement. As in the case of the arrangement according to FIG. 1, the loop oscillator 12 delivers in the arrangement of FIG. 2, one input pulse per loop signal period for the loop counter 14. It is assumed that the loop counter 14 according to FIG Binary counter with 1o24 different counting states, which are referred to below with zero to 1o23. The loop counter 14 counts pulses that are fed from loop oscillator 12 into a loop counter input terminal 4o,

- 11 -

509835/0728

when an enable signal in a loop counter input terminal 42 is fed. The loop counter 14 can function as a function of a loop counter reset terminal 44 input signal can be reset to zero. Furthermore, the loop counter 14 delivers after counting to 1o23 an overflow signal at an output terminal 46.

As was explained with reference to FIG. 1, the frequency of the Schlexfen oscillator 12 is monitored by the fact that the duration a fixed number of loop signal periods is counted by the loop counter 14. In the case of the one shown in FIG The embodiment is the duration of the fixed number of loop counter cycles by a duration counter 48 in Connection with a presetting counter 5o counted. Before explaining how the duration counter and the Presetting counter reference should be made to a sequence control logic network 52, which the advancement and operation of the The circuit of FIG. 2 controls.

Sequence control logic network 52 includes five set-reset -Flip-flops 54, 56, 58, 6o and 62, which are connected in the form of a ring counter, so that only one flip-flop supplies a signal "1" at one point in time. The advancement of the single bit "1" from the flip-flop 54 successively through flip-flops 56, 58, 6o and 62 is referred to as the "detector cycle". Will be used during each detector cycle five different control states with operations and signal transmissions are defined. The transmission of the only bit "1" from a flip-flop to the following flip-flop im Logic network 52 occurs coincidentally with a clock pulse which is generated by a very precise crystal clock pulse source is delivered. Although not specifically shown in FIG. 2 for reasons of clarity, it should be noted that the clock pulses are fed into the gate, which are sent to the

- 12 -

509835/0728

Set and reset inputs of the flip-flops in the network 52 are coupled so that each flip-flop only coincides with the occurrence of one supplied by the source 64 Clock pulse is set and reset.

The network 52 defines during each detector cycle the following states:

GO, advance (ADV), read (RD), reset (RST) and preset (PRST). The aforementioned switching states are successively determined when the single bit "1" from flip-flop 54 through flip-flops 56, 58, 6o and 62 is advanced. The incrementation of the bit "1" by the logic network 52 is triggered by a "start" signal, which is fed into the control input of the flip-flop 54 via a gate 63. This "start" signal is called Function of the loop signal period generated which follows the switching of the flip-flop 62 to the bit "1". Before further explanation of the mode of operation of the logic network 52 and especially the criteria for incremental switching of the single bit "1V" from one flip-flop to the next Let us first consider the above-mentioned duration counter 48 again. This duration counter 48 is just like the loop counter 14 a multi-level binary counter.

It is assumed that the counter 48 is formed by 16 stages and can therefore assume 65,536 different counting states. It counts clock pulses from the clock pulse source 64 are fed into an input terminal 7o, albeit an enable signal into an enable terminal 72 is fed in. It is assumed that the clock pulse source 64 operates at a frequency of 2 MHz. As a function a signal fed to a reset terminal 74 of the continuous counter will set the counter to a zero count

13 -

509835/0728

switched back .. At an output terminal 76 of the continuous counter an overflow signal is delivered when this counter is in the highest counting state 65 535.

During the GO switching state, which is then set, when the flip-flop 54 is switched to the bit "1", the loop counter 14 counts periods of the loop oscillator signal as a function of the output signal "1" of the flip-flop 54, whereby the loop counter via the terminal 42 is released. Furthermore, the continuous counter 48 counts clock pulses during the GO switching state, as the output signal "1" of the flip-flop 54 is fed into an input of an OR gate 8o, the output signal of which is based on the Release terminal 72 of the duration counter 48 is given. When the loop counter 14 reaches the count value 1o23, and on supplies an overflow signal at terminal 46, the flip-flop 54 of the control network is reset and the flip-flop 56 is set via an AND gate 82, whereby the incremental state is determined. When the duration counter 48 has counted up to the count value 65 535 and an overflow signal on the Output line 4 supplies 6, an AND gate 84 is activated to reset the flip-flop 56 and that To set flip-flop 58 via an OR gate 85, which switches from the incremental state to the read state. The reset state, which is determined by the fact that the flip-flop 6o supplies an output signal "1", occurs the clock pulse which immediately follows the switching of the flip-flop 58 into the logic state "1". Corresponding the flip-flop 66 delivers a logic "1" at the clock pulse, which corresponds to the switching of the flip-flop 6o follows the logical "1".

During the preset state in each detector cycle

- 14 -

509835/0728

the content of the aforementioned preset counter 5o is fed into the duration counter 48 via gate 9o. This Presetting counter 5o is formed by a binary counter, which in the present embodiment has 16 levels, so that it can count from zero to 65,535 just like the duration counter 48. As explained in more detail below the preset counter is used to feed a count value into the continuous counter during each detector period, the count being of such a size that the slider counter overflow signal appearing on line 46 and the overflow signal des appearing on line 76 Duration counter in the absence of a significant change in the loop signal frequency occur temporally coincident.

The content of the presetting counter, which is to be explained in more detail by means of the figures, is special Adjustment speed stages 98 are controlled via the transmission gates So during the preset state fed into the continuous counter in each detector cycle. For the basic explanation of the mode of operation of the arrangement According to Fig. 2, it is initially assumed that it is in an idle state in which in a long period of time no significant changes in the loop signal frequency have occurred. In this case, the deliver Loop counter 14 and the duration counter 48 the overflow signal temporally coincident. It is now assumed that a vehicle drives onto the loop, whereby the frequency of the Loop signal is enlarged. This results in the loop counter 14 counting faster and therefore on the line 46 supplies an overflow signal before the duration counter has supplied an overflow signal. As in the following in more detail is explained, the adjustment speed stage 98 then increases the count in the presetting counter 5o, so that the continuous

- 15 -

509835/0728

- Tb -

Counter delivers its overflow signal earlier in the detector cycle. In other words, this means that the count in the preset counter is carried out by the adjustment speed stage 98 is changed in a direction in which the overflow signal of the duration counter in the direction of a temporal coincidence with the overflow signal of the loop counter. Compensation for the time difference between the overflow signal of the loop counter and the overflow signal of the duration counter takes place in increments over many detector cycles at a speed set by the adjustment speed stage 98. That is, the time difference between the occurrence of the overflow signal of the loop counter and the overflow signal of the continuous counter can be compensated quickly if the arrangement adapts very quickly to changes in the loop inductance target. On the other hand, this compensation can also be done slowly if the arrangement is slow to adapt to changes in the loop inductance. In vehicle traffic applications, it is often desirable continuously detect the presence of a vehicle over a loop for a large period so that the adaptation speed stage 98 the counter contents of the counter 5o in a manner to be described with reference to FIG Way slowly changes to the time difference between the occurrence of the overflow signal of the loop counter and of the overflow signal of the continuous counter in a very large number of detector periods. On the other hand, it is It is desirable that the arrangement respond very quickly to a following vehicle after a change the loop inductance has occurred by a vehicle driving away from the area of the loop, then must the counter contents of the preset counter can be changed very quickly to the overflow signal of the loop counter

16 -

509835/0728

and the overflow signal of the duration counter within a few Bring detector cycles into temporal coincidence.

The relationship between the overflow signal has been described above of the loop counter and the overflow signal of the continuous counter during an idle state and for the Consider the case that a vehicle drives onto the loop and increases the loop signal frequency considerably. It has also already been stated that the count value in the preset counter as a function of an increasing Loop signal frequency is changed so that the overflow signal of the continuous counter earlier in the detector cycle occurs around the time difference between the overflow signals of the loop counter and the duration counter. After a certain interval of, for example The arrangement has adapted completely to 12 minutes, i.e. the time differences ζ between the occurrence of the overflow signals of the loop counter and the duration counter is complete disappeared so that the arrangement no longer recognizes the continued presence of the vehicle over the loop notices. Now consider the case where the detected vehicle drives away from the area above the loop. The loop signal frequency then decreases so that the loop counter overflow signal appears on line 46, after the duration counter overflow signal has occurred on line 76. Therefore, the adjustment speed level reduces then the count value in the presetting counter 5o to again the overflow signal of the duration counter within each Detector cycle to vary such that the time difference between the overflow signals of the loop counter and the Continuous counter is compensated. From the above explanation of the arrangement of FIG. 2 it is therefore apparent that the Reference duration, which is determined by the duration counter 48,

- 17 509835/0728

the measured duration of a fixed number of loop signal periods readjusts in such a way that the time difference between the measured duration and the reference duration is reduced to zero.

During the GO state, the loop counter counts 14 loop signal periods, while the continuous counter counts 48 clock pulses counts. Assume that the overflow signal of the loop counter 14 before the overflow signal of the continuous counter 48 occurs. As a result, the flip-flop 54 is reset and the flip-flop 56 is set, so that the GO state is switched to the incremental state. A LO / HI flip-flop 1oo, which was set during the reset status of the previous detector cycle, remains set, so that it provides a LO / count output signal. During the step-up state, the duration counter 48 remains on the Or-gate 8o activated. The duration counter therefore continues to count until it overflows. If the duration counter overflows, it resets the flip-flop 56 of the control logic network 52 via the gate 84 and sets the flip-flop 58, which switches from the incremental state to the read state. The number of times during the incremental state Occurring clock pulses are counted by an error counter 1o2. The output of the clock pulse source 64 is connected directly to the input of this error counter 1o2. The error counter 1o2 is by the output signal of a OR gate 1o4 enabled because s is coupled to an enable input 1o6 of the counter 1o2. During the switching state the error counter is enabled via an AND gate 1o8, so that the OR gate 1o4 receives an input signal "1" contains. The AND gate 1o8 is then always during the incremental state switched through if an initial state is not specified. An initial state is only then

- 18 -

509835/0728

given when the arrangement is switched on (hereinafter described in more detail). The error counter is set via an input terminal during each reset state of a detector cycle 11o reset. Therefore, the error counter 1o2 counts the number of clock pulses or the duration of the progress-old state, which is the time difference between the occurrence of the overflow signals of the loop counter and the duration counter represents.

The output signal of the error counter is at the input of a Threshold logic level 112 coupled, which of the logic level 28 of FIG. 1 is analogous. This logic stage 112 according to FIG. 2 has two outputs which supply a signal "1", if the count of the error counter is less than the threshold value established by this stage. When the count of the error counter 1o2 by the logic level 112 exceeds a specified threshold value, an over-threshold value output line delivers 114 a signal "1". On the other hand, if the count of the error counter 1o2 is less than that through the threshold value determined by the logic stage 112, a sub-threshold value output line 116 supplies a signal "1". the Signals on these output lines 114 and 116 determine when a "call" signal is to be generated.

It is now assumed that the overflow signal is on the line 76 of the duration counter occurs during a detector cycle prior to the overflow signal on line 46 of the loop counter. In this case, the continuous counter overflows during the GO state, causing the LO / HI counting flip-flop 1oo is reset via an AND gate 118. Then the flip-flop 1oo provides a HI count output signal, whereby an AND gate 12o is switched through during the GO state. The output of the AND gate 12o is at an input

- 19 -

509835/0728

of the OR gate 1o4 coupled, which, as mentioned above, enables the error counter 1o2. Therefore the error counter counts 1o2 the number of clock pulses or the duration between the occurrence of the overflow signals of the duration counter and the Loop counter. As mentioned above, the threshold logic level determines 112, whether the count of the error counter 1o2 is above or below the threshold value determined by this. It should also be noted that when the loop counter overflows, the GO state is switched off and the Control logic network 52 is switched to the incremental state. When the flip-flop 1oo is a HI count output supplies, the logic network 52 is switched from the stepping state to the immediately following clock pulse Read status switched.

If a call flip-flop 13o is set, it supplies a call signal, whereby a presence of a vehicle is indicated. This call flip-flop 13o is via gates 132 and 134 set or reset during the read state. The read state is defined by the fact that the flip-flop supplies a "1" signal in the sequence control logic network 52. The call flip-flop 13o is then set via the gate 132, when the counting flip-flop1oo during each detector cycle supplies a LO count signal and if the threshold value logic stage 112 an over-threshold state of the error counter notices. Note that the LO count signal of flip-flop 1oo occurs when the loop counter overflows occurs during a detector cycle before the duration counter overflows. The over-threshold condition in which a "1" signal is present on line 114 occurs if the count stored in the error counter 1o2 during this detector cycle is greater than that by the Threshold level 112 is set threshold. if

- 2o -

509835/0728

- 2ο -

the count in the error counter exceeds the threshold value, so the measured duration of a fixed number of loop signal periods deviates so far from the reference duration that the actual presence of a vehicle above the loop is determined.

The call flip-flop 13o becomes each during the read state Detector cycle reset when threshold logic stage 112 indicates that the frequency deviation of the loop signal frequency, which is given by the size of the count in the error counter 1o2 is not sufficient to generate a ringing signal to create. In order to avoid that the call flip-flop 13o in a case in which the threshold value has just been exceeded, the threshold value logic stage 112 preferably sets a lower count for each selectable threshold so that the over-threshold signal after exceeding of the threshold value is held until the error falls to a value that is smaller than the threshold value. For example, assume a threshold of 12 counts. If the error exceeds 12 counts, the over-threshold signal is generated and held until the error for example, falls below 11 counts.

Before discussing FIGS. 3 and 4, which illustrate an embodiment of the adaptation speed stage 98 and its operating conditions show, let it be an initial timing stage 14o and an enable timing stage for the adjustment speed stage indicated according to FIG. The start timing stage 14o only speaks to the switch-on the arrangement, which is shown schematically by a switch. The start time cycle stage 14o is inserted Interval of, for example, 30 seconds in which

21 -

509835/0728

the arrangement adapts very quickly to the existing environmental conditions. During this interval the Initial timing stage 14o an initial signal on line 146 indicating the rapid storage of a count in advance tell counter 5o triggers the overflow signal of the continuous counter to bring it into temporal coincidence with the overflow signal of the loop counter. To generate a ringing signal to prevent locks during this initial interval the start signal the AND gate 1o8, which is at the input of the OR gate 1o4, which in turn with the release input of the error counter 1o2 is coupled. Therefore, the error counter 1o2 does not count any clock pulses, which after the overflow of the loop counter and before the overflow of the duration counter occur during this start interval. This prevents the generation of a ringing signal, but the adaptation speed stage does the counting can change in the presetting counter 5o in the sense described above.

The timing stage 142 is activated by a ringing signal supplied by the flip-flop 13o and sets an interval for example ten minutes. As will be explained below with reference to FIG. 4, do not adjust the arrangement during this ten minute interval, i.e., the count of the preset counter 5o is not changed. Through the action of the release timing stage 142, the arrangement can detect the presence hold a vehicle longer before the continued presence of the vehicle is blurred by the adjustment of the arrangement will.

The overall function of the adaptation speed stage 98 was described above in connection with FIG. Be it mentioned once again that this level is limited to an

- 22 -

509835/0728

counter 1o2 responds and a servo loop closes, whereby the count in the preset counter is changed so that the occurrence of the overflow signal of the duration counter coincides with the occurrence of the overflow signal of the loop counter. The adjustment speed level 98 continues to change the count in the preset counter 5o slowly or quickly by one accordingly to ensure slow or fast adaptation to changes in loop inductance.

To explain how the adjustment speed stage works 98 reference is made to the table of FIG. 3, from which the change in the count in the preset counter 5o can be seen as a function of the various conditions. In each of five lines of the table according to FIG. 3 there is a specify the other set of conditions entered in columns 1 to 4. In columns 5 and 6 is the entering Effect entered. The six columns in each row represent the following:

Column (1): Start - "1" and "O" represent, respectively a point in time within and outside of the start interval defined by the timing stage 14o. The sign X in column (1), line (3) indicates that there is no difference for other conditions specified in line (3), whether the start interval is defined or not.

Column (2): ^ X loop frequency - the arrows in column 2 indicate a change in the loop frequency in the sense of an increase or decrease. The loop frequency increases as a vehicle drives onto the loop and decreases the loop inductance and decreases as a vehicle moves out of the area above the loop

- 23 -

509835/0728

drives away.

Column (3): LO / HI counting flip-flop - this column shows the switching state of the flip-flop 1oo according to FIG.

Column (4): Threshold value - this column indicates the decision of the threshold value logic stage 112, whether the count in the error counter 112 is above or below the defined threshold value. An X in this column means that the effects according to Columns 5 and 6 occur regardless of the threshold value condition.

Column (5): Adjustment - this column gives the desired adjustment speed (either fast or slow) of the preset counter 5o as a function of the conditions given in columns 1 to 4.

Column (6): Counting - this column indicates the direction (up or down) in which the preset counter 5o conditions specified as a functiorider in columns 1 to 4 must count so that the arrangement can adapt.

Line 1 in Fig. 3 shows that the counting flip-flop 1oo during the initial period as a function of an increase in the loop frequency is in the switching state LO and that the preset counter is fast regardless of the threshold value condition must count up to the overflow signal of the continuous counter in temporal coincidence with the overflow signal of the loop counter.

Line 2 in Fig. 3 shows that the flip-flop 100 during the initial interval as a function of a decreasing loop frequency is in the HI state, with the preset counter

- 24th

509835/0728

regardless of the threshold value condition given by logic stage 112 must count down quickly to keep the overflow signal of the continuous counter in temporal coincidence with the Bring overflow signal of the loop counter.

Line 3 in Fig. 3 shows that the preset counter is decreasing the loop frequency and generation of the counting state HI in the flip-flop 1oo in the event that the threshold value is exceeded must count down quickly due to the error in order to turn the overflow signal of the continuous counter into temporal coincidence with the overflow signal of the loop counter. Line 3 represents a state in which the arrangement has adapted to the presence of a vehicle, which then suddenly drives away from the area above the loop, whereby the loop frequency decreases. In this case it should the arrangement can quickly adapt to this new state, so that a subsequent approach to the loop area Vehicle can be determined.

Line 4 in Fig. 3 shows the case after the end of the initial interval, in which the loop frequency has increased, so that the counting flip-flop 1oo in the counting state LO is switched. When the threshold logic stage 112 has a Over-threshold state indicates, so is by the call flip-flop 13o of FIG a slow counting up of the preset counter, determined by the timing stage 142 in FIG. 2 5o causes. Under the same conditions specified in line 4 of FIG. 3, prior to the adaptation to the Changing the frequency does not generate a ringing signal and also no delay caused by the clock stage 142 if the error counter does not have an over-threshold condition in the

- 25 -

509835/0728

Logic stage 112 generated. That is, the slow counting up of the preset counter is triggered immediately. This corresponds to the conditions according to line 4 in FIG. 3 a change or deviation of the loop frequency in the calling direction. Is the deviation from the generation of a If the ringing signal is large enough, the adaptation is switched off during the interval established by the timing stage 142. If the deviation is not sufficient to generate a call signal, what is the case with slowly changing environmental conditions may be the case, the adaptation is triggered immediately at a slow speed.

Line 5 in Fig. 3 shows the state occurring after the initial period when the loop frequency is used for generation a count position HI in the flip-flop 1oo decreases. If the deviation is smaller than that determined by logic stage 112 Threshold value so the presetting counter 5o slowly counts down in order to reduce the overflow signal of the continuous counter in terms of time Coincidence with the overflow signal of the loop counter bring.

In summary, in connection with FIG. 3 it can be stated that the arrangement changes during the initial period always adapts quickly. After the initial period, the arrangement always adapts slowly if the deviation is smaller than the defined threshold. If the deviation in the call direction is above the defined threshold value, it takes place the adjustment is slow; If the deviation is in the non-call direction, the adjustment takes place quickly.

4 shows a preferred embodiment of the adjustment speed stage 98 according to FIG. 3 for the implementation of the conditions specified in the table according to FIG. The in Fig. 4

- 26 -

509835/0728

The preset counter shown is the same as the preset counter 5o of FIG. 2. As mentioned above, the preset counter comprises 16 binary levels. The preset counter counts clock pulses supplied by the clock pulse source 64 (Fig. 2), which are fed in at the data input terminal 158.-So the presetting counter can count, a release signal must be fed into the release input 16o. The preset counter 5o is switched as an up-down counter, which normally counts down except that on an up control line 162 an up control signal is fed in.

It should be mentioned again that lines 1, 2 and 3 in 3 shows the conditions for rapid adjustment of the preset counter Specify 5o. In the embodiment according to FIG. 1, the presetting counter 5o is used directly for rapid adjustment enabled via OR gates 164 and 166. As long as the gate 164 and 166 are switched through, the preset counter counts 50 clock pulses which are fed in via the input line 158 will. Three AND gates 168, 17o and 172 are used for Realization of the functions according to the first, second and third lines in FIG. 3.

Specifically, the AND gate 168 is during the initial interval switched through when the count value LO is present for the duration of the incremental state that is triggered by the flip-flop 56 of the sequence control logic network 52 is established. It should be remembered once again that the duration of the incremental state is directly related to the frequency deviation or the error stored in the error counter 1o2, if the Count LO is present. Therefore, the AND gate 168 gives the presetting counter 5o for the duration of the incremental addition

- 27 -

509835/0728

Was free via the OR gates 164 and 166, so that the preset counter counts up, because the Flip-flop 1oo according to FIG. 2 supplied count signal LO fed into the up control terminal 162 of the presetting counter 5o will.

The conditions specified in line 2 according to FIG. 3 are implemented by the AND gate 17o. In this case, however, will the duration during which the AND gate 17o is switched through, determined by the duration of the GO state after the counting flip-flop 1oo has assumed the count value HI. This duration is a measure of the deviation of the loop signal frequency.

The AND gate 172 sets the conditions for a rapid adaptation of the preset counter according to line 3 in FIG. 1 realized, this gate being switched through for a period which is related to the magnitude of the deviation of the loop signal frequency. When the gates 17o and 172 are switched through, the presetting counter counts down. For a slow adaptation of the presetting counter 5o, the clock pulses are passed through an adaptation delay counter 18o, which divides by 1o24. So this adjustment delay counter is one in two directions counting multi-stage counter that can count from zero to 1o23. Clock pulses are fed into an input 182 of the adjustment delay counter 18o fed in, which counts when a release control input 184 has a release signal is fed in. The adjustment delay counter 18o normally counts down except for a control signal is fed into a step-up control terminal 186. At the output of the adaptation delay counter 18o is a counting detector, for example an AND gate 188

- 28

509835/0728

switches to determine the occurrence of a single count value, for example 1o23. If the gate 188 detects this count, so it enables the preset counter via the OR gate 166 to generate a clock pulse in feed this meter. It is important to note that the preset counter has OR gates 164 and 166 is enabled, and counts clock pulses directly when the arrangement adapts quickly. Adjusts the arrangement slowly on, the preset counter is enabled via the AND gate 188 and the OR gate 166 so that it is only counts a clock pulse of 1o24 clock pulses each.

Clock pulses are generated by the adjustment delay counter 18o counted under the effect of AND gates 19o and 192, which realize the conditions according to lines 4 and 5 of FIG. The AND gate 19o is switched through if during of the read state determined by the flip-flop 58 in the sequence control logic network, the count value LO is present. In addition, the AND gate 19o is only switched through if after that determined by the clock stage 142 Delay interval1 an adjustment enable signal is available.

The AND gate 192 is switched through when the threshold value HI and an over-threshold condition exist. The outputs of the AND gates 19o and 192 are connected to the input of one Or gate 194 coupled, which controls the enable input line of the adjustment delay counter 18o.

To explain how the adjustment speed level works 4 it is initially assumed that the arrangement according to FIG. 2 is switched on and the initial interval occurs. For the duration of the initial interval

- 29 -

509835/0728

it is assumed as an example that the overflow signal of the Loop counter very far before the overflow signal of the Duration counter occurs and that the error counter 1o2 assumes the count value 64 during several detector cycles. That means, that the indexing state determined by the sequence control logic network 52 during each of these detector cycles has a duration of 64 clock pulses and that gate 168 of FIG. 4 has 64 clock pulses during each detector cycle feeds into the presetting counter 5o. Therefore, the counter content of the preset counter 50 increases in increments to, whereby the time interval between the occurrence of the overflow signal of the loop counter and the overflow signal of the Duration counter is compensated. The overflow signals of the The loop counter and the duration counter are finally temporally coincident. It is now assumed that the initial interval is completed. Are the overflow signals of the loop counter and the duration counter coincide in time, the threshold value logic stage 112 sets an over-threshold value state fixed. During each read state, a clock pulse is fed to the adaptation delay counter 18o, causing it to counts up or down, depending on whether the overflow signal of the loop counter or the overflow signal of the Duration counter occurs first. The counting device therefore depends on the switching state of the counting flip-flop 1oo. If the arrangement is idle, the adjustment delay counter can increase by one count during each detector cycle count up or down. However, this normally has no effect on the preset counter, as this is only for a clock pulse as a function of just one specific count of the 1o24 counts of the adaptation delay Counter 18o is released.

Let the condition given in line 4 according to FIG. 3 now be assumed

- 3o -

509835/0728

assumed at which the loop counter frequency is significant increases and an over-threshold condition arises. According to the above, this leads to the call signal 13o (Fig. 2) generates a flip-flop and that the timing stage 142 the adaptation enable signal for a certain time interval turns off. During this interval there are no inputs to the adaptation delay counter 18o fed in. After the interval specified by the timing stage 142 has elapsed, the gate 19o is switched through, to add a count signal to the adaptation delay for each detector cycle feed counter 18o. Entered into the adjustment delay counter 18o for every 1o24 Count values are only given a count value in the presetting counter 5o. Therefore, the preset counter becomes 50 only incremented once per 1024 detector cycles. This slow adjustment speed in the preset counter ensures that the presence of the vehicle is maintained for a large period of time, for example 12 minutes can be. Assume now that the vehicle is driving away from the loop and that the loop frequency is sudden decreases, as indicated in line 3 of FIG. Through this process the gate 17o is switched through, so that for the duration determined by the interval of the GO state after switching the counting flip-flop 1oo clock pulses are fed directly into the preset counter. In other words, that for a of the deviation or the difference between the occurrence of the overflow signals of the loop counter and the continuous counter dependent duration clock pulses are fed directly into the presetting counter 5o. In this case, counts If the error counter is up to 64, for example, 64 clock pulses are entered into the preset counter during each detector cycle fed in. This fast adaptation speed differs significantly from the slow adaptation speed, with one count value per To24 detector cycles

- 31 5098 3 5/0728

is fed into the presetting counter 5o. The arrangement can therefore change during the rapid adaptation more than 60,000 times faster than during the slow one Adjust customization.

- patent claims -

- 32 -

509835/0728

Claims (1)

Claims 1) / Arrangement for determining the presence of a vehicle in a certain area of a street, with a loop of wire near the pavement in the certain Area, characterized by an oscillator (12) coupled to the line loop (1o), which operates on one of the Inductance of the line loop (1o) dependent frequency oscillates, a clock circuit (14, 18, 2o) for measurement the duration of a fixed number of periods of the oscillator signal, a reference signal stage (24) which is a one A comparison stage (22) for determining the difference between the measured signal supplies reference duration Duration and the reference duration, and by a threshold value stage (28) which is set to a threshold value exceeding Difference signal responds and generates a signal indicating the presence of a vehicle in the particular Indicates area of road. 2) Arrangement nach.Anspruch 1, characterized by an on the feedback stage (26, 28) responding to the difference signal for changing the reference duration in the sense of a reduction of the difference signal towards zero. 3) Arrangement according to claim 1 and 2, characterized in that the feedback stage (98) a circle (19o, 192, 194, 18o, 188, 166) to slowly change the reference duration, a circle (168, 17o, 172, 164, 166) to quickly change the duration of the draw as well as a the size and the direction of the difference responsive circle for the selective activation of the circles for the slow one and quick change of reference duration. - 33 509835/0728 4) Arrangement according to one of claims 1 to 3, characterized in that that the clock circuit (14, 18, 2o) has a first counter (14) for counting the fixed number of periods, a clock pulse source (18) and a second counter (2o) for counting the clock pulses in the counting interval of the first meter (14) contains. 5) Arrangement according to one of claims 1 to 4, characterized in that that a sequence control network (52) for determining successive detector cycles with a Stage (62) for generating a start signal during each detector cycle is provided that the first counter (14) after the occurrence of the start signal periods of the oscillator signal counts and after M counts a first overflow signal provides that the second counter (48) counts clock pulses from the clock pulse source (64) after the occurrence of the start signal and after N counts a second overflow signal delivers that a presetting stage (5o) for feeding a count value into the second counter (48) before the start signal occurs is provided and that a ringing signal circuit (1o2, 112) is provided which, when the first overflow signal occurs supplies a ringing signal before the second overflow signal which indicates the presence of a vehicle in the specified area. 6) Arrangement according to one of claims 1 to 5, characterized in that that the adjustment speed stage (98) to change the through the presetting stage (5o) in the second counter (48) fed count value in the sense that the interval between the generation of the first and the second overflow signal is reduced. - 34 - 509835/0728 7) Arrangement according to one of claims 1 to 6, characterized by the following design of the generating the call signal Circle: a third counter (1o2) for generating a counter value, which is a measure of the number of clock pulses occurring between the generation of the first and second overflow signals is, and a threshold level determining a ringing threshold value (112), the ringing signal only then is generated when the count value supplied by the third counter (1o2) exceeds the ringing threshold value. 8) Arrangement according to one of claims 1 to 7, characterized in that that the change in the counter value (48) fed into the second counter by the presetting stage (5o) by the adjustment speed stage (98) as a function of the count value supplied by the third counter (1o2). 9) Arrangement according to one of claims 1 to 8, characterized by a responsive to the call signal timing stage (142) for defining an interval of fixed duration in which the adjustment speed stage (98) is switched off. 1o) Arrangement according to one of claims 1 to 9, characterized in that the adjustment speed stage (98) responds both to the occurrence of the first threshold value signal before the second threshold value signal and to a counter value supplied by the third counter (1o2) and exceeding a threshold value to change the counter value fed into the second counter (48) by the presetting circuit (5o) at high speed. - 35 - 509835/0728 11) Arrangement according to one of claims 1 to 1o _f, characterized by a timing stage (14o) which defines an initial interval of fixed duration, wherein the adjustment speed stage (98) responds to an output signal of the timing stage (14o) defining the initial interval, by which of the presetting stage (5o) to change the count value fed into the second counter (48) at high speed. 12) Arrangement according to one of claims 1 to 11, characterized in that that the Rufschwellwertstufe (112) to one of the Difference exceeding the threshold value only responds in one direction. 13) Arrangement according to one of claims 1 to 12, characterized in that that the adjustment speed stage (98) reduces the reference duration by a fraction during each detector cycle the difference changes in order to reduce the difference incrementally towards zero. 14) Arrangement according to one of claims 1 to 13, characterized in that that the adjustment speed stage (98) is responsive to the direction and magnitude of the difference. 15) Arrangement according to one of claims 1 to 14, characterized in that that the third counter (1o2) is an error counter which counts a number of clock pulses which are a measure for is the difference between the duration of the fixed number of periods and the reference duration, and that is the count value of the error counter is reduced to zero by the adjustment speed stage (98). 16) Arrangement according to one of claims 1 to 15, characterized by a stage (1oo) for generating a display signal in the event that the reference duration is the duration of the fixed number of periods and that the ringing signal circuit (112) 13o) - 36 - 509835/0728 a stage (13ο) that responds to the display signal for Contains generation of the ringing signal. 509835/0728