DE2505720C3 - Data registration device for cameras - Google Patents

Description

The invention relates to a data registration device for a camera, by means of which the differences before data can be coded for storage in a register during image acquisition and the memory content of the register can be read out by a decoder in order to use recording head elements on the film to be recorded.

Recently, there have been various types of electronic cameras with built-in electronic circuits for electrically controlling the shutter mechanism or the shutter in the market of which some have image capture information display devices while others have the capability to register or record some information in certain appropriate places on the film is provided. Among the most desirable when recording an object with a camera too registering data includes various types of information about the image acquisition as well other data such as data to be entered outside the camera, it being for the photographer It would be convenient if this at the same time as the image was recorded at a specific, suitable point on the film would be recorded, so that there is a great demand for one with a corresponding registration device equipped camera prevails. As for this type of data registration, control the camera digitally even has remarkably complicated circuits thanks to the new advances Conventional digital technology with only low power consumption can be built in such a compact manner that such a device can easily be built into a compact camera. So far there have been many such registration devices proposed; the known facilities are constructed so that they the digital information processed in the camera on the film in the form of a digital code ίο which has been decoded into common characters in any suitable manner.

There are also devices known for cameras with which manually adjustable data can be recorded on the film simultaneously with a recording (DT-OS 21 04 324). These devices contain transparent rings carrying the data to be recorded, which can be adjusted from the outside by means of corresponding setting rings carrying the same data and whose data can be projected onto the film by means of an illumination lamp and a lens system. Apart from the mechanical complexity associated with this known device, it is not suitable for simultaneously recording the recording values determined by a digitally controlled camera on the film.

The object of the invention is to create a data registration for a camera, by means of which both manually Data that can be entered as well as photographic data originating from digital processing by the camera cannot be coded in the form of letters, numbers, etc. can be registered with a recording on the film.

This object is achieved according to the invention by a data registration device with the features of Claim 1 solved.

According to a further development of the invention, the Beiich Direction of the film can be controlled by the recording head elements in accordance with the film sensitivity.

Furthermore, it is advantageous that the reading out of the register and the data recording by means of the Recording head elements are controllable by means of position pulses that control the movement of the film correspond.

The invention is explained below using an exemplary embodiment with reference to the drawing explained in more detail.

Fig. 1 shows the circuit diagram of an inventive Data registration device for cameras, FIG. 2 shows the circuit diagram of the data input part of FIG Device according to fig. 1 represents

FIG. 3 shows the timing diagram of the data input part according to FIG. 2 applied signals, F i g. 4 shows the circuit diagram of the data storage part of the device according to FIG. 1 represents

FIG. 5 shows the timing diagram of the data storage part according to FIG. 4 signals applied,

F i g. 6 shows the circuit diagram of the recording control partly the device according to fig. 1, FIG. Figure 7 illustrates the timing diagram of Figure 7 The recording control part of FIG. 6 applied signals,

Figure 8 represents the diagram of the data recording or-registrierteilsder device according to Fig. 1 represents, ^ft 5 9 shows the arrangement of the Belichtungsdiodei relative to the register or recording material.

In the representation of the circuit diagram of the data registration device for cameras in FIG. 1 is with

Keypad for recording various types of data not originating from the camera, while 2 denotes a camera from whose data processing device various types of image recording information are taken as digital information. A binary coding circuit 3 contains a bounce minimizing circuit and generates codes which are created both as evaluation signals Wi, Wj, W ₄ and W «and as a logical coding signal FU and as a left shift signal LSFW . The signals Wi to W ₈ and FU are converted into serial (temporally successive) signals by means of a parallel-serial converter (time division multiplex generation circuit) 4, so that digital information signals DAEN are input into the memory circuit. A register input gate circuit 5 of the memory circuit takes the digital information signals DAEN, the left shift signal LSFW, the logic coding signal FU, a right shift signal RSFW, an _{intermediate register signal Q n} -I, a register end signal Q _n and a readout signal Q _{n +} 1 a gate control, with its output signal a Register 6 is supplied. The dynamic register 6 forms the main memory part, the intermediate register output signal Q _n - \ being applied to a right shift gate circuit 7, while the register end output signal Q _{n is applied to} a readout module 8 for left shift control and decoding intermediate storage. The register output signal Q _{n of} the register 6 is also fed to a display device with a display buffer 9, a decoder driver 10 and a display 11 in such a way that, for example, letters or numbers are displayed with four digits in 7-segment representation. From the register 6 read-out signals WL ₁ to WLs taken via the read-out circuit 8 are entered in a decoding circuit 12 with a binary-decimal decoder and a decimal-point decoder, so that they can be input with the aid of timing pulses R \ to /? 5 from a Clock counter 17 is decoded into dot pattern signals Q to Q and amplified by a driver 13 to form lamp signals L \ to Ly , with the aid of which a dot pattern register head 14 with light-emitting diodes of a plurality of matrices flashes in such a way that letters or numbers light up. These light-emitting diodes (LED) are used to expose the data to be recorded on a recording material 15, such as, for example, the film in the camera. In accordance with the movement of the recording material 15, position pulses PP synchronized with clock pulses are generated, which are recorded by means of a waveform regeneration and synchronization circuit (pulse shaper) 16 and counted by the clock counter 17 for conversion into the timing pulses R \ to R » which control the decoding in the decoding circuit 12 and the right shift signal KSFW as well as a memory command LATCH in chronological order. 18 is a brightness or exposure timing control circuit which generates a brightness control signal WRE in accordance with the input ASA of the sensitivity information about the recording film so as to control the brightness or the lighting time of the recording light emitting diodes in accordance with the ASA sensitivity of the film, so that a certain fixed exposure is achieved. Further, /? E a position signal PPD to generate the right shift signal RSFW and a Süeicherbefehls LATCH converted into a digital signal so as to Rechtsschiebetorschaltung 7 and the (Linksschiebesteuer-) readout circuit 8 in the stored or the memory circuit by means of the coming out of the clock counter 17 timer pulse to control.

By means of the circuit arrangement described above, the from the data processing part! the Camera 2 or the keypad 1 coming digital information converted into the time division signal and in the dynamic register 6 is stored when the left shift is performed. This saved content is shifted to the right by the trigger command so that it can be read out and processed by the decoder circuit 12 is converted into the dot pattern signal and then for recording on the recording material or film 15 the light-emitting diode recording head 14 as a lighting element in letter and number patterns for Brings shine.

The stored information is decoded by the display device in such a way oali they are visibly displayed in the form of letters or numbers on a certain fixed position of the camera.

Each part of the data recorder is explained in detail below, with the same parts, as in Fig. 1 are denoted by the same reference numerals.

The F i g. 2 represents the data input part according to FIG. 1, where 1 is the keypad with a plurality of key switches SP ... O. The binary coding circuit 3 includes NAND gates 21i to 2I ₅ , a NOR gate 22, a monostable multivibrator 23, flip-flops 24 and 25, AND gates 26 and 27, an OR gate 28 and inverters 29 and 30, the NAND gates 211, 2I ₂ , 2I3, 2I4, 2I5 generate the logical output signals or evaluation signals Vi, Wi, Wi, W * and W ₈ , respectively. When a switch is turned on, a logical "0" is generated. All these keys serve as input for the NAND gate 21, or for the NAND gate 2I ₂ , so that when a key is switched on either the output signal Vi of the NAND gate 211 or the output signal Wi of the NAND gate 2I ₂ becomes »1 " will. This changes the output signal! KN of NOR gate 22 from "1" to "0".

The drop in this output signal KN triggers the monostable multivibrator 23, so that the multivibrator output signal MM becomes "1".

When this multivibrator output signal MM is “1”, a first start pulse TWE is applied in order to set the flip-flop 24 to “1”. The multivibrator output signal MM returns to "0" after a certain fixed time through the time constant circuit, the flip-flop 25 being set at the same time as the start signal TWE rises, if the key is still depressed, so that the left shift signal LSFW is generated as the output signal and TWE is retained until the next start pulse. The left shift signal LSFW is therefore held in the "1" state for the duration of a word.

Fig. 3 illustrates the time chart of the voltage applied to the data input section according to Figure 2 signals, the clock pulses are indicated by CP, the existing of square waves with a certain fixed repetition rate, at the same time with the falling of the clock pulses, the timing pulses TB _0, TBu TB ₂ and TB ₃ generated. Four bits or binary characters from TSb to TBi form a binary digit that is generated in the order D ,, D ₂ , Dj and D * . Four binary digits from Di to D ₁ form a word, where the

Start pulse TWE is generated in phase with a timing pulse TBi in such a way that the fall of the start pulse TWE is synchronized with the rise of the digit signal D \.

From the timing diagram in Figure 3 it can be seen that the first binary digit of a word is formed by the digit signal Di; this digit signal D \ and the left shift signal LSFW according to FIG. 2 recorded by means of the AND gate 26, so as to generate the logical coding signal FU.

In FIG. 2 also contains the time division multiplexing circuit or the parallel-serial converter 4 AND gates 311 to 3I ₄ , OR gates 32 and 33 and inverters 34 |, 342 and 34 ₃ , the information of the various keys being entered in this converter 4. The different key input information from the keypad is input to the NAND gates 2h, 2I ₃ , 2I ₄ and 21s and converted there into four binary characters to generate the evaluation signals Wi, Wi, W ₄ and VVb as output signals that correspond to their respective values in the time division multiplex process with the aid of the timing pulses TB ₀ . TBu TB ₂ UnO TS _{3 are applied} via the AND gates 31 |, 31 ₂ , 31 ₃ and 3I4 to the OR gates 32 and 33 in order to produce the digital information signals DAEN as their output signal. Further, when the input signal from an external register such as a register in the data processing device of the camera into the input terminal EXT. REG. is input for the external register according to the drawing and a signal RWSTR is input for the duration of a word, these are output via the OR gates 28 and 33 converted into digital information signals DAEN and the logical coding signal FU . These output signals are fed to the memory part as shown in FIG. 4.

The I "ig.4 shows the memory part of the device according to FIG.], The input terminals of which contain the digital information signals DAEN, the logical coding signal R / and the left shift signal /..9FW from the circuit shown in FIG. 2 together with the right shift signal RSFW and the memory command LATCH from the / il'fcriHimsetzschaltting 19 shown in Fig. 1 (or 6). The RegiMereentangslor circuit 5 includes AND gates 35i to 35 ₄ , 36 and 37, an OR gate 38 and inverters 39i, 39? and 391, As shown in Fig. 4, the digital information simulation signals DAEN are input to the sub-registers DSR \ and DSRi of the dynamic register 6 when shifting to the left or extracted when shifting to the right by the gate building 5. The output signal of the OR gate 38 is namely in the register DSRi is entered with a coupon of 12 bits or, respectively, Binttrzoichen, the output signal of which as an intermediate register signal Q ,, - \ via a right shift training 7 forming the AND outter is fed to the 4-bit part register DSRi . In doing so, these registers execute a cyclic operation by means of tier clock pulses CP.

The Ausgitngssignal Q _n of the sub-register DSRT is input as Rcgistcrcndsignal the Daton readout circuit 8, by four gates, nUmlich which the circuit 8 forming AND gates 4Oi to 40e ODF.R-Gattcrn 411 to 4h and the flip-flop 42i to 42 _4, the recording b / w. Auslcscsignulc WLu WLi, WU and W / * iils Ausgungssignulc generated. The signal Q _{11 is} applied to the OR gate 38 by the logical product of LSfW and RSFW, the signal Q _n + 1 by the logical product of FU and LSFW and the signal Q _n - \ by the logical product of FU and RSFW and fed back to the input of the sub-register DSR \. Furthermore, the left shift signal LSFW or the storage command LATCH are input to the read-out circuit 8 via the OR gate 43, while the flip-flops 42 | to 42 ₄ are triggered in succession by the clock pulses.

In the circuit arrangement described above, the interruption and reading out of the data are carried out in accordance with the timing diagram shown in FIG. The logic signal FU serves as an interrupt input terminal of the register 6, wherein there is a register input signal from the pulse train of the Digitalinformationssignalc DAEN in the generation of the logical encoder signal FU, while the left-shift signal LSFW causes the normally rotating with the return of 16 bits register 6 with a cycle of 20 bits circulates. If, as shown in FIG. 5, the coding signal FU and the left shift signal LSFW are generated simultaneously by the key input, the digital input signals W ₈ to W are interrupted at the lowest point above which the content of one bit to 12 bits is arranged, which is pushed to the left. When the left shift signal LSFW becomes "0", the register 6 begins to circulate with 16 bits, during which time no change is made to the data for each start signal rWif. In this way, the data is stored in register 6 during one word.

The reading out of the data from the register 6 is carried out according to the illustration in FIG. 5 in such a way that the right shift signal RSFW and the storage command LATCH are output from the digit set / switching 19 while synchronizing with the rise of the start signal TWE, with the same / hastily three digits for the right shift signal W.S7 "and a digit for the storage command LATCH are generated so that the lowest digit of the data stored in the register f> is read out as WU to W / .i and the next digit in the Rcihenfolgu is shifted to the right by GE in Zeitaufeinanderfol read Auslescsignalc W / * to W / .i be in the Dckodiersclmllung 12 according to FIG input I Similarly, the timing pulses Wi to X, and the signal WW to be in the Dekodicrschaltung 12 /...: ¹ to control the brightness or the (retraining) /.cn as

so entered registration head 14 provided Lcuchtdioclcn, whereby the Dlgitulinformotioncn in the for Record suitable Mutrix point pattern sign be converted in such a way that the light-emitting diodes of the Bclcuchtungsclcmcntgruppc made to glow

SS are used to generate a recording code in the form of Receive letters or numbers.

The Fig.6 represents the register structure while the F i g. 7 the timing diagram showing the relationship between the position impulses, the witness

bcimpulsen and the Hclligkcitsstcuersignal WRE represents. The movement of the film as a recording material IS in the drawing corresponding position pulses are synchronies in mild Sturlimpulsen TWE (and thus also with the clock pulses CfV Positionsimpulssignalc PPD reacted catalyzed by means of Synchronisicrschaltung 16 gctriggcrte by the Sturlimpulse rW £ flip-flop 44i, 44; and 441 and an AND gate 45. These pulse signals

7 8

PPD are used for one cycle of the register AND gates 6I ₁ ... 6I ₅ and an OR gate 62

generated and in the clock counter 17 with flip-flops 46i, 46 ₂ existing driver circuit for reading out the deco

and 46j and AND gates 47i ... 47 <j input, read out signals WU to VVLi are used in accordance with

whose outputs the timing pulses R \ to R _H mung with a respective series of timing pulses

are produced. On the other hand, as shown in Fig. 5, Ri to R5, where those corresponding to the pattern

the representation in the time diagram in Fig. 3 by means of information in chronological order as a

output signal generated by the clock pulses CP-triggered flip-flops 49i, 49 _2. Be that way

and 49j and a NAND gate 50 the binary characters - the readout signals WLi to WU by means of the diode dimensions

pulses TB ₀ to Tßj and decoded with the help of the from the trix circuit MTR in the dot pattern, whereby

Pulses TBi converted by means of an inverter 51 the signals decoded in this way by the driver circuit

pulse c TBj triggered flip-flops 52, 52 _; and 52j and Hing MDPm in chronological order, respectively

a NAND gate 53 the digit pulses Di. D ₂ , Di are taken from the timing pulses Ri to Rs,

and Da generated. Further, by forming a logical product Weil in the above-described process

from these pulses TBi and from the digit pulses the timing pulses R \ to /? <·, in accordance with

sen Ο * by means of an inverter 54 converted pulses 15 of the position of the Aufzichnungsmatcrials 15 generated

D ₄ in an AND gate 55 will be the slart pulses, when the position R \ des is passed

TWE generated. Then, by forming a recording logical material on the recording head, the

Product of the timing pulse R ₈ at the output of the driver circuit MDP by means of the timing pulse Ri

Clock counter 17, the position pulse PPD and operated in such a way that, for example, in the case

the pulse D _{4 converted} by means of an inverter 56 thatclie Auslcscscsignalc WLh to WLi in each case the values

Pulse D ₄ in an AND gate 57 of the digit conversion 0, 0, 0, I correspond to the output signals

Circuit 19 the right shift signa! RSFW received. Lamp signals Lj and L _{7 are} generated so that at

By forming a logical product of the output using seven lined up

signal of a flip-flop 58, to which the output signal of the light-emitting diodes LEDi to I.EDj as a recording head 14

AND gate 57 is input and that of the 25 as shown in Fi g. 9 only the light emitting diodes

Pulses TIh is triggered, and the output signal LEDi and I.EDj of this light-emitting diode group 14 aul-

of the AND gate 57 in the AND gate 59 will light up, whereby at the position R \ 'of the calibration

.LATCH memory command is generated and only the light emitting diode is added to the register part! I.EDi and

fed. Be exposed by generating pulses in a location corresponding to the I.EDj. To the-

Position pulse PPD triggered monostable multi-30 accordingly with the position change of the

vibrator 59 'in the HcHigkeilsstcuerschallung 18 and Auf / eichnur.gsmalerials from R \' to RV the den

Adjust the film speed of the line pulse corresponding to the recording positions R 'to Rs'

materials 15 at a variable resistance til) Ri to Ri generated in such a way that the

With this circuit, the timing pulses Ri to R ^ are obtained at the output OS on the diode matrix

Brightness control signal WRE The llelligkeitssieuersi- 3s corresponding signal is read out so that a

gnal VVR / -. ' is exposed in the number "I" on the recording material to control the current conduction time

Decoding circuit 12 entered. By means of this becomes. Li according to the invention are seven light emitting diodes !! in

SiromleUinstruktioti arranged by the lielligkeitssteuersignal a row as well as for mapping a

IVR / -. "Can control both the Stromlciisielle as a letter or a digit of the letter or the

also the power routing time is divided into five columns regardless of the length or 40 digits, so that the arrangement;

the return of the position impuir.e PPD '. carried out the seven light emitting diode !! in a row is sufficient

will. When the octal clock counter i / the witness- during / to keep the exposure of the same

luMinpuls Wher / eugt. will / wischenden / ifFernimpulscn Punktmusiers. as in the case of birth in general

Di and Di the position impulse PPI.) Tins right a total of 5 ^r > LEDs (7 χ 5) are required, see above

Shift signal R.S '/' Wer / .cugt, whereby during the first 45 that the small space requirement weighed the inventive

Digit of the mailbox signal R.S '/' Wder Speiclu'r-appropriate direction as a Dalenrcgistncreinnchtung for

incorrect LAICH is released, so that the lowest small (! crate like cameras is very useful.

Number of the register f> in the exclusion 8 as if, however, a letter or a number

Buffer memory for the trigger signal « WLt to IV / .ι the recording material recorded at once

is entered. In this way it should be synchronized with 50, there are lünl Spuliu »

the rise of the position pulse PPD the register 6 with seven disordered Lcuehtdiödcn in a row

through dus Rechtsschicbesignul RSI ⁷ W me right dcruri / u use that the lines with the

shifted and the clock number ¹ 17 on the output of the above-mentioned positions R \ to Rs so in correspondence

Timing pulse Ri advanced. Thus, the determination will be made that a position signal PPD The content of the trigger circuit 8 is generated in the form of the trigger signal SS when the recording head passes the film,

le IVLi to WU only during the existence of the whereby the Leucludlodcn of the position Ri 'cnlspre

Stromleitinstrtiktlon through the Hclligkcitssicucrsignal related column by the timing pulse Ri / um WRK can be decoded and illuminated in the Mairix-Pimkt-Mustcrsignal; this way the

implemented. LEDs corresponding to the positions Ri 'to Wj'

FIG. 8 shows in detail the arrangement of the columns in accordance with the timers

niing of the driver and decoder cooling for pulsing Wi to Rj in succession to the candlestick

/ s of the brewed in chronological order, so that the letter or number according to

Auslesesignalc WU to WL, in which the Auslcsesigmtlen WL \ to WU itufgc for recording at once

suitable matrix-point-pattern signal, where MTR draws a

Diodon matrix circuitry, which is used to convert the 6s. The posilons output signals are PPI

digital information of the trigger signals WU to through the three Zcitgebelmpulse Re to Rn of the counter

Wl. \ On Dczlmalwcric these readout signals to the not decoded, so on these catfish the intermediate Decoded dot pattern. MDP refers to the space created between the letters. If all

If read signals WLn to WL \ have the value "I", no decoding is carried out, so that the space corresponding to a location is empty. According to the illustration above, the data stored in the register are decoded in succession and the film is exposed as a dot pattern so that the data is displayed in the form of letters or numbers as the film is developed.

In Fig. I the display part is shown with the display decoder, the driver and the 7-segment display, which is used to determine the content stored in the register. If for the display pattern and for the aforementioned Druckbzw. If the same system is used for recording patterns, the read only memory (ROM) is used in common to read out and display.

In addition 8 sheets of drawings

Claims (3)

Patent claims: 1, data registration device for a camera, by means of which different data can be coded during image recording for storage in a register and the memory content of the register can be read out by a decoder in order to be recorded on the film by means of recording head elements, characterized by data input Device (1, 3, 4) for converting manually entered data into a digital signal, through a connection (EXT. REG) for receiving photographic data which have been converted into a digital signal by means of a processing device of the camera (2), and through an OR -Gate (33), the inputs of which are connected on the one hand to the data input device (I, 3, 4) and on the other hand to the connection (EXT. REG) , the output of the OR gate (33) being connected to the register (6) is connected to supply the digital signal from the data input device (1, 3, 4) and that from the terminal (EXT. REG) at the same time to the register (6). 2. Device according to claim 1, characterized by an exposure control device (18) for Controlling the exposure on the film (15) by means of the recording head elements (14) in unison with the film speed. 3. Device according to one of claims 1 or 2, characterized in that the reading of the register (6) and the data recording by means of the recording head elements (14) with the aid of position pulses (PPD) can be controlled in accordance with the movement of the Films (15) are generated.