DE2505457B2 - - Google Patents

Description

The invention relates to a method and a circuit arrangement for the transmission of signaling information or data information the FSK principle between digital switching offices that communicate with each other via analog / digital or Digital / analog PCM converters are connected by analog lines.

In modern telephone and message transmission systems, the central offices are im Time division multiplex operated and controlled via a data processing system. Today's requirements that are placed on telephone services, especially in dialing technology for conference calls, call delay, selective voice or data transmission, Tariff announcements and the like are in the direction of a two-way transmission, which at the fastest possible speed for a large amount of data / is established to shorten the call processing time to a minimum. This not only demands secure monitoring of the information exchanged between different exchanges and switched connections, but also highly developed call systems.

Signaling and data transmission between the various exchanges or offices can be carried out without difficulty by means of conventional FSK modems with the same bandwidth achieve a higher transmission rate for speech channels

than the usual "in-band" calling systems.

In general, it is known to transmit audio signals and ringing signals in such a way that the analog Call information is digitized and the digitized patterns are transmitted (DE-OS 23 14 272).

Call systems are also known on composite channels in which the transmission channel for call data between the offices is the same as that for the speech and / or data connection between the participant: η is used.

These systems have better flexibility in terms of signaling between different ones Points of the network, enable short waiting times and give the participants access to others Channels.

The use of conventional modems, which work on the principle of route sharing, in such Systems has proven unsuitable because a large number of these modems are on a more centralized location location would be required to have switchable connections to all channels of the to connect the respective network. The number of such required depending on the volume of traffic and the duration of the call In terms of costs, space, power consumption, maintenance and operational reliability, modems would become a Bring a lot of problems.

The object of the invention is therefore to provide a method for transmitting signaling information or To provide data information in which the variety of previously used in telephone exchanges individual data transmission modems and PCM terminals through a single digital time division multiplex modem is replaced, which with its one end via the time division multiplex data channel to the central signaling processing circuit and the other end can be connected to the digital switching exchange via the usual 2 Mbit / s data stream.

This object is achieved by the measures of the characterizing part of claim 1.

On the basis of an exemplary embodiment, the invention is illustrated in the drawing and in the following explained; shows in the drawing

Fig. La and Ib in a Cartesian coordinate system the six Abtaslim pulses of FSK waveforms generated within one symbol period,

2 in a schematic block diagram the Connection of the modem according to the invention on the one hand to one with the digital switching network connected PCM groups and, on the other hand, to a data processing system of the switching office,

F i g. 3 shows in a block diagram the one shown in FIG. 1 with MT labeled transmitter part.

F i g. 4 ii a block diagram the in F i g. I receiving part marked MR,

5 shows in a tabular signal flow diagram of the binary values of the signal from a timing circuit CT in F i g. 3 generated clock and count signals,

FIG. 6 in a tabular signal flow diagram the binary signal values when passing through the logic network RL 1 in FIG. 1,

F i g. 7 is a comparison table showing the signal development in some of the circuits of FIG. 3,

F i g. 8 is a comparison table showing the signal development in some of the circuits of FIG. 4th

As is well known, in digital frequency modulation, depending on the binary number (1 or 0) to be assigned to the message information, each of the two sine tones, lau, is transmitted, the frequencies of which differ from one another and have defined intervals with respect to a mean reference frequency * in the speech frequency band.
For the digital generation of the

ι Sampling pulses of the waveforms is expedient a multiple of the sampling period selected for the duration of the binary digits to be transmitted; in the present Embodiment, this duration is 6 times the sampling period, namely 125 | isec with respect to

ίο the PCM system used.

In order to have a suitable spectrum of the modulated for transmission on channels with limited bandwidth To win a signal, a correspondingly suitable frequency is used and it is ensured that

π no phase jump occurs at the transitions from one frequency to the other.

To this phase continuity of the sampling pulses in the transitions of successive time intervals To ensure simple circuitry, the signaling frequencies should be an integer or half-integer multiple of the Üymbol repetition frequency be.

In the waveform of Figs. la is phase continuity given since the period of the waveform is equal to that

_> -, symbol period is; in the waveform of FIG. Ib is on the other hand, a phase reversal by 180 ° is required after each symbol period; as in the following This operation is explained by simply reversing the sign within the symbol period

accomplished in transmitting sampling pulses.

F i g. 1 shows the sequences of six sampling pulses C1, CI ... C6 of the two FSK waveforms assigned to a symbol period; In detail, the sampling pulses of Fig. la generate the symbol 1 associated

! · ■. ge waveform and that of Fig. Ib that of the symbol 0 associated waveform.

In order to have the symbols assigned to these symbols in a PCM system with a frame period of 125μ5εΰ To transmit waveforms, six as-fine

Hi the following PCM frames set six time stamps with each time stamp in digital form the absolute value and the sign that have been assessed accordingly each of the scanning pulses Cl, C2 ... C6 to be transmitted contains.

it Although the modem explained here can also be used for other PCM systems, the following is based on a PCM time division multiplex system for 32 channels with 8 bits per sample.
Fig. 2 illustrates any digital distribution

vi switching network RC, which operates on the basis of the time division multiplex system and is applicable to electronic telephone exchange.

MN here means the digital time division multiplex modem according to the invention, which consists of a

v. Switching network RC via a line 2 connected transmitting part MT and a here / un connected via a line 1 receiver part MR existing *. The data set up for PCM technology and containing 8 bits per time stamp pass in parallel

mi shape the 32 channels of line 1 in the input direction and the 32 channels of the line 2 in the output direction, but the summary made once Solution of the 32 channels on line 1 and the 32 channels remains on line 2. Furthermore, the

(.-, for the sake of simplicity it is assumed that one of 32 possible configurations for the time division multiplex modem MN corresponds to each of the 32 channels, which means that the modem according to the invention can be used without limits

but not restricted, since it is known that the digital switching network RC connects each of the 32 PCM channels linked on the input or output side to the modem MN via lines 1 and 2 with any channel of a PCM system entering or leaving the switching station.

A data processing system UED, in particular monitoring the time division multiplex in the central office, is coupled to the modem MN , which receives from the receiver part MR of the modem AfW over a line 3 the zcitmultiplex signals demodulated with respect to each of the 32 PCM channels of the line 1 and is fed to the transmitter part / V / T via a line 4 which transmits time-division multiplex signals to be modulated with respect to each of the 32 PCM channels of the line 2.

Accordingly, ni \, nn ... m, ... mn represent configurations which are recorded by the modem MN in the 32 line marks of the PCM frame via lines 1 and 2. Correspondingly, in these configurations C], es ... c, ... Ch represent the time stamps of the frame.

Transmitter part

In Fig. 3, CK is a timing circuit that generates the following clock signals both for the receiver part MR and for the transmitter part MT:

CR For the recognition of the address of the configuration m, or the time stamp c, on the receiver side;

Cl for the recognition of the address of the configuration m, or the time stamp c, on the sender side;

TL for the clock sequence of all logical circles.

RIA, RL2 and RL3 are logical networks, of which the network RL 2 has an exclusive OR function and the network RL 3 has an exclusive NOR function. LR denotes a digital delay line which contains six memory cells for 32 addresses recognized by signal C1 to be controlled in time division multiplex. MX 1 is a conventional multiplexer with several inputs and one output.

A timing circuit CT generates two counting signals TC and TB of the module 6 and module K type in time division multiplex for each of the 32 time stamps c, where K represents the given number of signals resulting from the usual length of the messages processed by the modem MN given is.

MB denotes a buffer stage that receives the data supplied via line 4 from the data processing system UED in parallel representation, which are processed by the modem MN during each of the 32 time stamps c, in time multiplex, as well as the asynchronous display via the idle or working status for each of the m, configurations of the modem in the corresponding time stamps c _h

The buffer stage MB controlled by means of the clock signal Cl outputs the data containing the m, configurations of the modem synchronously with the PCM frame of the line 2 in time division multiplexing on a plurality of K lines 5. A synchronous signal TR for the idle or idle mode arrives via a line 6 Working status of the modem configuration to the timer CT, which is also controlled by means of the clock signal CI. The synchronous signal TR triggers two counting sequences in the timing circuit CT. With one counting sequence, the counting signal TC is generated and sent to a line 8, while the other counting sequence is the counting signal! TB generated and on a line 7 is.

The in F i g. The table shown in FIG. 5 shows the correlation between the synchronous signals TR, the clock signals Cl and the counting signals TB and TC. In Fig. 5 shows the / th configuration of the modem as an example; this configuration has been taken into account for a certain number of PCM frames, this configuration corresponding to the / th time stamp.

In order to be able to follow an entire message, a number of time stamps greater than K have been shown.

! m execution example! can only use the values for JIc synchronous signals 77? freely chosen who other values result from this.

In a certain configuration w, of the modem MN corresponds to c, in which the Taslsignalc Cl in V ig. 5 shows a time interval of 128: 32 = 4 usec.

In accordance with the PCM frame, these time intervals each have a duration of 125 nsec.

The synchronous signals 77? can only ever do one of two possible with the transmitter of the time mark c Accept values, namely the value 0 in the idle state of the modem or the value 1 in the working state de < Modems.

The counting signal TC is triggered at the line mark c , which follows the time mark at which the synchronous signal?.! TR has the value 1. It starts at 0 and continues to count by the value I until it reaches the value 5. As long as the synchronous signals retain the value 1, the counting cycle starts from the beginning.

The counting signal TB is triggered at the time mark c, which follows the time mark / u which the second counting cycle for the counting signal TC begins. d. h "after the TC has assumed the value 0 again. During this second counting cycle of 7 "C, the counting signal TB assumes the value 1 and increases it by I as soon as TC has fallen back to 0. Until the value K- 1 is reached, after which the synchronous signal TR begins for a new counting cycle retains the value 1.

Whenever the synchronous signal, for example to the one shown in FIG. 5 separately marked time mark c, ⁴ -, assumes the value 0, both counting signals Tl nnrj 77 ~ hpi i \ pt närhstfolppprlpn Zpitmarke deleted which is triggered and controlled by the timing circuit Cl designed for this purpose.

At each time interval c _h which is related to one of the m configurations of the modem MN , the multiplexer MXi is set to one of the K lines of the connection 5 in accordance with the counting signal 77?.

According to the 9 information given from the multiplexer MXL on the line and the übp- a plurality of lines 8 from the timing circuit Cl incoming count signal TC generates the logic network RL 1 on the output line 10 as> sign and on the output line 11 of the absolute value of the to be transmitted, in the table dei F i g. 6 appearing sampling pulses Cl, C2 ... C6.

This table in FIG. 6 shows the special task of the logic network RL 1, which transforms the logic values serially supplied by the multiplexer MX 1 via the line f into sampling pulses of an FSK signal, which were already stored in the logic network RL 1. These sampling pulses are of the PCM type and are transmitted in parallel octets on a plurality of 7 output lines! 1 and given to the output line 10.

As already explained at the beginning, the Dauei corresponds one the data processing system and then c

the signal leaving the multiplexer MX 1 of 6 times the duration of the scan time given by 125 jisec and thus of a PCM frame; this ratio I: 6 is determined in the logical network Kl. 1 by the count signal TC and corresponds to a module 6 count expressed by three bits ( column TC in FIG. 6). The output signal of the data processing system has either the value 1 or 0 and is represented by a bit which is assigned to line 9 and appears in column 9 in FIG.

) e after the binary configuration of this signal and the counting signal TC on line 8 is obtained at the output of the logical network Rl. 1 in parallel on the 7 lines of the connection 11 binary digits which correspond to the coding of the value of each of the six scanning signals in a predetermined order of that FSK signal which is characterized by the BiI generated on the line 9. The bits generated by the logical network Kl. 1 on line 10.

correspond.

The pulse train on line 9 as well as the initial signals on lines 14 and 13 are arbitrarily given, while the signals of the other lines result as follows:

The signals on line 10 are obtained by transmitting columns 9 and 10 from FIG. 6; the signals following the start signal on lines 14 = 15 = 16 result from the previously explained operation of the delay line L / ?; the signals on line 13 result in turn from the previously explained operation of network Kl. 3 and those of line 18 from the operation of network RL 2. The signal on line 2 contains the digital value of the scanning pulse on line II and its sign on the line 18. As FIG. 7 shows, dl: continuity of the phase through the when the signal 0 appears from the network Rl. 2 performed sign reversal guaranteed.

riciri'riiCii uct «iciric cti'ics t ^ .ivi - \; mcus, yiui ud-> sign of the scanning signal in relation to the absolute value on the line 11 again and has the value 0 if the scanning value is 0 or positive ( C \, Cl, C6 in Fig. La and Ci. C2, C'4. C5, C "6 in Fig. Ib) and the value I. if the sample is negative (C3. C'4, C'5 in Fi g. la and C3 in FIG. 1b).

The logical network Rl. 1 therefore acts as a read-only memory that is addressed by input signals on line 9 and on line 8 at the same time.

In FIG. 6, the addresses appear in columns 9 and TC and the output values in column 10 for the output on line 10 and in column 11 for the outputs on connection 11. The associated scanning signals are in column FSK Cl (0) ... C6 (0) of the signal series FSK = 0 and Ci (1) ... Cb (I) of the signal series FSK = I noted.

The from the delay line LR and the logical networks RL 2 and Rl. 3 circuit is used to reverse the sign at the end of each symbol for FSK = 0.

The delay line LR (FIG. 3) receives the synchronous signal TR of the buffer stage MB via the line 12 for a period of I25nsec depending on the key signal C / and sets its memory cells to 0 when the synchronization signal 77? has the value 0, regardless of the logical value of the incoming signal on line 13.

As soon as and as long as the synchronization signal 77? has the value 1, the delay line LR transmits with a time delay of six times 125 μβεΰ the logic signal from the line 13 as an output on the line 14, 15, 16. The network RL 3 , effective as an exclusive NOR gate, outputs the signal line 15 to line 13 when the logic value of the signal taken from multiplexer MX 1 from line 9 via line 17 is 1 If this value is 0, gate RL 3 forms the inverse value of the signal passing through line 15 and gives this value to line 13.

The network RL 2 , which acts as an exclusive OR gate, sends the signal on line 10 to a line 18 if, for example, the logical value of the signal on line 16 is zero. In contrast, if the sign on line 16 is reversed, it generates the supplementary value of the signal value on line 10.

F i g. 7 shows five signals, each of which contains six bits, corresponding to the binary configurations on lines 9 = 17, 14 = 15 = 16, 13, 10, 18, 2

MIL '1, UIIlIIIgUII Il UIIU IO UIIUCIl / USiI I! I Il IUII UUII

Output 2 of the transmitter part M7 "for the for each channel PCM load pulses to be transmitted in parallel.

Receiver part

In the FIG. 4, CK again means the timing circuit for generating the clock signals CR, Cl, TL required in the receiver part. LD is a digital dynamic limiter that limits the amplitude of the PCM samples of the FSK signals received via line 1 to suppress the noise effect. A digital frequency discriminator D / V is connected to this via a line 19, which is controlled by the timing circuit CK with the clock signal TL and separates the two FSK frequencies F1 and F2 from the incoming signals on the line 19.

The sequence of sampling pulses applied to output line 26 represents amplitudes which are a function of these frequencies FI and F2. The value of these sampling pulses changes depending on the discriminator DN currently used.

SO i is a logic which responds to a threshold value of the sampling pulses and outputs a two-stage pulse train to its output line 29; Each step or each level represents a specific correlation with the frequency F1 or F2 in relation to the PCM sampling pulses received via the line 1.

The scanning pulses leaving the discriminator DN on the line 26 reach the input of a further logic MO3 via a line 28, which takes the absolute value from these pulses and feeds the result to a digital low-pass filter FN via a line 30 - a known circuit technology , however, required operation once signal rectification in logic MO 3 has been performed

The filtered sampling pulses pass via a line 31 to a logic 1 SO similar logic SO 2, the pulses with a soft compares with respect to the particular for the logic 1 SO different threshold value, and outputs a two-stage logic signal to its output line 32; The criterion for one stage is that the threshold value of the logic SO2 is reached or exceeded, and for the other stage that the threshold value of this logic has not been reached. Each of these signals corresponds to the presence or absence of a suitable signal on line 1 and causes a common one

AND gate PX switching the signal on line 29 through to a line 33.

The task of the logic chain MO 3, FN, SO2 and P \ is to block signals on the line 29 which can be traced back to a noise occurring in the transmission path, the amplitude of which on the line 31 therefore does not reach the threshold value assigned to the logic SO 2 . However, signals that originate from sampling pulses of the FSK transmission are switched through.

P2 is an AND gate with two inputs. The first input 34 receives the impulses originating from the Ciatier PX , while the second input 36 receives impulses which were present at the first input 34 in a previous cycle (for example in the previous cycle 125 jisec) and through a conventional digital delay line / "have been delayed accordingly.

The AND gate P2 switches a pulse with the value I at its output 37 when both input pulses have the value I. The output signal of the value I is fed to the first input of a logic network RL 4 , the second input 38 of which is controlled by a signal IN and which emits a signal of the value I at its output 39 if a signal of the value 1 at least at one of its inputs is applied.

The signal IN supplies a decoder D 1, which is controlled by a signal BRR which is generated by a timing circuit BCR operating in time division multiplex on the channels scanned by the clock pulse CR . The timing circuit BCR is in turn controlled by a signal RR supplied via the output 39 and is synchronized by the clock signal TL. The timer circuit BCR makes two counts. of which the first count, which generates a signal CRR, is triggered with the signal RR and creates a module 6 cycle, while the second count, which generates the signal BRR, creates a module Ai cycle and then turns over one increases when the first count has reached a counting position following the second counting position, for example counting position 3. A third generated by the timing circuit BCR , Signa! PB is always put on a line 43 when the signal CA? A? has reached a specific, given counting point, for example counting point 3, AC times, ie when a counting step of K -! adjusts.

The decoder DX is set so that it outputs an output signal from the value I, when the input signal has the value I, wherein the said output signal from the value 1 holds as long as the signal containing BRR cycle does not fall back to 0.

The signal CRR is decoded by a further decoder D 2 , which then generates an output signal CP with the value 1 whenever the signal CRR assumes the value 3, for example.

All of these signals are shown in the table in FIG. 8, in which at the beginning of each row the Number of the line carrying the respective signal or the signal identifier is noted.

As already in connection with the table according to FIG. 5, each of these signals relates to the same time mark c, or to the corresponding configuration of the modem MN.

It is to be assumed here that the signal sequence on line 34 is given arbitrarily and that all other signals result from this in the sense of the explanations given above. It is also assumed that the noise in the line 34 (row 34 in FIG. 8) still responds to the row circuit BCR , but does not generate a signal CRR with the value 3, so that the signals BRR and / Λ / are absent, whereby the timing circuit

^r > flCA? is set to zero.

So that the circuit responds sharply to these signals, it should be designed so that the counting only is triggered after three stages, which is based on statistical calculations with regard to the noise

ίο has proven to be sufficient.

Finally, FIG. 4 shows a shift register RS which operates in the time division multiplex of the 32 channels and the output signals of this gate from the output U of the gate PX via a line 40 in series

r> receives fed.

This register contains a number of positions corresponding to the number of channels. Every site that contains AC cells is progressively filled from above after being released by the signal CP. The clock signal CR

- ¹ H addresses the position with the data relating to the respective channel. The position data are then put on a connection 42 in parallel.

The time at which all ai data of a message on a plurality of lines of this connection 42

2Ί are present, is recognized by the signal PB generated by the timing circuit BCR on the line 43; Together with the signal on line 43, these signals are fed to the data processing system UED via connection 3.

As soon as the timer BCRtWc has counted out the entire message, it is automatically set to its initial state with a signal BRR of the value 0 and remains in it until the beginning of a new message coming from the line 39 of the logical

r> Network RL 4 is not recognized.

Mode of action

The function of the modem MN in connection with the processing of a signal transmitted by the 4 () transmitter part MT and a signal received by the receiver part MR should , for the sake of simplicity, only relate to the ni, configurations of the modem (VfiV bc / .icMcii and in the corresponding time for all other configurations apply.

transmission

The Ai asynchronous data that come from the data processing system UED and the 32nd

V) Configurations of the modem MN correspond to each of these configurations, together with the asynchronous statement with regard to the idle or working state.

The buffer level MB between the data processing

«Processing system UED and the logic in the transmitter part M7" of the modem MN delivers the data and the clock signal TR in parallel on the connection 5 or the line 6 synchronous to the PCM channel clock, ie with a periodicity of 125 yisec, controlled by that of

ω of the timing circuit CK generated clock signal Cl.

The signal TR supplied by the buffer stage MB triggers the signals TC and TB in the timing circuit CT in accordance with the counting method in the table in FIG. 5 off, with this signal 77? the delay line LR

b "> causes either those arriving on line 13 To let signals go through or to set their content to 0.

Asynchronous data present on line 5

arrive at the multiplexer MX 1, which, depending on the address determined by the counting signal TB , selects the data to be transmitted on the line 9, which then together with the signal TC coming from the counting circuit CT over the line 8 in the following logical network RL 1 according to the Table according to FIG. 6 can be processed.

The sign and absolute value of the sampling pulses are obtained on the output lines 10 and II of the network RL 1.

An FSK signal sequence. resulting from signals with the Value I, means no sign reversal, between one and the next following signal; a precautionary measure is made by the Signal value 0 given; after this signal value would come at a signal value I or 0 results in a sign reversal that corresponds to a phase jump of 180 ", as shown in FIG. 1 shows.

This functional sequence, which is per se disadvantageous, counteracts the logical network RL 2 in that it can reverse the sign on the line 10 as a function of the signal on the line 16.

Signals of the transmitter / V / 7 "on the connection line 2 correspond to the PC'M coding of the FSK sampling pulses. The digital switching network of the electronic central office into which the modem is connected M / V is involved, allows it. which are processed according to the respective configuration of the modem Forward signals in a specified transmission direction and through digital / analog conversion PCM sampling pulse trains in analog FSK signals c so reshaped so that they can be transmitted on a voice channel.

Kpfang

The eight hits assigned to a PCM time mark are present in parallel on connection 1 and correspond to the time-division multiplex coded sampling pulses that the PCM input circuit, not shown in the drawing, is derived from the received analog signal Has.

The dynamic limiter LD receives this sampling pulse sequence fed in parallel and forwards it to the line 19 with an amplitude grunt for noise suppression.

The frequency discriminator DN separates the sampling pulses corresponding to the two FSK frequencies and delivers to its output line 26 a pulse train whose amplitude is a function of each of the two FSK frequencies in accordance with the amplitude-frequency characteristic of the discriminator DN.

These sampling pulses are transmitted to the logic SO 1, where they are compared with a specific threshold value for generating a two-stage sampling pulse intended for the gate Pi , each stage or level of this pulse being correlated with one of the two KSK frequencies.

The gate PX switches from the logic SO 1 to a line i3 only when it is via the logic chain MO 3, FN. SO 2 and the associated lines 28, 30, 31 and 32 contains a sampling pulse which displays an information signal on the lines 26 and 28, but not for signals that target noise Nrhnn <Irr amplitude control of the incoming sampling pulses By means of the logic chain MO 3. FN, SO2 and the reconstruction of the scanning signals with the value 0-1 by the logic SO 1, a continuous control of the scanning pulses with signal values 0-1 is also carried out to suppress false signals due to noise.

Since the duration of the incoming FSK signals on connection 1 corresponds to the six time division multiplex frames if no sampling pulse is lost, each of the FSK symbols theoretically also agrees with the six following! Sampling pulses match. With the circuit arrangement according to the invention, the signal duration can be checked on four sampling pulses by means of the components T and P2 (2 pulses for controlling P2 and BCR and two pulses for controlling BRR).

The first usable signal enables the timing circuit BCR, one in the table of FIG. 8 to generate reproduced signal sequence; after detection of the first signal, the timing circuit BCR causes for all K data of the message and through the intermediary of the signal CP via line 41 for each channel to transfer data to the shift register RS, and monitored by the signal PSauf line 43, the parallel implementation of the whole Aw weeding the connection 3 in the direction of the data processing system UED ajf.

In addition 6 sheets of drawings

Claims (1)

Patent claims: 1. A method for the transmission of signaling information or data information according to the FSK principle between digital exchanges, which are connected to one another via analog / digital or digital / analog-PCM converters by analog lines, characterized in that on the transmitting side the binary-coded data information via a digital Time division multiplex channel of the transmission side of a modem operating in time division multiplex, which converts the binary data (bits) into digital PCM signals by adding six successive code words consisting of eight bits to each binary element in suitable time slots of six successive PCM frames assigned to a digitized sample value depending on the value of the binary element to be transmitted of a first frequency ('ί) or a second frequency (fj) of two Spracfifrequenzen (f _x , f ₂ ) that the digital PCM signals via the coupling network to Digital / analogue PCM converter for the E Generation of FSK signals are switched through on the analog lines, and that on the receiving side, conversely, digital PCM signals are obtained from the FSK signals, which are switched through the coupling network to the receiver side of the modem, here in each time slot of the incoming PCM frame in the respective Frequencies are demodulated and refilted in order to obtain the binary data information according to the size of the transmitted binary element. 2. Circuit arrangement for carrying out the method according to claim 1, characterized in that a buffer stage (MB) is provided in the transmitting part (MT) of the modem (MN) , which the incoming data of a data transmitter (LJED) with a through the product of the duration a time stamp and the sampling frequency of the transmission system and outputs the synchronous signals for each message in parallel and serially for each channel to a multiplexer (MX 1). 3. Circuit arrangement for performing the method according to claim 1, characterized in that the sign reversal of the amplitude values to be transmitted in the event of a phase jump occurring between the two speech frequencies in a chain of logic networks (RL 3, LR, Rl2) connected downstream of the multiplexer (MX 1) takes place, of which the logic network (LR) designed as a delay line and the logic network (RLJ) connected in series with this maintain the respectively most recently performed sign change until the arrival of a signal that requires a new sign change. 4. Circuit arrangement for performing the method according to claim 1, characterized in that in the receiver part (MR) of the modem (MN) the transmitted sampled amplitude values of the FSK signals are filtered out in a digital dynamic limiter (LD) , at the output of which a frequency -Discriminator (DN) is connected, which, depending on the two speech frequencies, delivers different sampling pulses to a downstream shift register (RS) . 5. Circuit arrangement according to claim 4, characterized in that the shift register (RS) can be controlled by a timing circuit (BCR) which, in time division multiplex, generates a first pulse train (BRR) for holding the incoming message signals, a second pulse train (CRR) for feeding in one Signal in the shift register (RS) and a third pulse train (PB) for the data transfer to the data transmitter (UED) generated. in 6. Circuit arrangement according to claim 2, characterized characterized in that the multiplexer (MXi) from the timing circuit (CT) through the binary digits of a first sequence of, following the module of the number (K) of signals containing the message - Counting signals (TB) and the logic network (RI 1) addressed by the binary digits of a second sequence of subsequent counting signals (TC) running according to the module of the number of sampling pulses of the split signal to be transmitted 2u, whereby the respective counting sequences are represented by a signal representing the idle state of the modem in the corresponding time unit! (TR) are triggered. 7. Circuit arrangement according to claim 5, characterized r> characterized in that the timing circuit (BCR) in the receiver part (MR) sends the first pulse train (BRR) after the arrival of at least 7weier message signals corresponding to the number (K) of signals containing the message according to the module to running counting sequence, the second pulse sequence (CRR) after the arrival of at least the second of these signals corresponding to a counting sequence running according to the module of the number of scanning pulses of the signal to be transmitted and each pulse (PB) '"> of the third pulse train at each end one incoming message begins to generate.