DE2503152A1 - CIRCUIT ARRANGEMENT FOR DETECTION OF DEFECTS CAUSED BY COMPONENT FAILURE IN THE MULTIPLICATION UNIT OF A DATA PROCESSING SYSTEM - Google Patents

Description

Böb3ingen, January 22, 1975

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Official file number: New registration File number of the applicant: WA 972 010

Circuit arrangement for the detection of errors caused by component failure in the multiplication unit of a data processing system. ' ^^

Numerous applications of digital computers require not only a very fast, but also a highly reliable machine. The industry has enormously improved the reliability of the components. However, as completely reliable components always have not yet been developed, constitute improved error detection methods a practical alternative. The multiplication unit is a weak point in computers when it comes to calculation errors.

The multiplication in digital computers is generally carried out according to an algorithm that uses repeated addition. The circuitry required to put the multiplication algorithm by repeated addition into practice is complex and the multiplication operation may require numerous stations in this circuit, which increases the likelihood of a computational error due to component failure. The monitoring of the multiplication for the detection of calculation errors due to component failures turned out to be very desirable.

In order to detect errors in the multiplication unit of digital computers average, residual value methods were often used. These are described in more detail in U.S. Patent 3,167,645. - ■

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A known method for detecting errors in the multiplication unit of a digital computer seeks to make advantageous use of the residual value method through an overall residual value check e.g. Modulo 3. A predicted remainder for the product becomes generated by the following steps:

a) Generation of the residual values of the multiplier and the multiplicand,

b) Multiplication of the residual values with one another

c) Generation of the residual value of your product.

The remainder of the product of the remainder of the multiplier and the multiplicand, i.e. the predicted remainder, then becomes compared to the residual value of the actual product after the multiplication was performed to determine if a machine error occurred during the multiplication.

However, generating the final product may require many iterations of the same loop of the multiplication algorithm and the total residual value check. cannot discover every single machine fault. For example, if one error in the loop leads to several Errors in the end product or the errors produce a residual value of zero, i.e. the predicted and generated residual value match, the error will not be discovered by the entire residual value check.

One way of reducing the number of undiscovered individual machine errors in the multiplication unit consists in performing a residual value check after each iteration of the multiplication loop perform. When the multiplication algorithm changes the multiplicand according to one bit of the multiplier during each Processed iteration, the predicted residual value of the partial product can be determined as follows:

a) Generation of the residual value of the previous partial product and the residual value of the running addend, i.e. the multiplicand according to the current multiplier bit,

b) the residual values together

c) Generation of the residual value of their sum.

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The residual value of the sum of the previous partial product and the current addend then becomes the residual value of the actual of the current partial product after executing the current iteration to determine whether a machine error occurred during the current iteration has occurred.

The above method for detecting machine malfunctions in the multiplication unit of a digital computer with the iterative addition algorithm works well as long as this iterative addition algorithm processes only one multiplier bit per iteration. However, because ever greater operating speeds are required, multiplication algorithms with iterative addition have been developed that process several multiplier bits during each iteration. Such an algorithm is described in US Pat. No. 3,515 3 ^ 4. The multiplier shown by γοη Goldschmidt can process 6x multiplier bits per iteration, where χ = 1, 2, 3 ₉ ··· »π. The multiplier bits are decoded so that χ multiplier bits are equal to one decoded bit and the multiplicand is shifted in a series of three input carry adders according to the decoded bit. Since the ÜA needs three input signals and each input is determined by the χ multiplier bits (one decoded bit), 6x multiplier bits are processed by the ÜA in the multiplication unit for each iteration.

This type of multiplication unit can be made with the help of the above Total residual check must be checked for errors because the multiplier and multiplicand are checked before performing the multiplication operation be available. As has already been said, the overall remainder cannot check all individual errors discover. However, the sub-products can be replaced by known residual

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drive are not checked for errors related to machine drive | fall back during each iteration of the multiplication loop-! because the remainder of the decoded multiplier bits do not follow the known rules for determining the remainder.

The object of the invention is therefore to provide a circuit arrangement for the detection of faults caused by component failure) learn to specify in the multiplying unit of a digital data processing system that a multiplication by repeated Performs additions and where the multiples are determined by decoding a series of multiplier bits during each Iteration without the performance of the multiplier unit being reduced by this circuit arrangement.

This object is achieved with the aid of a circuit arrangement of the type just mentioned, which is characterized by

a) a device for predicting a residual value, which is connected to the input of the multiplication unit for generation a predicted residual value for that during the current Iteration obtained partial product based on the remainder of the multiplicand, the decoded multiplier bits for the current iteration and the predicted residual value for the previous iteration

b) a residual value generator connected to the outputs of the multiplier is connected to determine the actual residual value of the partial product generated in the current iteration and

c) a comparison device, which is connected to the device for prediction of a residual value and is connected to the residual value generator and which, if their input signals are different, enter Provides error signal.

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An embodiment of the invention is in the drawings and is described in more detail below. It shows;

1 shows a block diagram of a test device which is connected to a multiplication unit which

6 bits processed per iteration,

2 shows the multiple residual value generator in a block diagram to generate the predicted residual. worth,

3 shows the logic circuits necessary for implementing the multiple residual value generator of FIG. 2,

, Fig. 4 possible combinations of the decoded multiplier bits and the corresponding shifts and / or sign changes of the MuItχι plikanden (MD), which in the multiplication device ! to which the test device is connected. closed is, ·

j Fig. 5 the determination of the multiple residual value by the Tester according to the multiplicative

multiplicand shifts carried out by the device.

The embodiment of the invention will be described in conjunction with a multiplication unit, which is constructed substantially similar to the multiplication unit is described> in the U.S. Pat. No. 3,515,344. 1 shows in a: Block diagram the residual value prediction unit 200, the real residual value generator 400 and the residual value comparator 300 in connection with the multiplication unit 100. For the sake of simplicity, the multiplication unit 100 is shown in its simplest form, where six bits of the multiplier during each

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iteration can be processed by the adder. An exact description of the operation of the multiplication unit 100 is found in the aforementioned US patent, as there is only one Job description is given.

The multiplication unit 100 in Fig. 1 includes an operand input device 20, a transfer adder 21, an adding loop 22 for carries and an adder, not shown, working in parallel for continuous carries. The operand input device 20 includes a multiplicand source 30 and a multiplier source 31, a multiplier selection unit 31A, an iteration counter 31B, a multiplier-decoder 32 and multiplicand gates .24. The multiplicand gate circuits 24 consist of several gate circuits, whereby several binary bit operands through the elements to the input of the Carry adder circuit 21 can be transferred. With the multiplier selection unit 31A, the multiplier bits is sampled and the multiplier-decoder 32 energized during each iteration. The iteration counter 3IB energizes the multiplier selection unit 31A after the system clocking for initiation the sampling of the in the multiplier source 31 by the Multiplier selection unit 31A stored multiplier bits. With each iteration, seven bits of the multiplier are examined and used to energize the multiplier-decoder 32. In the first iteration, the multiplier selection unit 31A the first seven bits of the multiplier to the decoder 32 of the multiplier source 31 transmitted. From then on, the multiplier selection unit is in charge 31A subsequent groups of seven multiplier bits to decoder 32 overlapping so that only six new Bit3 are brought into the decoder 32. At each iteration of the multiplication operation, the multiplier-decoder generates 32 signals through which the multiplicand (MD) from the multiplicand source 30 is fed to the gate circuits 24 and by one the corresponding amount is postponed and / or made negative,

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! to reflect the multiple of the MD passed by those

iMultiplier bits have been prescribed which are used to generate the Examined multiples of the MD at the input of the carry adder , which are designated in Fig. 1 with Ml to M3. As in (the previously mentioned known multiplying unit, the multiples

j times Ml to M3 some sign extension bits due to a (Characteristics of the adding loop included. Two prefix extension bits are in the embodiment described here needed. The group of signal lines labeled Ml to M3 is a multiple of the MD, represented as operand input signals, for the carry adder circuit 21 to generate a final output that is the product of the MD and the examined multiplier bits. The multiplier bits are through the multiplier-decoder 32 in overlapping groups of three Bits are examined to determine the correct shift amount and sign of the MD, which is to be applied by the gates 24 are direct. In this way it becomes the high value multiplier bit each iteration the lower value bit for the following iteration and six bits of the multiplier are retired during each operation. A summary of the decoding technique of the multiplication unit is given in Table 1 of FIG.

The remainder prediction unit 200 of the error checking device of the present invention operates in conjunction with the input device 20 of the multiplication unit, as shown in FIG. 1, and generates a "remainder prediction for the partial product generated during each iteration by the multiplication unit 100 200 contains a multifunctional residual value generator 210, the input of which is connected to the multiplicand source 30, a generator 2 ^ 0 for the residual value multiple, which receives input signals from the multiplicand residual value generator 210 and the multiplier-decoder 32, a residual value accumulator 220 for partial products , which has a feedback connection and is connected to the inputs of the generator 2 ¹ JO for the fceat value multiple and the buffer 230 and an input

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! signal receives the residual value multiple from the accumulator.

The remainder, e.g. modulo 3 of the MD, uses conventional residual value technology to generate the remainder via the multiplicand residual value generator 210. The present Invention, of course, works just as well with any other modulo system, Modulo 3 was only used to describe the exemplary embodiment; Ies chosen.

2 shows the generator for residual value multiples in a more precise block diagram. It receives input signals in its puncture from the multiplicand remainder generator 210 and the multiplicator decoder 32 and generates a predicted residual value for the multiples Ml to M3 based on the received input signals. The residual value generator 240 for the partial products contains a residual value adjustment circuit 250 and a generator 260 for residual value multiples. The residual value adjustment circuit Its task is to correct the remainder for a negative MD so that the system only works with positive remainders. During operation with modulo 3 remainders, 3 can of course be added to each remainder, without changing the result, since the addition of 3 to a remainder is equal to the addition of a zero. A negative one The remainder can therefore be converted into its positive equivalent modulo 3 by adding a 3. Da negative numbers in the form of two's complement are shown in the multiplication unit, only the remainder of the negative MD needs to be corrected by 2, to get the positive equivalent modulo 3. The residual value adjustment 250 therefore logically corrects the remainder of the negative MD after the multiplicand remainder columns in Table 2 of FIG. 5.

[With further reference to FIG. 2 and Table 2 in FIG. 5, it is shown that the residual value multiple generator 260 corrected the MD residual value from residual value adjustment circuit 250 over the input lines 261 and the decoding information for the ! Multiples Ml to M3 from the multiplier decoder 32 via the ! Input lines 262 receives. The generator for residual value

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fold 260 combines the corrected MD residual value and the decoding information with regard to the multiples for determining the residual value of the multiples M1 to M3 according to Table 2 in FIG. 5 ^;

Fig. 3 shows a detailed implementation of the residual value generator : 24O for the partial products. While the embodiment with AND gates and OR gates is shown, these functions can of course also in another form, such as by NOR gates can be realized without departing from the scope of the invention.

As can be seen from FIG. 1, the input lines include the residual value generator 240 for the partial products three set lines emanating from the multiplier-decoder 32, one set each for the multiples M1 to M3. Similarly, generator 240 includes three sets of lines from residual value adjustment circuit 250 and residual value multiple generator 260. The generated residual values, R _M1 to R _MM -z for the multiples Ml to M3 are forwarded to the accumulator 220. The remainder accumulator 220 adds the remainder modulo 3 from R _M1 to R _M ~ to the predicted remainder of the previous iteration to determine the predicted remainder for the current iteration. This predicted residual value is then delayed in the buffer 230 until the conclusion of the current iteration in the multiplication unit and for the generation of the residual value of the current partial product.

! Simultaneously with the generation of the predicted residual value , the remainder prediction unit 200 performs the multiplication

unit 100 the current iteration to get the current partial product to determine. The carry addition circuit 21, consisting from the carry adder 40 (ÜA-A) receives at its input Groups of signal lines which represent all bits of the multiples Ml to M3 which pass through the multiplicand gate circuits 24 to have. The output of the carry adder consists of two sets of signal lines, the sum and the carry represent the multiples Ml and M3; The number of carry-over additions rer in the carry adder circuit is determined by the number

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the multiplier bits to withdraw during each iteration. ^! In the exemplary embodiment of the multiplication unit shown here _: six multiplier bits are withdrawn during each iteration and since two multiplier bits are decoded into one bit, a carry-over adder circuit with three inputs is required

retract six bits. The number of Prob's needed in the Übertragsaddierschaltung can \ be represented with N-2 where N is the number of inputs for Übertragsaddierschal-! tion is.

The adding loop 22 comprises a first and second stage of ÜA's, the first stage of the adding loop being formed by the carry adder 50 with the designation ÜA-B. The second or final stage of the adding loop 22 is formed by the carry adder 52 with the designation ÜA-C. The adder loop 22 receives successive outputs from the carry adder circuit 21 simultaneously while two sets of output signal lines are generated by the ÜA-C. In addition to the output values of the carry adder circuit 21, the adder loop 22 also receives the feedback signal from the carry output of the ÜA-C and a so-called HOT ONE for the multiple Ml at the input of the ÜA-B. The function of the HOT ONE is to convert a negative MD into two's complement form, as is used for the decoding scheme according to Table 1 in FIG. As soon as the decoded multiplicand bits are 100, 101 or 110, the negative MD in the ÜA-A 40 of the carry adder 21 must be shifted by the multiplicand gate circuits 24. Subtraction by converting the subtrahend to its two's complement and addition of numbers is a well known technique as the conversion to the two's where you first converts to the one's complement, ie the environmental

reversing the bits, and then a one to the lowest digit added to the number. With this technique, the MD is in the nega-! tiven MD converted as soon as the multiplier-decoder 32 the Shifting the negative MD required in the carry adder 21 and the HOT ONE is the binary ones bit which is used for the

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! lowest digit must be added to convert it to the two-part!

to convert 'mentform. The HOT ONE is a binary zero bit, so- '

soon the decoder 32 causes a positive MD or zero i to be shifted into the carry adder 21. The sum of the Addierschleife 22 is the input of the ÜA-C coupled to the second stage back \. Because the output signals of the ÜA-C generated at the same time

j to which the ÜA-B receives its input signals must be in the jSum feedback loop provided some delay J to compensate for the forwarding time by the ÜA-B so that that the ÜA-C the output signals from the ÜA-B and the feedback sum receives at the same time. The buffer 51 has to provide the necessary delay. The ÜA-C also receives at its entrance the HOT ONE for the multiple of M2.

The output signals generated by the ÜA-C are the sum and the transfer for one iteration by the multiplication unit. Since six bits of the multiplier are withdrawn at each iteration, the output values of the ÜA-C must be shifted six bits towards the lower values at the end of each operation in order to accommodate the next six bits of the multiplier sampled by the multiplier selection unit 31A. It was previously said that seven bits of the multiplier are selected in the first iteration and seven bits in the subsequent iterations by an overlap technique. The seventh or most significant bit of each iteration is re-selected as the least significant bit for the subsequent iteration because the decoder examines the bits in overlapping three-bit groups. (Seven bits are required to form three overlapping groups of j three bits each, e.g. 101 $ 100. The numbers 011100 are withdrawn during the iteration and 1 is the lower bit for the next iteration. Accordingly, six bits of the I output signals become the Carry adding loop, shifted to the right at the end of each iteration and applied to the adder for carry bits 71, which has to calculate the sum of the applied bits and pass a carry on through each subsequent series of carry bits to determine whether through the end group of carry bits that is passed to the adder for carry bits jl ^ WA 972 010. ~

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was, at the end of the last iteration by the adding loop 22 a carry is generated. The bits added in the adder 71 form the lower-order bits of the product of the multiplication operation and are stored in the carry sum register ¹ JIk after each iteration as long as the last iteration through the adding loop 22 is still outstanding. The HOT ONE for the multiple M3 is added into adder 71 as well. The OR circuits 90 and the OR circuits 91 pass the sums and carries from the ÜA-C to the remainder generator 400 after each iteration and lead the output values of the adding loop together with the carry from the adder 71 after the last iteration to the adder for continuous carries Production of the valuable part of the end product. The content of the carry-over sum register 7IA is then passed into the lower-value part of the product register via the OR gates 90.

The residual value generator 400 generates together with the output signals the adder loop 22 and the output signals of the adder for carry bits 71, the remainder of the partial product during each iteration. A carryover sum generator 410 is connected to the sum output of the adder for carry bits 71 and generates the remainder of the 6 sum bits and the 6 carry bits from the ÜA-C, which are accumulated in the adder 71 during each iteration and a residual value generator 430 for the sum and carry of the ÜA-A is connected to the OR gates 90 and 91 so that the Residual value of the output value of the ÜA-C of each iteration is generated. The sign extension bits at the ÜA-C output must also the generator 43O are fed. The residual value generators for the carry sum and the ÜA-C output signals are conventional Generators as already described. The output of the generator 410 is connected to the accumulator 420 where the initial values for the previous residual value of the carry-over sum is added. The residual values of the carryover sums must be collected as the carry sums are with each other and then after the last iteration with the result of the adder for continuous Carries are chained. The final link in the residual value generator 400

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is the remainder adder 440. The remainder adder 440 receives at its input the output signals of the accumulator 420, which represent the accumulated remainder of the carry sums during the previous iteration, of the remainder generator 430 for sum and carry of the ÜA-A, which represent the remainder of the current iteration and the carry signals of carry adder J71 for the previous iteration. In the first iteration JPress from gangs are signals from the accumulator by the adder 42.0 and Jl zero, j JThe Restwertaddierer these inputs combined plus ^"U 2 to generate the residual value. The" 2 "is $ m adder 440 to

to compensate for any peculiarities of the ÜA initialization one of the outputs is always negative. The "2" is, as said above, added to the negative remainder into a positive one j to convert residual value.

I "

jThe output signals of the residual value prediction unit 200 and des Residual value generator 400 are received by the residual value comparator 300, in which the residual value comparator 310 receives the two signals compares for digital equivalence and generates an error signal, " jif the result of the comparison is not equal. That generated Pelersignal can be used to indicate that during an error occurred during the multiplication operation.

During normal operation, the multiplicand and the multiplier, the product of which is to be determined, are stored in the multiplicand source 30 and the multiplier source 31 of the multiplication unit 100 is loaded. If either is negative, it will be in two's complement form shown. The first iteration is initiated by the iteration counter 3IE and the multiplier selection unit 3IA asks the first 7 bit positions of the multiplier source : 30 and transfers the bits to the multiplier-decoder 32. The multiplier-decoder 32 decodes the multiplier bits, which are kept therein in overlapping groups of three bits, -jund directs the multiplicand into the multiplicand gate circuits 24 in order to determine the multiples M1 to M3

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That means if the first 7 bits of the multiplier are iOlllQO then the multiples Ml to M3 are determined as follows:

M 2

1011100
M3 Ml

In Pig. 4 is the negative MD directly in the ÜA-A 40 for Ml = 100 of the carry adder 21 to load. The inversion (one's complement) of the multiplicand is therefore passed through the Ml position of the gate circuits 24. For M2 = 111, the ÜA-A 40 closes zero load. A zero is correspondingly 'through the M2 position of the Gate circuits 24 directed. For M3 = 101, a negative MD is in to load the ÜA-A 40 shifted by one bit position to the right and accordingly the reversal of the MD is through.die position M3 of the gate circuits 24 shifted to the right by one bit position. The starting bit position of the multiple M2 is at the input of the ÜA-A by two positions to the left of the starting bit position of the multiple Ml. The starting bit position of the Multiples M3 two bit positions to the left of the starting bit position of the multiple M2.

The multiplicand remainder generator 210 shown in FIG. 1 determines the remainder and the sign of the multiplicand source 30. These are then sent to the inputs of the generator for residual value multiples 240 together with the decoding information from the multiplier-decoder 32 received. The residual value of the multiplicand is passed through circuit 250 for residual value adjustment of the generator 240 for residual value multiples in FIG. 3 on the input lines 251 is received and the sign of the .MD is received on input lines 252. The residual value adjustment circuit 250 corrects the residual value of the MD so that it always appears positive. If, for example, a residual value MD = 2 is assumed, then the residual value adjustment circuit is combined 250 the input signals of the negative MD and the MD residual value equal to 2 and generates a positive one Remainder of 1, which is equivalent to adding 2 modulo 3 to the remainder

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! value of a negative number in two's complement form.

The decoding information from multiplier-decoder 32 is received on input lines 262 of residual multiple generator 260 which is part of residual quadruple generator 240. The residual value generator 260 combines the output ides decoder with the corrected MD residual value for determining the residual value of the multiple Ml to M3 · In ^r the above examples,! Where the Decodiererbits for Ml = IOO (charging MD directly in ÜA-A) and the corrected MD remainder were equal to 1, the remainder of Ml = 2. Similarly, Table 2 of FIG. 5 shows a remainder of 2 for an operand where the remainder of the negative MD = 2 and the output signal from require the loading of -MD directly into the ÜA-A. The remainders of M2 and M3 are similarly determined by the remainder multiple generator 240.

The residual value accumulator for partial products 220 receives the kest values for the multiples Ml to M3 at its entrance and combi. nees this with the predicted residual value for the previous one Iteration to get the predicted residual for the current iteration to determine. For the first iteration, the one predicted earlier is? Residual value zero. When the accumulator 220 shifts its output into the buffer 230, it becomes the output thereafter also fed back to the accumulator 220, where it. is added to the three residual value multiples for the next iteration.

Simultaneously with the generation of the predicted residual value, the multiplication unit 100 generates the partial product for the current iteration. Correspondingly, the content of the gate postures 24 representing the multiples Ml to M3 is shifted into the ÜA-A'40 as determined above. The üA-40 adds Ml to M3 together gap. Generation of a sum and a carryover at its output. The ÜA 50 receives at its input the output signals of the ÜÄ HO ₉ ! The fed back transmission of the ÜA 52 and a HOT ONE for Ml. In the above example, Ml was negative and was loaded into the ÜA 40 as one's complement, so the HOT ONE for Mi is a bΙ972 010

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Nary one that is loaded into the rightmost transfer part of the ÜA 50. The fed back input signal for the ÜA 50 for ' the first iteration is zero. At its output, the ÜA 50 generates: a sum and a transfer, which is the sum of the sum and the transfer from the ÜA 40 and the fed back transfer from the ÜA 52 | represents. The output signals of the ÜA 50 are the input signals for the ÜA 52 together with the sum output signal of the ÜA 52, which was delayed in the buffer 51, and the HOT ONE for the multiple M2, which is zero in the above example. The ÜA 52 adds its input signals to generate a sum and a carry · The output signals of the ÜA 52 are shifted 6 bits to the right and put in the adder for carry bits 71 to make room for the six multiplier bits to be taken into account in the next iteration are.

Simultaneously with the shifting of the six sum and the six carry bits as output signals of the ÜA 52 in the adder 71 the residual value generator 400 is actuated to determine the residual value of the partial product that is generated at the output of the ÜA 52. The OR gates 90 and 91 are operated to set the unshifted output bits of the ÜA 52 including the sign extension bits into the residual value generator 430 for total and carry forward of the ÜA-A. The residual value generator 430 generates the residual value of the sum and the carryover from the ÜA 52 and forwards this residual value to the residual value adder 440. The remainder adder 440 receives at its input the output signals from residual value generator 430, the carry output signals from adder 71 for carry bits and the output signals from accumulator 420 for the residual value the transfer amount and added to these inputs plus "2" to generate the residual value for the current partial product. As previously said, the "2" compensates for the ÜA initialization. The output signals of the accumulator for the residual value of the transfer amount, which are passed on to the remainder adder represent the output signals of the previous iteration, da the output signals of the residual value generator 43Ο from the not

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j shifted output signals of the ÜA-C 52 are generated. In the first. Iteration, these two output signals are therefore zero.

The residual value comparator 310 receives the output at its input | Output signals of the remainder adder 440 and buffer 230 showing the actual and predicted remainders for the current Represent iteration. The residual value comparator 310 compares its inputs digitally to determine if there is a mechanical error caused an error in the multiplication unit during the relevant iteration. If an error has occurred, the comparison results are different and an error signal is generated generated.

Simultaneously with the forwarding of the output signals of the ÜA-52 of the residual value generator 430 for the sum and transfer of the ÜA-Ä OR gates 90 and 91 become six sum bits and six carry bits of the partial product shifted from the ÜA 52 into the adder 71. The adder 71 receives these bits together at its inputs with its own fed back carry bit and the HOT ONE for M3 and adds them to generate a sum and carry output. The sum output of the adder 71 is shifted to the sum register 71A, where it is matched with the Sums from previous iterations are concatenated. The Summenaus output signal of the adder 71 is also generated by the generator 410 is queried, which determines the remainder of the sum. The output of generator 410 is passed to accumulator 420 where it to the accumulated residual value of the carryforward sums for previous ones Iterations is added. The output of the accumulator 420 is passed into the remainder adder 440 where it is added to the partial product remainder for the next iteration. The carry output of the adder 71 is fed directly into the remainder adder 440, since it is only a one-bit signal, and is also added to the partial product remainder for the next iteration ..

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After the last iteration through the adding loop 22 the output signals of the ÜA 52 through the OR gates 90 and 91 to the adder for continuous transfers together with the HEIS-SEN ONE for the multiple M3 for the last iteration and the carry of the adder 71. These input values are combined to the most valuable numbers of the end product. The output signals of the sum register 7IA are then via the OR gates 90 to form the lowest value numbers of the end product passed into the adder for continuous carries.

In the description above, an error checking circuit has been shown, which is designed to detect when a machine failure occurs during each iteration, led by one with iterative Addition working multiplication unit when performing a multiplication is performed in which two bits of the multiplier can be decoded to a decoded bit to get the correct shifts and the sign of the multiplicand in an adder for the carry sum with three inputs. The test circuit performs its task in parallel with the actual multiplication operation without affecting the efficiency the multiplication unit is thereby reduced.

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Claims (1)

- I ₉ - PATENT CLAIMS Circuit arrangement for the detection of errors caused by component failure in the multiplying unit of a digital one Data processing system that performs a multiplication by repeated addition and in which the multiples are determined by decoding a series of multiplier bits during each iteration by a) a device (200 Fig. 1) for predicting a residual value, which is connected to the multiplicand input of the multiplication unit is connected to generate a predicted residual for that during the current iteration partial product obtained on the basis of the residual value the multiplicand, the decoded multiplier bits for the current iteration and the predicted remainder for the previous iteration ₉ b) a residual value generator (40O) ₉ which is connected to the outputs of the multiplication unit to determine the partial product land generated in the current iteration c) a comparison device (300) / attached to the device for predicting a residual value and is connected to the advisory value generator and when their inequality Input signals provides an error signal. Circuit arrangement according to Claim 1, characterized in that the device for predicting a residual value a first device (210) for determining the residual value of the multiplicand and a second device (240) connected to the first for determining the residual values of the running multiples for the multiplying unit and one Accumulator (220) connected to the second device to combine the current residual values with the previous WA 972 010 509832/0710 - Contains 20 predicted residual values. 3. Circuit arrangement according to claim 2, characterized in that the second device (240) for determining the Contains residual value a) a device (250 $ Fig. 2) for correcting the remainder of the multiplicand into a positive remainder and b) a device (260) connected to the device for correcting the residual value of the multiplicand for generating the residual values of the running multiples for the multiplication unit based on the corrected multiplicand residual value and the decoded multiplier bits for the current iteration. . Circuit arrangement according to Claim 2, characterized in that that the device for predicting the residual value one to the accumulator and to the comparison device attached buffer (230) contains to delay the predicted current residual value until the actual current residual value is generated. WA 972 010 SG9832 / G716