DE2460379C2 - Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element - Google Patents

Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element

Info

Publication number
DE2460379C2
DE2460379C2 DE2460379A DE2460379A DE2460379C2 DE 2460379 C2 DE2460379 C2 DE 2460379C2 DE 2460379 A DE2460379 A DE 2460379A DE 2460379 A DE2460379 A DE 2460379A DE 2460379 C2 DE2460379 C2 DE 2460379C2
Authority
DE
Germany
Prior art keywords
pin diode
plastic
connection
encapsulated semiconductor
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2460379A
Other languages
German (de)
Other versions
DE2460379B1 (en
Inventor
Erich 7808 Waldkirch Schindler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE2460379A priority Critical patent/DE2460379C2/en
Priority to IT30272/75A priority patent/IT1050400B/en
Priority to GB51826/75A priority patent/GB1524860A/en
Priority to FR7538985A priority patent/FR2303380A1/en
Publication of DE2460379B1 publication Critical patent/DE2460379B1/en
Application granted granted Critical
Publication of DE2460379C2 publication Critical patent/DE2460379C2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1515th

alle Anschiußflächen (21, 22, 23, 24) sind zum Zentrum der Verkapselung (P) hin 90°-keilförmig ausgebildet,all connection surfaces (21, 22, 23, 24) are 90 ° wedge-shaped towards the center of the encapsulation (P),

auf zwei in der einen Achse liegenden Anschiußflächen (21, 22) sind ein erster (1) und ein zweiter (2) pin-Dioden-Halbleiterkörper und auf einer in der anderen Achse liegenden Anschlußfläche (23) ein dritter pin-Dioden-Halbleiterkörper (3) im Gebiet der jeweiligen Keilspitzen mit ihren Anoden elektrisch leitend befestigt, undon two connection surfaces (21, 22) lying in one axis are a first (1) and a second (2) pin diode semiconductor body and on one lying in the other axis Terminal surface (23) a third pin diode semiconductor body (3) in the area of the respective Wedge tips attached to their anodes in an electrically conductive manner, and

die Kathoden der drei pin-Dioden-Halbleiterkörper sind derart über Verbindungsleitungen (41,42,43) an den Anschlußflächen angeschlos- so sen, daß der erste pin-Dioden-Halbleiterkörper (1) mit der Anschlußfläche (23) des dritten (3) und der zweite (2) und der dritte (3) pin-Dioden-Halbleiterkörper mit der pin-diodenlosen Anschlußfläche (24) verbunden sind.the cathodes of the three pin diode semiconductor bodies are connected via connecting lines (41,42,43) connected to the connection surfaces sen that the first pin diode semiconductor body (1) with the connection surface (23) of the third (3) and the second (2) and the third (3) pin diode semiconductor body with the pin-diodeless Connection surface (24) are connected.

5050

Aus dem DE-GM 19 78 285 ist ein plastikverkapselter ίο Planartransistor entsprechend dem Oberbegriff des Patentanspruchs bekannt.From DE-GM 19 78 285 is a plastic-encapsulated ίο Planar transistor according to the preamble of the claim is known.

Hierbei ist eine der vier Zuleitungen so ausgebildet, daß sie im Bereich der Anschiußflächen zwischen den drei anderen Zuleitungen verläuft und so die drei anderen Zuleitungen gegeneinander abschirmt.Here, one of the four supply lines is designed so that it is in the area of the connection surfaces between the three other leads and thus shields the three other leads from each other.

Obwohl sich die bekannte Zuleitungsanordnung bei dem bekannten Planartransistor bewährt hat, zeigt es sich bei der beabsichtigten Anwendung dieser Plastikverkapselung bei pin-Dioden-TT-Gliedern, daß die Zuleitungsanordnung nicht optimal ist.Although the known lead arrangement has proven itself in the known planar transistor, it shows in the intended application of this plastic encapsulation for pin diode TT elements that the Feed line arrangement is not optimal.

Die Aufgabe der Erfindung besteht daher darin, die vom erwähnten Planartransistor her bekannte Zuleitungsanordnung für die Anwendung bei pin-Dioden-jr-Gliedern abzuwandeln und die Kapazität der Längsdiode des pin-Dioden-rc-Gliedes auf etwa die Hälfte zu reduzieren und dessen Dämpfung auf etwa das Doppelte gegenüber den entsprechenden Werten bei seiner Realisierung aus Einzel-pin-Dioden anzuheben. Dabei soll die Abschiriiiwirkung der Zuleitungen im Inneren der Verkapselung aufrechterhalten bleiben.The object of the invention is therefore to provide the feed line arrangement known from the planar transistor mentioned for use in pin diodes-jr-members and to modify the capacitance of the series diode of the pin diode rc element to about half and its attenuation to about that Twice as much as compared to the corresponding values in its implementation from single-pin diodes. The shielding effect of the supply lines should be Maintain inside the encapsulation.

Diese Aufgabe wird von der im Anspruch angegebenen Erfindung gelöst, die nun in Zusammenhang mit der Darstellung eines Ausführungsbeispiels an Hand der Figuren der Zeichnung näher erläutert wird.This object is achieved by the invention specified in the claim, which is now in connection with the Representation of an embodiment is explained in more detail with reference to the figures of the drawing.

F i g. 1 zeigt im Schnitt den Grundriß eines Ausführungsbeispiels der Erfindung, undF i g. Fig. 1 shows in section the plan view of an embodiment of the invention, and

F i g. 2 zeigt das elektrische Schaltbild der AnordnungF i g. 2 shows the electrical circuit diagram of the arrangement

6565

nach F ig.according to Fig.

In F i g. 1 ist durch die kreisförmige Fläche P die Plastikverkapselung des pin-Dioden-jr-Glieds angedeutet. Die vier Anschlußleitungen rechteckförmigen Querschnitts sind kreuzförmig angeordnet, d. h. je zwei der Zuleitungen haben eine gemeinsame Achse. Dies trifft einerseits für die Anschlußleitungen 11, 12 und andererseits für die Anschlußleitungen 13,14 zu.In Fig. 1, the plastic encapsulation of the pin diode jr element is indicated by the circular area P. The four connecting lines of rectangular cross-section are arranged in a cross shape, that is, every two of the supply lines have a common axis. This applies, on the one hand, to the connecting lines 11, 12 and, on the other hand, to the connecting lines 13, 14.

Zum Zentrum der Verkapselung hin weisen die vier Anschlußleitungen keilförmig zugespitzte Anschlußflächen 21, 22, 23, 24 auf. Der Innenwinkel der keilförmigen Spitze beträgt 90°, so daß die Begrenzungslinien benachbarter Anschlußflächen parallel zueinander und engbenachbart verlaufen.Towards the center of the encapsulation, the four connection lines have wedge-shaped tapered connection surfaces 21, 22, 23, 24 on. The interior angle of the wedge-shaped tip is 90 °, so that the boundary lines adjacent pads run parallel to one another and closely adjacent.

Auf den drei Anschlußflächen 21,22,23 ist jeweils der Halbleiterkörper einer pin-Diode mit ihrer Anode elektrisch leitend befestigt So gehört zur Anschlußfläche 21 der pin-Dioden-Halbleiterkörper 1, zur Anschlußfläche 22 der pin-Dioden-Halbleiterkörper 2 und zur Anschlußfläche 23 der pin-Dioden-Halbleiterkörper 3.On each of the three pads 21,22,23 is the Semiconductor body of a pin diode with its anode attached in an electrically conductive manner So belongs to the connection area 21 of the pin diode semiconductor body 1, to the connection surface 22 of the pin diode semiconductor body 2 and to the connection area 23 of the pin diode semiconductor body 3.

Die an der freien Oberfläche des jeweiligen pin-Dioden-Halbleiterkörpers liegende Kathode ist über jeweils eine Verbindungsleitung mit einer der anderen Anschiußflächen derart verbunden, daß die Kathode der pin-Diode 1 über die Verbindungsleitung 41 an der Ansch'.ußfläche 23, die Kathode der pin-Diode 2 über die Verbindungsleitung 42 an der Anschlußfläche 24 und die Kathode der pin-Diode 3 über die Verbindungsleitung 43 ebenfalls an der Anschlußfläche 24 liegt.The cathode lying on the free surface of the respective pin diode semiconductor body is Connected via a connecting line to one of the other connection surfaces in such a way that the Cathode of the pin diode 1 via the connecting line 41 on the connection surface 23, the cathode of the pin diode 2 via the connecting line 42 on the pad 24 and the cathode of the pin diode 3 via the Connecting line 43 also lies on the connection surface 24.

In F i g. 2 ist das elektrische Schaltbild der Halbleiteranordnung nach Fig. 1 gezeigt. Es stellt ein aus drei pin-Dioden gebildetes π-Glied dar, das in den beiden Querzweigen die pin-Dioden Dl, D2 und im Längszweig die pin-Diode D3 aufweist. Wird bei der Anordnung nach Fig. 1 die Anschlußleitung 13 als Eingang El nach Fig.2 und die Anschlußleitung 14 als Ausgang A 1 nach F i g. 2 benutzt und dienen die Anschlußleitung 11 entsprechend dem Eingang E2 und die Anschlußleitung 12 entsprechend dem Ausgang A 2 als für Eingang und Ausgang des π-Gliedes gemeinsame Elektroden, so ist die bei der eingangs geschilderten bekannten Anschlußleitungsanordnung vorhandene Abschirmwirkung bei der Anordnung nach F i g. 1 ebenfalls vorhanden, obwohl die eine Zuleitung nach der bekannten Planartransistoranordnung nicht mehr vollständig zwischen den anderen Zuleitungen verläuft.In Fig. 2, the electrical circuit diagram of the semiconductor arrangement according to FIG. 1 is shown. It represents a π-element formed from three pin diodes, which has the pin diodes D1, D 2 in the two shunt branches and the pin diode D 3 in the series branch. If, in the arrangement according to FIG. 1, the connection line 13 is used as input El according to FIG. 2 and the connection line 14 as output A 1 according to FIG. 2 and the connection line 11 corresponding to the input E2 and the connection line 12 corresponding to the output A 2 serve as electrodes common to the input and output of the π-element, the shielding effect present in the known connection line arrangement described above is in the arrangement according to FIG . 1 is also present, although the one lead according to the known planar transistor arrangement no longer runs completely between the other leads.

Wie Untersuchungen gezeigt haben, würden entsprechende in einzelnen Gehäusen aufgebaute pin-Dioden eine durch den Gehäuseaufbau bedingte parasitäre Parallelkapazität von 10OfF haben, während dieser Wert bei der erfindungsgemäßen Anordnung für die Längs-pin-Diode DZ auf 4OfF reduziert ist. Ferner wurde festgestellt, daß mit dem Aufbau eines jr-GIiedes entsprechend Fi g. 2 aus cinzelverkapselten pin-Dioden die Dämpfung des jr-Gliedes bei einer Frequenz von 800 MHz nur kleiner als 28 db wäre, während bei einem pin-Dioden-jr-Glied entsprechend der erfindungsgemäßen Halbleiteranordnung die Dämpfung bei 800MHz größer als 45 db ist.As studies have shown, corresponding pin diodes built in individual housings would have a parasitic parallel capacitance of 10OfF due to the housing design, while this value is reduced to 40FF in the arrangement according to the invention for the series pin diode DZ. It was also found that with the construction of a jr link according to FIG. 2 made of cinzelverkapselten pin diodes the attenuation of the jr element at a frequency of 800 MHz would only be less than 28 db, while with a pin diode jr element according to the semiconductor arrangement according to the invention the attenuation at 800 MHz is greater than 45 db.

Zu diesen überraschend guten Werten trägt insbesondere die Tatsache bei, daß die Anschlußleitungen 11,12 die Anschlußleitungen 13, 14, also Eingang und Ausgang, gegeneinander abschirmen, obwohl, wie bereits oben erwähnt, die vierte Anschlußleitung nicht mehr vollständig zwischen den anderen verläuft. Dies ist ein durchaus überraschendes Ergebnis und dürfte daraufThe fact that the connecting lines 11, 12 the connection lines 13, 14, that is, the input and output, shield from one another, although how already mentioned above, the fourth connection line no longer runs completely between the others. This is a quite surprising result and should be on it

3 43 4

zurückzuführen sein, daß mittels der erfindungsgemä- sen, daß die Anschlußleitungen zwischen ihrem im Ben keilförmig spitz zulaufenden Ausbildung aller Innern der Plastikverkapselung außen angeordneten Anschlußflächen eine besonders raumsparende und Teil und der jeweiligen Anschlußfläche eine Einschnüengbenachbarte Anordnung der einzelnen Anschlußflä- rung aufweisen, die der Verankerung der jeweiligen chen möglich wird, so daß die Verbind.jngsleitungen 5 Anschlußleitungen in der zur Herstellung der Plastiksehrkurz sein können, verkapselung verwendeten Kunststoffpreßmasse die-Der Vollständigkeit halber sei noch darauf hingewie- nen.be due to the fact that by means of the inventive that the connecting lines between their im Ben wedge-shaped tapering training all inside the plastic encapsulation arranged outside Connection surfaces a particularly space-saving and part and the respective connection surface a constriction adjacent Have the arrangement of the individual connection surfaces that anchor the respective Chen becomes possible, so that the connection lines 5 connecting lines in the very short for the production of plastic can be, plastic molding compound used encapsulation die-The For the sake of completeness, this should be pointed out.

Hierzu 1 Blatt Zeichnungen1 sheet of drawings

Claims (1)

Patentanspruch:Claim: Plastikverkapselte Halbleiteranordnung mit vier in einer Ebene liegenden, einen rechteckigen Querschnittt aufweisenden Anschlußleitungen, die in zwei senkrecht zueinander stehenden Achsen aus der Verkapselung austreten und im Inneren der Verkapselung teilweise keilförmig mit einem Innenwinkel von 90° (90°-keilförmig) ausgebildete Anschlußflächen aufweisen, wobei mindestens auf einer ein Halbleiterkörper und von diesem ausgehende Verbindungsleitungen befestigt sind, gekennzeichnet durch die Kombination der folgenden Merkmale:Plastic-encapsulated semiconductor device with four lying in one plane, one rectangular Cross-section having connecting lines in two mutually perpendicular axes exit the encapsulation and inside the encapsulation partially wedge-shaped with an interior angle of 90 ° (90 ° wedge-shaped) have formed connection surfaces, with at least one a semiconductor body and connecting lines extending therefrom are attached, characterized by combining the following features: 1010
DE2460379A 1974-12-20 1974-12-20 Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element Expired DE2460379C2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE2460379A DE2460379C2 (en) 1974-12-20 1974-12-20 Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element
IT30272/75A IT1050400B (en) 1974-12-20 1975-12-15 SEMICONDUCTIVE DEVICE WITH PLASTIC CAPSULE
GB51826/75A GB1524860A (en) 1974-12-20 1975-12-18 Plastics encapsulated semicondusctor device
FR7538985A FR2303380A1 (en) 1974-12-20 1975-12-19 SEMICONDUCTOR DEVICE IN PLASTIC CASE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2460379A DE2460379C2 (en) 1974-12-20 1974-12-20 Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element

Publications (2)

Publication Number Publication Date
DE2460379B1 DE2460379B1 (en) 1976-04-29
DE2460379C2 true DE2460379C2 (en) 1980-06-26

Family

ID=5933978

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2460379A Expired DE2460379C2 (en) 1974-12-20 1974-12-20 Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element

Country Status (4)

Country Link
DE (1) DE2460379C2 (en)
FR (1) FR2303380A1 (en)
GB (1) GB1524860A (en)
IT (1) IT1050400B (en)

Also Published As

Publication number Publication date
FR2303380A1 (en) 1976-10-01
GB1524860A (en) 1978-09-13
IT1050400B (en) 1981-03-10
DE2460379B1 (en) 1976-04-29

Similar Documents

Publication Publication Date Title
EP0116519B1 (en) Building block, in particular for building-block toys
DE2700617C3 (en) Process for the production of an electrical component with connection lugs and component produced with this process
DE2717254C3 (en) Fabric electrical circuit matrix
DE3520519A1 (en) ELECTRICAL CONNECTOR AND METHOD FOR THE PRODUCTION THEREOF
DE1914442C3 (en) Semiconductor device
DE2460379C2 (en) Plastic-encapsulated semiconductor arrangement in the form of a pin diode II element
DE1911779A1 (en) Wiring arrangement for the electrical connection of mutually different connection levels
DE1206043B (en) Block-shaped arrangement for the assembly of electrical or electrical circuit elements and process for their production
DE2520429C3 (en) Translucent cover for lights
EP0117456B1 (en) High voltage cascade
DE2900838A1 (en) Printed circuit board assembly for small quantity prodn. - comprises two parallel boards with components mounted between them with lead ends protruding
DE4037763A1 (en) Screened printed circuit module for communications appts. - has screening frame on each side of printed circuit board formed by sheet metal strips
CH532526A (en) Yarn monitor - using transducers from integrated circuit systems
EP0038578B1 (en) Pluggable module for high frequency devices
DE2608522A1 (en) CIRCUIT BOARD FOR ELECTRONIC CIRCUITS
DE3303165A1 (en) SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION
DE1905656C3 (en) Rectifier bridge
DE876555C (en) Ribbon cable
DE2921205C2 (en) Electronic device
AT320054B (en) Electrical assembly with a housing
DE385757C (en) Resistance set for all integer resistance levels from 0 to 9 resistance units
DE1613988A1 (en) Electric device
DE1079704B (en) Adjustable termination circuit for coaxial lines
DE8709795U1 (en) Board for printed transistor circuits, especially for laboratory purposes
DE1032400B (en) Ceramic multiple decoupling capacitor for electron tubes

Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee