DE2438218C2 - Electronic security system with a false signal blocking circuit - Google Patents

Description

The invention relates to an electronic security system with an interference signal blocking circuit according to the preamble of claim 1.

Such an electronic security system is known from DE-OS 22 63 905. There is a connection with one embodiment described a safety system which has a reset device, which takes effect when the preselected number of received pulses is within the preselected Integration time 73 of the integrator is counted and an alarm has been triggered or if within the Integration time 73 the preselected number of pulses could not be counted. A setback ensues thus only at the end of the integration time 73, within which a preselected number of wobble periods lies. Thus, this known security system is after activation for a predetermined time, namely the integration time 73, focused on this activation and then remains activated for this time, if a fault occurs due to the failure of a pulse. In this case, one of the disturbed impulse chains can occur time-delayed, but occurring within the time of this activation, by a to be registered The pulse waves generated by the resonance marking circuit are not registered. It must therefore with the Design of this known safety system found a compromise for a suitable integration time that are long enough on the one hand for the required accuracy of the safety system and on the other hand for a not too long dead time of the interference signal blocking circuit, b'io the security system a new one Signal processing can begin, should be short enough.

The invention is based on the object of an electronic security system according to the preamble of claim 1 defined genus in such a way that their dead time after failure at least of an impulse in the impulse chain just registered is reduced to a minimum

This object is achieved by the features characterized in claim 1.

A major advantage of the security system ^{according to the invention is that C:} e dead line of the interference signal blocking circuit, i.e. the time that elapses after the failure of a pulse until the security system can start a new signal processing, is independent of the integration time preselected for the integrator. The integration time can thus be selected solely as a function of the preselected accuracy of the safety system, while the dead time of the interference signal blocking circuit is limited to the time of the period. within which the absence of a pulse is detected. The security system according to the invention can thus be reactivated immediately after the absence of a pulse has been detected, for example if a resonance marking circuit to be registered is located in the monitored zone or is introduced into it during this time.

Advantageous refinements of the invention are characterized in the subclaims, with every detail given circuit examples for the configurations of the following description of the preferred Embodiments / u can be found.

The invention is described below with reference to the preferred embodiments shown in the drawing explained; in this shows

1 is a block diagram of an electronic security system;

Fig. 2 is a block diagram of an interfering signal blocker * circuit;

3 shows a block diagram of the non-retriggerable

monostable multivibrators in FIG. 2;

F i g. 4 is a block diagram of the retriggerable monostable Multivibrators in FIG. 2;

F i g. 5 is a schematic representation of the integrator and the threshold detector in FIG. 2; and

F i g. 6 is a graphical representation of signals generated during operation of the interference signal blocking circuit shown in FIG be used.

1 includes an electronic security system a transmitter iO, which is connected to an antenna 12, usually a loop antenna This creates an electromagnetic field within a predetermined zone that will be monitored is generated. A receiving antenna 14, which is also a loop antenna, takes that from antenna 12 radiated energy and is arranged to monitor a resonance marking circuit 15 in the Can fix the area, the absorbed energy being fed to the input of an RF receiver which comprises an RF bandpass filter 16 and an RF amplifier 18 The output of the RF amplifier 18 is fed to a detector 20, the output of which is fed to a signal processing circuit 22 £ U The signal processing circuit 22 may include analog noise limiting circuits such as Filters to limit the band of signals received that are subsequently processed should. The output signals of the signal processing circuit 22 are taken from a noise blocking circuit 24 processed, which is described in detail below. According to the block diagram 2, the Störsignalblockierschaltung a non-retriggerable monostable multivibrator 28, which the pulses from the signal processing circuit 22 and receives a retriggerable monostable multivibrator 30 triggers The output of the multivibrator 30 is integrated by an integrator 32, and this integrated The output signal is fed to a threshold detector 34. When the threshold of the threshold detector 34 is exceeded by the output signal of the integrator 32, the threshold detector 34 inputs Output signal to an alarm device 26 for its actuation. A staircase generator and comparator 36 can additionally be used, which receives pulses from the signal processing circuit 22 and a Reset signal generated for the integrator 32 when a high-frequency interference signal occurs, as will be described below will.

According to FIG. 3, the non-retriggerable multivibrator 28 comprises a flip-flop circuit 40 which is switched into one of its operating states by a signal from the signal processing circuit 22. The flip-flop circuit 40 also receives a reset signal from a threshold detector 42 which is actuated by an input signal which is derived in front of a βC integration circuit comprising in series a resistor R 1 and a capacitor CX connected between a voltage source + V and a reference potential is switched, the reference voltage usually being ground. A switch 51 is connected in parallel to the capacitor C1 and responds to the output signal of the flip-flop switchgear ^ O in order to short-circuit the capacitor C1.

When the switch 51 is open, the capacitor Ci is charged by the voltage + V. If the Kofidensators voltage exceeds the predetermined threshold voltage of the threshold detector 42, a reset signal is fed to the flip-iFlop circuit 40. When the switch S ¹ 1 is closed, the capacitor Cl is discharged and the threshold voltage of the threshold detector 42 is prevented from rising and there is no reset signal the flip-flop circuit 40 is supplied

When the flip-flop circuit 40 receives a trigger pulse from the signal processing circuit 22, it is set to a first level, usually a high level, and this provides a first level output signal, usually a high level signal, to the multivibrator 30 submitted. This output signal also opens the switch S1 so that the capacitor Ci can be charged. When the voltage on capacitor Ci reaches a predetermined threshold, threshold detector 42 is triggered to generate a reset signal for flip-flop 40, which in turn generates an output signal of a second level, usually an output signal of a lower level that the switch S1 is closed. The switch 51 is usually a solid-state switch, such as, for example, a transistor, the grid electrode of which is connected to the output of the flip-flop circuit 40.

The flip-flop circuit 40 can only by alternating Pulses can be triggered which are fed to the input and reset terminals not until the completion of the AC integration circuit with respect to the threshold voltage of the threshold detector 42 is retriggered certain cycle will. The pulses received by the signal processing circuit 22 of the flip-flop circuit 40 during the Charging cycle of the capacitor C1 are supplied, the state of the flip-flop circuit 40 can not influence and are excluded from the subsequent processing.

The retriggerable monostable multivibrator 30 is shown in FIG. 4 and generally constructed similarly to the non-retriggerable multivibrator 28 νι · η F i g. 3. A flip-flop circuit 50 receives a brief setting signal from the multivibrator 28, which is in particular the leading edge of the received pulse, and this signal also forms an input signal to a switch 51, this signal going through an OR circuit 52. The flip-flop circuit 50 receives a reset signal from a threshold detector 54, which is actuated by an AC integration circuit, which has a resistor R 2 and a capacitor C 2 at rest, which is between a voltage source + V and a reference voltage, usually Ground is connected. The switch 52 is connected in parallel to the capacitor C 2, and when this switch is closed, the capacitor is short-circuited. The output signal of the flip-flop circuit 50 is fed to the integrator 32 and an input of the OR circuit 52.

Upon receipt of a trigger pulse from multivibrator 28, capacitor C 2 is discharged by temporarily closing switch 52, and flip-flop circuit 50 is set to a first level to provide an output signal with a first, usually high, level Level to generate. The output signal with the first signal level is fed via the OR circuit 52 to the switch 52 in order to open it as long as the output signal remains at its high level and no trigger signals are received from the multivibrator 28. Pulses of preselected periodicity which be picked up by the multivibrator 28

den, close switch 52 and discharge capacitor C2, periodically; thereby the flip-flop circuit 50 remains in its set state to generate a continuous output signal of a constant level. Pulses received from a valid resonance marking circuit in a monitored zone will have this preselected periodicity.

If no pulse is received from multivibrator 28 within the time interval determined by the time constant of the KC integration circuit, switch 52 remains open and capacitor C 2 is allowed to charge to its trigger level and this causes threshold detector 54 to turn on Reset signal for the flip-flop circuit 50 is generated. The FHp-flop circuit 50, when reset, produces an output signal of a second level, usually a lower voltage level, and this indicates the absence of a pulse. The multivibrator 30 thus works as a detector that detects missing pulses, with its circuit then being reset in order to prevent a false alarm and to trigger a new cycle for registering a pulse train.

The integrator 32 and the threshold detector 34 are shown schematically in FIG. 5 shown. The integrator has a resistor R 3 which is connected in series with a capacitor C3 . Signals from the multivibrator 30 are fed to the resistor R 3, while the capacitor C3 is grounded or connected to another reference potential. A diode D 1 is connected in parallel with the resistor R 3 with the polarity shown. A switch, usually a transistor Q 1, has its collector connected to the junction between resistor R 3 and capacitor C3 and its emitter connected to ground or to a reference voltage. A bias resistor R 4 is connected between the base and emitter of transistor Q 1 and the base receives a reset signal from staircase generator and comparator 36 (FIG. 2).

The threshold detector 34 has a voltage divider circuit comprising a resistor R 5 which is connected to the voltage source + V and to the source electrode of a transistor Q 2. The drain electrode of this transistor is connected to ground or another reference potential via a resistor R 6. The grid electrode of the transistor Q 2 is connected to the junction between the capacitor CZ and the resistor R 3 . An output signal is taken from the source of the transistor Q 2 . If an output of opposite polarity is desired, that output can be derived from the drain of transistor Q 2.

When the multivibrator 30 emits a signal with a high voltage level, the capacitor C3 is charged via the resistor R 3 to a reference potential, at which the transistor Q 2 is brought into its conductive state in order to generate an output signal at the output terminal to trigger the alarm. The diode D 1 is inversely biased by the voltage across the resistor R 3. When the multivibrator 30 (FIG. 2) is reset and emits an output signal of a lower voltage level, the capacitor C3 is discharged via the diode D Ϊ and the voltage on the capacitor C3 assumes the lower voltage level value which is then generated by the multivibrator 30, and this voltage is selected so that it is below the threshold voltage at which the transistor Q 2 becomes conductive. As a result, there is no output signal at the threshold detector and no alarm is triggered. The integrator 32 can also be reset by pulses generated by the staircase generator and comparator 36 to prevent triggering of the transistor Q 2 which could result in unwanted output signals. When a reset signal is received, the transistor Q \ becomes conductive and the capacitor C3 is short-circuited to ground or to another reference voltage. The capacitor C3 is thereby discharged during the interval of the reset signal in order to delay actuation of the transistor Q 2 and thereby the resulting output signal for the triggering of the alarm.

The staircase generator and comparator 36 that is provided a reset signal is supplied to the integrator 32. On trigger pulses from the signal processing circuit 22 towards the I reppengcnerator generates a staircase voltage, which for the duration of a each pulse coming from the signal processing circuit 22 rises. The comparator includes a Threshold circuit; and when the staircase signal exceeds a predetermined threshold level, an output pulse is generated which resets the integrator 32. This also causes the stair generator deferred myself. The staircase generator can additionally by a signal from the integrator 32 or from Threshold detector 34 can be reset to properly process successively received To ensure impulses. The voltage characteristic of the staircase generator is designed so that the staircase generator threshold level requires a greater number of pulses to generate a reset signal than the integrator needs to generate an alarm signal.

The operation of the sturgeon shown in FIG

ignaiblck

kierschaltung should be used in conjunction with the signal diagram of FIG. 6 will be explained. The pulses from the signal processing circuit 22 in FIG. 1 are shown in FIG. 6A shown. These pulses are fed to the non-retriggerable monostable multivibrator 28 whose period 7 * 1 is slightly less than that of the pulse modulation. The leading edge of Ti switches multivibrator 30, while multivibrator 28 prevents interfering input signals from triggering multivibrator 30 at a frequency greater than that of the expected signal, as shown in FIG. 6B shows.

The retriggerable monostable multivibrator 30 has a normal period 72 that is slightly larger than the period of the expected signal. Whenever the multivibrator 30 receives a trigger pulse from the multivibrator 28, the multivibrator 30 is reset to its initial value and remains in its high voltage output state for a period T2 after the last trigger pulse. F i g. Figure 6C shows the output of the multivibrator 30, triggering pulses occurring whose period is less than 7 * 2. The voltage of capacitor C2 is shown in Figure 6D.

As long as the capacitor is discharged before the threshold value is reached, the multivibrator 30 remains in its high voltage state.

As long as the multivibrator 30 is in its high voltage state, the output voltage becomes fed to the integrator and generates a rising signal, as shown in FIG. 6E is shown. If the output voltage of the integrator exceeds the threshold, an alarm is triggered.

However, if the multivibrator returns 30 in its state with a low voltage level before time Γ3, wherein is the integration time of the integrator here, that the integration circuit is reset, so that the threshold voltage is not exceeded 5 and not trigger the alarm.

Fun alarm can only be triggered when the multivibrator 30 receives a continuous series of Triggcrimpulssji with a period "t" , where the relationship 7Ί <f < T2, applies and this series of Trig- ίο gerimpulses continues over a period of time that is greater is as T3. In the case of the in FIG. 2, the entire circuit is reset as soon as the multivibrator 30 measures the first pulse. Alternatively, the multivibrator 30 can be modified so that more than one pulse must be measured before the integrator is reset.

For this purpose 2 sheets of drawings

20th

25th

30th

35

40

45

50

55

60

65

Claims (4)

Patent claims: 1. Electronic security system with an interference signal blocking circuit, a transmitter (10) which generates an electromagnetic field in a monitored zone with a frequency which is swept in a predetermined frequency range with a preselected period, and a receiver (16-26) which Presence of a resonance marking circuit (15), which has a resonance frequency within this frequency range, in the monitored zone, by means of a first device (22), which receives a pulse train generated by a resonance marking circuit (15) as well as interference signals, and a second device (32,34) which sums up the received pulses in an integrator (32) with the integration time 73 and, after receiving a predetermined number of pulses generated by the resonance marking circuit (i5), triggers an alarm (26) within a preset time, the interference signal blocking circuit (24) with a non-retrigger monostable multivibrator (28) is arranged between the first (22) and the second (32, 34) device and distinguishes between the presence of a resonance marking circuit (15) in the monitored zone and an error signal by only sending pulses with the preselected periodicity t lets through, namely by means of a Pe. ^ ode Tl of the non-retriggerable multivibrator (28). which is somewhat shorter - = "· than the periodicity f, characterized by a device (30) in the Störsignalblockiarsch titung (24), which is connected upstream of the integrator (32) and resets it after detecting at least one missing pulse in the pulse chain. 2. Safety system according to claim 1, characterized in that that the device (30) in the interference signal blocking circuit (24) is designed so that it the integrator (32) after determining a preselected number of several in the pulse chain resets missing impulses. 3. Safety system according to claim 1 or 2, characterized in that the device (30) in the interference signal blocking circuit (24) is a retriggerable monostable multivibrator connected downstream of the non-retriggerable multivibrator (28), the period 72 of which is slightly greater than the periodicity t . 4. Safety system according to claim 3, characterized in that the retriggerable multivibrator (30) controls the integrator (32) with a signal integrated by it with a preselected first level, as long as a registered pulse chain is not interrupted. and in the absence of an impulse switches a second level and that the integrator (32) has a switching device (50, 54) which resets it when receiving the signal with the second level: