DE2436648A1 - MEMORY CELL FOR AN FIELD OF DYNAMIC MEMORY CELLS - Google Patents

Description

PATENT LAWYERS

DIPL.-ING. LEO FLEUCHAUS DR.-ING. HANS LEYH

Dipl. -Ing ·, Ernst Iiathmann

Münch.n7i, July 27, 1974 Melchloretr. 42,

Our reference: MO 154P-1185

Motorola, Inc.

5725 East River Road

Chicago, I llinois 60631

United States

Memory cell for an array of dynamic memory cells

The invention relates to a memory cell with a transistor, the first main electrode of which is connected to a storage node and dossed second main electrode is connected to a read / write line and whose gate electrode is connected to a first selection line, for an array of dynamic memory cells.

Dynamic memory cells consisting of a single MOS transistor have already been proposed in order to achieve the highest possible packing density for monolithically integrated storage with direct access. This memory cell comprises a MOS transistor, its drain to a read-write line, its gate to a select line and its Source is connected to one side of a storage capacitor.

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The other side of the storage capacitor is ontwodcr from the substrate or formed by a supply line. During the writing process becomes the charge stored on the storage capacitor via the MOS transistor, if this is through a via dio selection line applied voltage is switched on, transferred to the capacitance formed by the Lesc write line. As the storage capacity usually only a fraction of the capacity of the read / write line is the tapped voltage change on the read / write line tiny. One way of increasing the amplitude of the voltage change on the read-write line is to increase the Increasing the capacity of the storage capacitor. However, this significantly increases the area required for the capacitor, so that the packing density on a semiconductor wafer is reduced to an undesirable extent and the cost per bit of a memory increase significantly.

The invention is based on the object of providing a dynamic memory cell using a single transistor and a storage capacitor to create that makes it possible to get by with fewer lines on the semiconductor die and the packing density for to significantly increase an array of memory cells.

This task is based on the memory cell mentioned at the beginning solved according to the invention in that a storage capacitor with its first side to the storage node and with its second side to a second selection line is connected.

Further features and refinements of the invention are the subject matter of further claims.

In a memory field constructed according to the measures of the invention

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using the memory cell according to the invention, ee is possible, on a variety of with the second side dos storage condenser to dispense with connected lines, which increases the packing density of the field of dynamic memory cells can be increased significantly and an increase due to the resulting lower line capacitance of the storage capacitor with the same detectable Can avoid voltage change on the read-write line.

The advantages and features of the invention also emerge from the following description of an exemplary embodiment in conjunction with the claims and the drawing. Show it:

Fig. 1 is a circuit diagram of part of an array of dynamic Memory cells according to the invention;

FIG. 2 shows waveforms for describing the mode of operation of the embodiment according to FIG. 1 during a writing operation; FIG.

FIG. 3 shows further waveforms for describing the reading and renewal operation of the circuit according to FIG. I.

In Fig. 1, a monolithically integrated storage system is described, comprising an array of dynamic memory cells, which are shown to include transistors 18, 24, 30 and 36. The storage system 10 comprises a read-write renewal circuit 14 and a selection circuit, which are both connected to the array 12 of dynamic memory cells.

Each of the four illustrated dynamic memory cells 18 ,? A, 30 and in the field is constructed in the same way and comprises a MOS transistor with two main electrodes, which act alternately as drain or source.

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can be sam. The control electrode acts as a gate, the reciprocal The use of the main electrodes as a source or drain is known to those skilled in the art for field effect transistors of the enhancement type. Therefore, in the following description, the designation of a Electrode as drain or source should in no way be understood as restrictive.

The gate of each field effect transistor is connected to a selection line, whereas the one main electrode, in the present case the Source, connected to a storage node. Each memory cell also includes a storage capacitor that is connected to one side Storage node and the other side is on a second select line.

The memory cell 18 according to FIG. 1 contains a field effect transistor 20, the drain of which is connected to a read-write line 50 and the source of which is connected to the storage node 42. The gate is connected to a column select line 56. The spinner capacitor 22 is connected on the one hand to the storage node 42 and on the other hand to a column selection line 58. In a corresponding manner, the Memory cell 24 has a field effect transistor 26, the drain of which is connected to the read-write line 50 and whose source is connected to a storage node 44. The gate of this field effect transistor stands with a Column select line 54 in connection. A storage capacitor 28 is connected on the one hand to the storage node 44 and on the other hand to the column selection line 56. The memory cell 30 comprises a field effect transistor 32, its drain to read / write line 52, its gate to the column select line 54 and whose source is connected to the storage node 43. A storage capacitor 34 is with its one side with the Storage node 46 and connected on its other side to the column selection line 56. The memory cell 36 also includes a field effect

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transistor 38, whose drain to the read-write line 52, whose Gate with the column select line 50 and its source with a Storage node 48 is connected. A storage capacitor 40 is connected on the one hand to the storage node 48 and on the other hand to the column selection line 58.

It is obvious that the illustrated matrix field 12 is related to both the number of columns and rows can be expanded as required, as indicated by the arrows on the read write lines 50 and 52 and the column selection lines 54, 56 and 58 indicated is. As a rule, such a matrix field contains M-Rethen and N-columns, with one side of the storage capacitor of each individual Memory cell in a given column is connected to the (n + 1) th column select line, where η is less than N and N is an integer is. A power supply line may be required for the Nth column of the memory cells in order to connect them to the corresponding connection of the respective memory cells to be provided in this column, as a function of from the topology of the memory cell layout, there is no (n + 1) th column select line. However, the memory cells be arranged so that this supply line is unnecessary.

As can further be seen from Fig. 1, the read-write lines are 50 and 52 connected to a read-write renewal circuit 14, which, in conjunction with the selected memory cell, form the oscillations A and B according to FIGS. 2 and 3 via the read-write lines 50 and 52 returns. This read-write renewal circuit can also Select and row decoding circuits include »

Similarly, the column select lines 54, 56 and 58 connected to the selection circuit 16, which is an address reversal circuit, a column decoder circuit and a driver circuit

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grasps. The signals supplied by the selection circuit are explained in terms of their waveforms by the representations C, D and E in FIG. 2 and are applied to the column selection lines 54, 56 and 58. The mode of operation of the monolithically integrated memory system 10 is described with reference to FIGS. 2 and 3 using the example of writing a logical 0 or a logical 1 into the memory cell 18. The waveforms A, B, C, D and F are correspondingly applied to the lines 50, 52, 54, 56, 58 and to the storage node 42 for the following description. ^k

The following discussion assumes that the MOS transistors 1 have an N-conducting channel path and that the pulse * voltage according to FIGS. 2 and 3 is positive. The time axis, not shown, for FIGS. 2 and 3 runs horizontally, whereas the voltage runs longitudinally plotted in a vertical direction. It is also assumed that a logical 1 Von has a positive voltage of about 15V and represents a logic 0 from a voltage of approximately 0V will.

To write a logical 1 into the memory cell 18, a the voltage corresponding to logic 1 - of about 15 V on the read / write line 50 with oscillation shape A is effective. By applying a positive voltage on the column select line 56 corresponding to the waveform D, the transistor 20 is conductive State switched. As can be seen from Fig. 2uid 3 for the signal curve B, C and E can be seen, a ground potential acts on the lines i »2, 54 and 58. This leaves the corresponding connected Side of the storage capacitor 22 at ground potential during the write process lie. The voltage written into the memory cell at the memory node 42 is represented by the waveform F. Of the Signal curve A according to Fig. 2 indicates that the voltage on the read

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Write line 50 between point A1 and point A2 "I in the Way changes that a logical 1 is written into the memory cell 18. A positive voltage can then be applied to the column selection line 50 are applied to thereby turn on the transistor 20, which is indicated by the waveform between the points Dl and D2 of the waveform D is indicated. A person skilled in the art recognizes that the positive signal course corresponds to the waveform D after the positive one An increase in the waveform A need not necessarily occur, although this is shown in FIG.

The voltage in the storage node 42, which is caused by the waveform F, increases when writing a logical 1 or, decreases when writing a logical 0 to essentially the voltage of waveform A. The solid line of waveform A represents the logical 1, while the dashed curve between the points A1 and A4 the course of the waveform for the logical 0 indicates. Correspondingly, the voltage at the storage node, which is represented by the waveform F, follows the waveform A, where a logical 1 is indicated by the solid curve and a logical one by the dashed curve of the waveform F. As soon as the desired logic state is reached by a charge or discharge in the storage node 42, the transistor 20 must be switched off as indicated by the course of the waveform D between points D3 and D4. It is important that this The voltage change takes place before the voltage change for waveform A takes effect between points A3 and A4, otherwise the The voltage represented by waveform F follows the voltage of waveform A and thereby that to be written into memory cell 18 Information destroyed.

The write and renew cycle of the monolithic storage system

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according to FIG. 1, the waveforms according to FIG. 3 described. Here, too, characterize the fully extended waveforms A and F a sampled and renewed logical 1, whereas when sampled and renewed a logical 0 the waveforms correspond to the dashed curve. The output voltage in storage node 42 is determined by the beginning of the waveform Voltage assigned to F. During the initial part of the scan and refresh cycle, before the refresh. If the point Dl reaches the waveform D, the Lene writing line is located 50 to an intermediate voltage of, for example, 7.5 V. If the memory cell 18 by switching on the transistor 20 is selected, wherein the waveform D changes its voltage at point Dl to the voltage at point D2, the stored in capacitor 22 is Charge partially to the capacitance 70 of the read-write line distributed, this capacitance is typically 5 to 15 times greater than the capacitance of the storage capacitor 22. Therefore, the voltage increases of waveform A when a logical 1 is stored in storage node 42 is, due to the charge distribution between the storage capacitor 22 and the capacitance 70, slightly on, as is part of it the waveform between points A1 and A2 is evident. if on the other hand, a logic 0 is stored in the storage node 42, the waveform A decreases slightly, as indicated by the course of the Waveform A between points Al and A7 is indicated.

The scanning thus initially destroys the logical one in the storage node 42 stored signal, as can be seen from the waveform F according to FIG. 3. This waveform shows that with a stored logic 1, the voltage in storage node 42 drops to a value that is slightly higher than the initial intermediate voltage of waveform A, in the present case than 7.5 V, as indicated by the course between the points Fl and F2 is indicated. Accordingly, for a different

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initially stored O is the stored voltage in storage base 42 raised from 0 to a value that is slightly below the intermediate value of about 7.5 V in the present case, which is indicated by the course indicated by the dashed line between points F5 and F 6

This means that every time the stored information is accessed takes place, d. H. the stored information is scanned, a renewal of the stored information has been provided. The change the voltage on the read-write line is determined by the read-write renewal circuit 14 noted. This voltage is amplified and fed back into the scanned memory cell, as by ' the course of waveform A for a logical 1 between points A3 and A4 and for a logical 0 between points A8 and A9 in Fig. 3 is indicated. Since transistor 20 is conductive, the voltage in storage node 42, i.e. waveform F, follows the voltage of Waveform A, as shown by the course between points F3 and F4 for a logical 1 and between points F7 and F8 for a logical 0 is indicated. In order to avoid a destruction of the renewed information, the transistor 20 must before any further Signaländorung, such as this is indicated between points A5 and A6 of waveform A, can be switched off. For this reason, the voltage curve of waveform D between points D3 and D4 before the mentioned signal change of waveform A between points A5 and A6 take place.

The memory cell according to the invention can be used both during manufacture of integrated circuits made of field effect transistors according to the known metal gate method as well as according to the known silicon gate method can be used, however, is the metal gale process somewhat more advantageous, since the read-write lines doped continuously

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Semiconductor areas can be while the column lines are passing through Metal lines can exist. This means that there are no prohmic contacts necessary. The memory cell according to the invention differs from the known prior art in that the one side of the storage capacitor not in the known manner with one Supply line is connected, but to a second selection line and the second selection line is not connected to the control electrode of the transistor of the associated memory cell. Much more this second selection line is connected to the control electrode of the transistor of the adjacent memory cell.

A major advantage of the memory cell according to the invention is « that in the field of the memory cells the additional supply line for connection to the storage capacitors for all columns with the exception of the last column of the memory cells can be omitted. In order to the packing density for the array of memory cells can be increased significantly, since the area required for an array is predominantly is determined by the needs of the lines. This advantage also results in the further advantage of improving the switching behavior, since the line lengths and thus the capacitance of the read / write lines are reduced, which leads to higher scanning voltages.

The memory cell according to the invention is advantageous for this suitable to replace memory cells of a known type, as in conventional Way to be manufactured as MOS integrated circuits. It is expected that the mentioned advantages of greater packing density and the higher operating speed can be improved even further if the memory cells are on isolated substrates can be formed, whereby a further reduction in the capacity of the read-write lines can be achieved. You can actually use the Size of the storage cell and that required for the storage capacitor

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Reduce space requirements, with the advantage that less semiconductor area is required for lines, becomes even more important because the additional supply line is no longer required.

An example implementation of the invention in a memory array in the metal gate process with MOS elements with N-type .The duct section enables the use of a 15 V power supply. The ratio between the storage capacity and the capacity of the read-write line can vary between about 1: 5 to about 1:15 in Depending on the packing density, the scanning circuit and the desired access time, i.e. the time that is required to obtain information from a certain point to the data output of the storage system to be transmitted after a read signal has been applied.

It is obvious that modifications in the described .. circuit are possible to meet different operational or functional requirements to meet. Such different designs of the circuit according to the invention are, however, within the range of what is customary for a person skilled in the art.

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Claims (7)

MO154P-1185 Claims Memory cell with a transistor, the first main electrode of which has a storage node and the second main electrode of which is connected to a read-write line and its gate electrode to a first selection line, thereby characterized in that a storage capacitor (28) with its first side connected to the storage node (44) and with its second side connected to a second select line (56) is. 2. Memory cell according to claim 1, characterized in that that the transistor is an enhancement type field effect transistor whose control electrode is the gate electrode. 3. Memory cell according to claim 1 or 2, characterized in that that the second selection line is connected to the control electrode of a second memory cell. 4. Storage cell in a storage array with direct access that consists of M χ N memory cells in M rows and N columns, where in the rows M read-write lines and in the columns N select lines run, characterized in that the first Main electrode of each field effect transistor in the memory cells is connected to a storage node to which the first side of the memory. capacitor is connected that the second main electrode of the field effect transistors in the mth row of memory cells to the mth read-write line is connected, where m is a whole 509810/0683 MO154P-1185 Number less than or equal to M of a certain row is that the gate electrode of the field effect transistor in the nth column to the corresponding nth selection line is connected, where η is an integer less than or equal to N, which is a specific Column indicates that the second side of each storage capacitor in the nth column is connected to the (n + l) th selection line, where η is an integer smaller than N, 5. memory cell in a memory array according to claim 4, characterized characterized that with the M-read-write lines a Read-write renewal circuit (14) is connected, and that a selection circuit (16) connected to the N selection lines is. 6. memory cell in a memory array according to claim 4, characterized characterized in that the N selection lines are made of metal lines and the M read-write lines are composed of doped silicon regions. 7. memory cell in a memory field, characterized in that that the doped silicon regions are arranged on an insulated substrate. 509810/0683 Blank page