DE2436207A1 - DIGITAL DETECTOR CIRCUIT TO DETERMINE THE SLOPE OF ANALOG SIGNAL - Google Patents

Description

LIGNES TELEGRAPHIQUES ET TELEPHONIQUES 89, rue de la Faisanderie
Paris, France

Digital detector circuit for determining the slope of an analog signal

The invention relates to a detector circuit for the slope of a signal, and more particularly to a detector circuit digital art,

The slope detector circuits are essentially based on the differentiation of the amplitude of a signal with respect to time. They are often used in data processing systems in which the data is supplied by physical or chemical measuring devices, such as chromatographs, which emit aperiodic analog signals which are accompanied by background noise. These signals appear in general in the form of pulses having a substantially Gaussian ¹ shear distribution, whose parameters, which is such as amplitude and mean square deviation, to change in a very wide range of values, for example, the relative value according to the order of 10 degrees.

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The state of the art includes slope detectors, which form components of integrating devices that are intended for this purpose are to determine the integral of a bell-shaped or similar signal. With these devices, the waveform of the signal is differentiated according to time, so that the rising parts of the curve shape are positive Signal, a zero signal for the maximum and a negative signal for the descending parts of the curve shape will. On the other hand, these devices contain a voltage-to-frequency converter that delivers impulses Repetition frequency at any point in time is proportional to the amplitude of the signal «, The analog differentiating circuit is used to determine the duration of the analog signal ", and the variable repetition rate pulses generated by the converter are counted during this period. The sum obtained is a measure of the integral of the bell curve.

It can thus be seen that in these devices the count takes place digitally, while the measurement of the duration takes place analogue. The duration is measured on an RC circuit the two Schmitt flip-flops follow, and the limits of the obtained integrals are ill-defined.

The object of the invention is to create a slope detector of great precision that operates entirely digitally.

According to the invention, the digital slope detector is arranged at the output of the voltage-frequency converter of the integrating device and characterized in that it has a negative feedback loop which receives at its input input pulses originating from the converter, as well Loop pulses that originate from the negative feedback loop »whose forward branch facilities for subtraction

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of the loop pulses from the input pulses and one contains the first frequency divider, and its negative feedback branch includes a second frequency divider with a controllable division factor and includes a digital integrating circuit.

The means for subtracting the input pulses and the loop pulses are through an up-down counter educated. There is no synchronous position between the input pulses and the loop pulses exists, it is possible that an input pulse and a Loop pulse at the same time at the forward input or At the countdown in the up / down counter: appears. To avoid this possibility is an anti-coincidence circuit is inserted in the forward branch in front of the up / down counter.

To increase the sensitivity of the slope detector must be the division factor of the frequency divider in the loop can be increased, which corresponds to an increase in the filtering and the gain factor, thereby making the determination is favored by very slight gradients. However, a very selective filtering has the disadvantage that at the end of the slope detection delays are generated, that is, the occurrence of a slight slope which immediately follows a steep slope is covered. To avoid this disadvantage, the division factor of the lying in the negative feedback loop frequency divider depending on the value of the slope in the course of the Changed detection making the loop non-linear.

Further features and advantages of the invention result from the following description of an exemplary embodiment with reference to the drawing. In the drawing show:

1 shows a block diagram of the slope detector according to Invention,

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Fig. 2 is a more detailed circuit diagram of the frequency compression circuit, which is assigned to the voltage-frequency converter,

3 shows a more detailed circuit diagram of the anti-coincidence circuit,

4 shows a diagram of signals for explaining the anti-coincidence circuit,

Fig. 5 is a circuit diagram of the up-down counter for the subtraction of the input pulses and the Loop pulses and

Fig.6 the controlled frequency divider and the digital Integrating circuit, which are in the negative feedback loop.

The slope detector shown in FIG. 1 has the form of a negative feedback circuit and contains a source 1 for the analog signals to be analyzed, a voltage-frequency converter 2, a dynamic range compression circuit 3, a subtraction circuit 4, a first frequency divider with the division factor k ^ and two Frequency comparators 6 and 6 ^f , which compares the frequency of the output signal of the slope detector arrangement with two frequency thresholds which define the positive slope and the negative slope.

The negative feedback loop contains a second frequency

t Cj er f

zäfeier 7 with the division factor kpi by a slope measuring circuit 8 is controlled like a frequency meter, and an integrating circuit 9.Der frequency divider introduces a non-linearity into the loop.

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The transfer function of the circuit of Fig. 1 is

k _£ pt

1 + k ₁

Here k ^ and k _{2 are} the already mentioned division factors of the frequency dividers, ρ the Laplace variable and τ the time constant of the integrating circuit 9. As already mentioned, the division factor k ₂ depends on the value of the slope measured by the frequency meter 8.

The dynamics compression circuit 3 is shown in more detail in FIG. It contains a pulse generator 300 which supplies pulses with the frequency 2f ^ = 20 kHz, and which is followed by a frequency divider 301 with the division factor 2, which emits pulses with the frequency f = 10 kHz. The dynamic range compression circuit also contains a frequency divider 302 which divides the frequency f of the output signal of the voltage-frequency converter 2 by the factor 10 and which is followed by a second frequency divider with the division factor 10. The circuits 300, 301, 302, 303 thus supply pulses with the frequencies 2f ₁ , f ^, f / 10 and f / 100, respectively. The frequency f is between 0 and 1 MHz, as will be seen later.

Two. Sequence detectors 304 and 305 receive the input signal e with a variable frequency and generate an output signal for f ^ f ₁ or for f ^ f ₂ with f ₂ = 10f ₁ . The output signal of the frequency detector 305 controls AND circuits 306 and 307, which the pulses with the frequency f / 100 and v /. receive the pulses at the frequency 2f ^. That to the output of the frequency detector

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The complementary signal and the output signal of the frequency detector 304 control AND circuits 308 and 309 which receive the pulses with the frequency f _1Q and the pulses with the frequency f ^, respectively. Finally, the signal complementary to the output signal of the frequency detector 3o4 controls an AND circuit 310 which receives the pulses with the frequency f.

The outputs of the AND circuits 306, 308 and 310 are connected to the inputs of an OR circuit 311, and the outputs of the AND circuits 307 and 309 are connected to the inputs of an OR circuit 312. Finally, the outputs of the OR circuits 311 and 312 are provided with an anti-coincidence and adding circuit 313 connected, the output of which delivers the signal E. One embodiment of the anti-coincidence circuit is made later, described.

It can be seen that the dynamic range compression circuit performs the following compression:

Frequency f the frequency of the

Input pulses e output pulses E

f ^ f ₁ = 10 kHz (310 open) "f

10 kHz = f ^ f <f ₂ = 10OkHz (308 and -309 open) f ₁ + f / 10

f ^ f ₂ = 10OkHz (306 and 307 open) 2 ± _Λ + f / 100

One could of course choose other values for f ^ and f ₂ as well as other fractions of f than 1/10 and 1/100.

The shown in Fig. 3 and 5 subtracting circuit 4 consists of an up-down counter, the pulses the negative feedback loop subtracts from the input pulses. Since this up / down counter cannot work, when he simultaneously has a count-up and a

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Receives a countdown pulse, must give it an anti-coincidence circuit be connected upstream, which prevents this state. The subtraction circuit 4 thus consists of an anti-coincidence circuit, which is followed by an up / down counter.

The purpose of the anti-coincidence circuit is ^{to convert the two input pulse trains E +} and E ~ "into two output pulse trains st and S7 of such a type that no pulse of the pulse train S ^ appears simultaneously with a pulse of the pulse train ST. if there are no output pulses S * and S-, the output terminals assume their digital signal value 1.

The anti-coincidence circuit includes a pulse generator 401, which generates square-wave pulses with a repetition frequency that is significantly higher than the maximum frequency of the input pulses, i.e., for example, significantly higher than 1 MHz. The square pulse generator 401 feeds two bistable multivibrators 402, 403 at their clock input T, namely the flip-flop 402 via an inverter 404 and the flip-flop 403 directly.

These flip-flops 402 and 403 are JK flip-flops. The output Q of each of these flip-flops is connected to its inputs J and K. the Inputs E and E "are connected to the reset inputs RAZ of the bistable multivibrators. To the outputs Q the bistable flip-flops 402 and 403 are each connected to a monostable flip-flop 405 or 4o6, the outputs of which generate the signals S * or sT.

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4 shows at T, E ⁺ , E ", Q 402, Q 403, s \ and S ~ the input and output signals of the bistable flip-flops 402 and 403 and the monostable flip-flops 405 and 406. It can be seen that the negative transitions of the clock signal T bring the output signal Q 403 to the value 1, and that the positive transitions of the clock signal T bring the output signal Q 402 to the value 1. The signal values 0 of the reset signals E ⁺ and E ~ bring the output signals Q 402 and . Q can be seen 403 to the value 0. As shown in Figure 4, it follows that the signal Q 402 is a sequence of pulses, whose number is equal to the number of the pulses e ^+, the positive transitions to the positive transitions of the Clock signal are synchronous and whose negative transitions are synchronous with the negative transitions of the pulses E, and that the signal Q 403 is a sequence of pulses, the number of which is equal to the number of pulses E ~ whose positive transitions with the negative transitions of the clock signal than are synchronous and their negative transitions are synchronous with the negative transitions of the pulses E ~. The signals Q 402 and Q 403 trigger the monostable multivibrator 405 or the monostable multivibrator, which deliver pulses whose duration is less than half the period of the clock signal, for example equal to a quarter of the period of this clock signal, so that any overlap of the pulses S * and S ^ is avoided.

The pulse subtraction circuit (Fig. 5) is an up / down counter 410 with four stages, whose up-counting input 411 is connected to the output S ^ of the anticoincidence circuit is connected and its countdown input 412 is connected to the output S ^ of the anticoincidence circuit. The counter 410 has two carry outputs 413 and 414; the output 413 provides output signals S ^, if a positive carry when the counter is full appears, and the output 414 supplies output signals S ^,

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if "a negative carry appears when the counter is empty.

A commercially available circuit manufactured by Texas Instruments under the designation SN 74 193 N is used for a particularly simple design of the up / down counter. This circuit has four flip-flops A, B, C, D and can therefore count up to 15. It has an up count input and a down count input. That one of these inputs which does not receive any pulses must be left at the binary signal value 1, and this is the reason why an anti-coincidence circuit is connected upstream of the up / down counter. The up-down counter also has a preset control input, which is used to write a predetermined counter reading into the up-down counter, and a clear input, as well as two carry outputs, namely a positive carry output, at which a pulse appears when. Down counter, after it has reached its maximum count, receives a pulse at its up count input, and a negative carry output, at which a pulse appears when the up / down counter, after it has reached the count O ·, receives a pulse its countdown input receives - * - The positive carry output is connected directly to the preset control input, while the preset inputs E., E _ß , E _c , E _{D are} all held at the signal value 1, and the negative carry output is connected to the clear input via an inverter RAZ.

It is assumed that the counter is empty at the beginning and that pulses appear at the up-counting input. You change the One after the other the binary digits A, B, C, D. At the fifteenth pulse the counter is full. The sixteenth impulse expresses itself that a pulse appears at the positive carry output and at the common preset control input,

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This results in the binary digits A, B, C, D being blocked in position 1, and the pulses subsequently fed to the up counting input can be found at the positive carry output. It can therefore be seen that as soon as the counter has reached the count 15, the subsequent up-counting pulses go through the up-down counter ⁿ ".

If pulses to the downward counting input when the counter is full are supplied, the counter is emptied and the positive carry output no longer receives any pulses. The binary digits A, B, C, D are then released and take on values that correspond to the respective count. if Six downward counting pulses have arrived, the counter reading 9 is written. If now eight count-up pulses arrive, the counter reading 17 is written. The difference is 8 - β = 2. When counting down, there is no Pulse fed to the negative carry output. When counting up, the counter readings 10, 11, 12, 13, 14, 15 corresponding pulses do not pass through the counter, but those corresponding to counter readings 16 and 17 Pulses go through the counter and appear at the positive carry output, which is the difference between supplies the count up pulses and the count down pulses,

If pulses are fed to the up counter input when the counter is empty, the counter and the negative one fill up The carry output no longer receives any pulses. The binary digits A, B, C, D are activated in sequence and assume values that correspond to the respective count. When six count-up pulses have arrived, that is Counter reading 6 inscribed. If now 8 downward counting pulses appear, the counter reading -2 is written. The difference is 6 - 8 = -2. When counting up, no pulse fed to the positive carry output .. At

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the down counting go the counter readings 6, 5, 4, 3, 2, 1.0 does not pass through the counter, but the pulses corresponding to the counts -1 and -2 go through the counter and appear at the negative carry output, which is the difference between the reverse counting pulses and the forward counting pulses.

The frequency divider 7 with the controllable division factor k ₂ is shown in FIG. It contains an actual frequency divider 700, which divides the frequency by a certain factor, for example a factor of 32, and is located on the positive output path and on the negative output path of the frequency divider 5 of the forward branch. The positive input and the positive output of the frequency divider 700 are connected to the up-counting input of an up-down counter 704 via AND circuits 701 or 702 and an OR circuit 703. The negative input and the negative output of the frequency divider 700 are connected via AND circuits 711 and 712 and an OR circuit 713 to the downward counter input 715 of the up / down counter 704. It can thus be seen that the up / down counter 704 counts up or down pulses whose frequency has been divided by the frequency divider alone, or pulses whose frequency has been divided by the two frequency dividers 5 and 7.

The pulses of the positive output path and the pulses of the negative output path of the frequency divider 5 are fed to the frequency meter 8, which consists of two four-stage counters 801, 802 for the positive path and two four-stage counters Counters 811, 812 for the negative path exist. These counters are cleared by clock pulses, their repetition frequency is dimensioned so that when there is no frequency division, i.e. at the maximum frequency, the Counters have enough time to fill up between two erase pulses.

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The places 2 ⁵ , Z ^, 2 ⁵ , 2 ^{6 of} the counters 801-802 are connected to AND circuits 803, 804, 805, 806, the outputs of which are connected to an OR circuit 807. The output of this OR circuit 807 is connected to a JK trigger circuit 808, the outputs of which control the AND circuits 701 and 702. The AND circuits up to 806 are selectively opened via connections according to the desired selectivity.

The positions 2 ³ , 2 ⁴ , 2 ⁵ , 2 ^{6 of} the counters 811-812 are connected to AND circuits 813, 814, 815, 186, the outputs of which are connected to an OR circuit 817. The output of this OR circuit 817 is connected to a JK trigger circuit 818, the outputs of which control the AND circuits 711 and 712. The AND circuits up to 816 are selectively opened via connections according to the desired selectivity.

The digits 2 ° and 2 ^{2 of} the counter 801 and the digits and 2 of the counter 811 are connected to a toggle circuit 609, 610 and a toggle circuit 619, 620, respectively. The flip-flops 609 and 610 are connected to one another via an AND circuit 621, which also receives the clock pulses, and via an inverter 622. The flip-flops and 620 are connected to one another via an AND circuit 631, which also receives the clock pulses, and via an inverter.

The trigger circuit pairs 609, 610 and 619, 620 each form a comparator with hysteresis. A signal P ^{+ is obtained} for a positive slope at the output of the flip-flop 610 and a signal P for a negative slope at the output of the flip-flop 620 when the frequency of the

ρ
Impulse is proportional to 2 and this signal only stops when the frequency of the impulses, down to the

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same proportionality factor, falls below 2. A NAND circuit 740 supplies the signal P ⁰ for the slope O. Hysteresis comparators of this type are known per se and are described, for example, in the French additional patent application 72/44 695 to the French patent specification 1,570,486.

The up-down counter 704, for example sixteen Has flip-flops, its counter reading can be transferred to a binary multiplier circuit 900, which is processed by a pulse generator 901 is controlled. The binary multiplier circuit 900 supplies the signal E ~, that of the anti-coincidence circuit is fed. The pulse generator 901 generates pulses with a frequency of 1 MHz. It is recognizable, that in this case the time constant τ has the following value:

τ = 2 ^16/1 MHz = 65.5 ms.

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Claims (4)

Claims cn e ./Digital detector circuit to determine the direction the slope of an analog signal of the analytical type with a voltage-frequency converter for the analog signal and with a negative feedback loop attached to their Input receives input pulses that come from the converter, as well as loop pulses that come from the negative feedback loop originate whose forward branch facilities for subtracting the loop pulses from the input pulses and contains a first frequency divider, and its negative feedback branch with a second frequency divider controllable division factor and a digital integrating circuit, the subtraction devices by an up / down counter are formed which delivers an overshoot signal when the absolute value of the Difference between the number of input pulses and the number of loop pulses has a predetermined value exceeds, characterized in that the up-down counter is assigned an anti-coincidence circuit in this way is that the input pulses and the loop pulses are not simultaneously on the up count input and arrive at the down counting input of the up / down counter. 2. Digital detector circuit according to claim 1, characterized in that that the loop has a frequency meter, and devices controlled by the frequency meter for changing the Contains division factor of the second frequency divider. 3.Digital detector circuit according to claim 1 or 2, characterized characterized in that the digital integrating circuit in the negative feedback branch has an up-down counter, to which a shift register is assigned, and means for serial output of the contents of the up / down counter contains as loop pulses. 509809/0735 4.Digital detector circuit according to one of claims 1 to 3, characterized in that the loop circuit with negative feedback branch contains two digital comparators which only deliver a digital signal when the frequency of the input signal is greater than a predetermined value. 509809/0735