DE2435420B2 - Control device for a vending machine - Google Patents

Description

a) the comparator (16) is connected to a disbursement device (28) for the remaining money;

b) the payout device (28) controls the clock generator (12);

c) the clock (12) leads the second accumulator during the payment of the remaining money (20) to the purchase price to be added to the issued coins corresponding coin value pulses; and

d) the comparator (16) generates a blocking signal for the payout device (28) if the values stored in the two accumulators (14, 20) are the same.

2. Control device according to claim 1, characterized by a blocking circuit (18) between the second accumulator (20) and the comparator (16).

3. Control device according to a * .m of claims 1 or 2, characterized by a difference decoder (24) connected to the comparator (16) with outputs which show the difference between the sizes stored in the two accumulators (14, 20).

4. Control device according to claim 3, characterized in that the two accumulators (14, 20), the comparator (16) and the differential decoder (24) by a single integrated circuit are formed.

5. Control device according to one of claims 1 to 4, characterized in that the two Accumulators (14, 20) are formed by several bistable flip-flops connected in series.

6. Control device according to one of claims 1 to 5, characterized in that the payout device (28) as a function of the difference the sizes of coins with different sizes stored in the two accumulators (14, 20) Outputs values.

7. Control device according to one of claims 1 to 6, characterized in that the clock generator du> * ch an oscillator circuit is formed.

8. Control device according to one of claims 5 to 7, characterized in that the comparator (16) contains several summing circuits, each with the corresponding bistable flip-flops of the two accumulators (14, 20) are connected.

The invention relates to a control device for a vending machine of the type specified in the preamble of claim 1.

From DE-OS 20 60 642 ei "e is through coins

actuatable merchandise sales device known in which a bidirectional counter for storing the amount of money inserted and correlating it Amount is used with the sales price. Of the Any amount thrown in beyond the purchase price can be spent again.

From DE-AS 17 74138 a control device is known for a vending machine in which a bidirectional counter is also used. This takes place

ίο no review of the beyond the purchase price thrown in, to be disbursed again, but when such a difference occurs Payout pulses are generated until the count reaches zero

From GB-PS10 70 005 there is a change machine

known that also at a vending machine can be used. A comparator is used for used to compare different amounts of money

Furthermore, from US-PS 33 44 898 a control unit

direction for a vending machine known in the a bidirectional counter is also used. Of the is the amount of money thrown in above the purchase price lost, so will not be refunded

Finally, from US-PS 33 65 045 one

Control device for a vending machine of the specified type known, which has a clock, the generated coin value pulses for a first accumulator according to the inserted coins, one second accumulator for the purchase price of the goods, one stored in the two accumulators Comparator sizes comparing and one connected to the comparator, the output of the goods only This vending machine has a blocking device that enables a certain amount to be entered

J5 can only dispense one specific product, namely, for example, gasoline at a gas station, with each a certain amount of petrol to be dispensed is assigned to a certain amount of money thrown in. The output of the amount of money that represents the value of the the amount of petrol removed, as would be desirable, for example, when the tank is full not possible.

The invention is therefore based on the object of a control device for a vending machine to create the specified category, with the issue of different goods with different prices even beyond the purchase price sums deposited can be repaid and the expenditure of these amounts can be precisely controlled.

This object is achieved according to the invention by the features specified in the characterizing part of the new claim 1

Appropriate embodiments are compiled in the subclaims.

The advantages achieved by the invention are based in particular on the fact that with the locking device connected comparator not only output the goods after entering a sufficient amount of money, but also the payment of the remaining money wakes up; this results in a very exact one Control of the issue of each individual coin, which ensures that only the remaining money and a higher amount is not spent again. In addition, this monitoring of the remaining money

b5 the one in the coin unit for the coins inserted Existing clock is used for generating the coin value pulses, so that despite this accurate Control of issued coins no high

additional design effort is required, because the existing components can largely be used. And finally, requires even when changing the coin system or a Change in the purchase price this payout facility does not require extensive maintenance work, as this Maintenance work must already be carried out in the coin unit and at the same time also the Adjustment of the associated components of the payout device takes place, namely the! Comparator and the Clock.

The invention is illustrated below by means of exemplary embodiments with reference to Schematic drawings explained in more detail It shows

P i g. 1 is a block diagram of the essential components and connections for one embodiment a control device for a vending machine according to the present invention,

F ϊ g. 2 shows a detailed circuit diagram of the programmable clock generator of the control device according to FIG. 1,

Fig.3 is a detailed circuit diagram of the parts of the Embodiment according to FIG. 1, located in the part of FIG. 1 outlined by the dashed line and provided with the reference number 10. 1 are located,

4 shows a detailed circuit diagram of the reimbursement facility, the payout facility and the Sales control of the control device according to FIG. 1, and

F i g. 5 a diagram of FIG. 4 corresponding circuit diagram for a vending machine in which two or more different sales prices can be used.

In the figures, the part of the control device is provided with the reference numeral 10, which completely is integrated, so is present on a single chip The part of the control device that is in the with The dashed lines bordered area 10 is for the two described embodiments of the The present invention is identical, that is to say for the embodiment shown in FIG. 1 to 4, with only one Fixed selling price is used, as well as the embodiment according to Figure 5, in which two or more different purchase prices can be used.

The essential, in the following described in detail components of the control device for a Vending machines according to the present invention are: a programmable clock 12, also known as "Clock circuit" is to be designated; an adder and storage circuit 14, hereinafter also referred to as Accumulator as well as sometimes called A-counter; a comparator 16, so one Comparator circuit; a locking device 18; a second adding and storing circuit 20 which is im also refer to the following as accumulator or ß-counter: will; a price coding circuit 22; an output decoding circuit 24; a refund circuit 26; a payout device 28 which also referred to as a "withdrawal control circuit"; and a sales control circuit 30.

In the case of the in FIG. 1, the circuits 14, 16, 18, 20 and 24 are a single control device integrated circuit summarized, for example, located on a single chip; this Circuit part is provided with the reference number 10.

Programmable clock circuit

The programmable key circuit 12 provides one corresponding number of pulses for the credit or credit input signals, which are sent by a coin unit or other similar input device, e.g. B, a coin validator; input units also belong to these facilities who are able to buy coins, tokens, Paper money, credit cards and other similar ones to include means of payment representing a certain monetary value. The credit or credit input device is only indicated generally by the number 32

to and has a plurality of output connections which are connected to corresponding inputs to the programmable clock circuit 12. In the figures are the inputs to the clock unit with 34,36,38, 40, 42 and 44 designated In practice, the Input connections between the credit unit 32 and the programmable clock circuit 12 through various types of links, using, for example, electrical connections, magnetic connections, optical couplings, etc.

μ can be.

Is applied to input terminal 34 oj) input signal received, the programmable clock circuit provides an output pulse which occurs on an output line 46 which is the A output line This The output signal can be a dime, a five-cent, or any other basic unit for that Represent the credit of a buyer, including basic units in foreign currencies. As soon as an input signal is received on the input connection 36 is, on the output line 46 of the clock circuit 2 output pulses generated twice the Represent the basic unit. Similarly, an input signal on input line 38 produces three output signals on output line 46 of the clock switch device, one input signal on input connection 40 produces four output signals on the output line 46 of the clock circuit, an input signal on input line 42 produces five output signals, and an input signal on input line 44 of FIG Clock circuit generates ten output pulses on the Auspangsleitung 46. Of course, if necessary, a larger or smaller number of combinations are supplied by input and output pulses of the clock circuit. The one on line 46 at The output pulses of the clock generator that occur in the circuit shown are always available if another input to the programmable clock circuit 12, namely an input on the line 48 (this input can therefore be the delivery of a Cause output signal), a specific state, such as. Legs:! Low voltage state, has If the input on line 48 has a "high." State «or a high voltage state there / in the clock steps or * clock pulses from the programmable clock circuit 12 output via a further output line 50, which is referred to as a 0 output line.

The programmable clock circuit 12 has further input lines which act as payout inputs 52,54 and 56 are indicated; these inputs can be used to send one, two or five pulses generate, which then each display the Tax change. In the case shown, the numbers 1, 2 and 5 respectively represent the payout of

μ represents one-cent pieces, five-cent pieces and 25-cent pieces. These entries are with other digits in of the circuit which will be described later. The programmable clock circuit 12 is used

So as a controllable pulse generator, the input pulses receives when coins or other forms of currency are inserted into the vending machine or entered in any other way; the pulses correspond to the value of the entered Means of payment; furthermore, the clock circuit 12 contains an arrangement which is responsive to other devices, which control the amount of money by determining the value of the coin, which is returned for each amount entered is to be repaid, which exceeds the price of a selected item, can continue to the entire amount entered will be refunded or refunded if a buyer after the Entering a certain amount for any reason decides not to proceed with the purchase. This can e.g. B. happens when the customer after entering part of the amount to be paid his Changes mind when he finds that he does not have enough money with him to make the purchase he is looking for perform when he has to find that the Vorral of the product he wants to purchase in the Vending machine is used up, or if for any other reason he decides that the deposited amount is to be repaid.

In addition to the above-mentioned connections to the programmable clock circuit, the Clock circuit has a further input 58. which serves as their reset input. Is available at this entrance high signal, so if it is held high, it prevents any clock pulses programmed and / or generated. A control circuit such as B. a control circuit for a Vending machines with a programmable clock circuit such as the clock generator 12 are extremely beneficial Versatile, adaptable and flexible arrangement for the amounts deposited and refunded to control and always keep track of them; the parts of this control circuit can dem Use with any known existing coin system as used in the world today will be adjusted.

Counter and comparison circuits

The, 4 counter circuit 14 receives as above mentioned, input from the programmable clock circuit 12 on line 46. These pulses from the clock circuit are applied to one connection of an AND gate 60, the output of which is connected by a line 62 to the input or the counting connection of the counter 14. The counter 14 has a further output terminal, which bears the reference numeral 64 and through a further line 66 is connected to the other input of the AND logic element 60 at the output terminal 64 a signal is generated whenever the count in the counter 14 has any before certain, maximum count, such as B. 31 reached in the illustrated FaIL. A count of 31 is the maximum possible count for a five-level binary counter and is achieved by the possible counter readings for the levels of 1, 2, 4, 8 and 16 can be added. If a count of 31 is reached, a signal at the output terminal 64 and is on of line 66 to prevent the AND logic element 60 sends the output signals generated by the clock circuit 12 to the -4 counter 14 can give. This will add another summation beyond the limit imposed by the binary Computational technology, avoided, which would otherwise lead to a loss of 31 counting units or incrementally Credit increases would result.

Price coding circuit 22 is used to determine whether the credit sum s is sufficient for a specific purchase determined, which is so constructed and connected that via its input lines 68, 70, 72, 74 and 76 of the Amount of a selected purchase price directly into selected binary levels of the β-counter circuit 20

ίο is implemented or transferred. The lines 68 to 76 encode one, two, four, eight and sixteen step-by-step in the respective stages of the counter 20 Increments or any combination of these values. Furthermore, the respective Stages of the counter circuit 20 with the locking circuit 18 and from there with corresponding inputs of the Comparator circuit 16 connected. In addition, the counter 2Ö has an input that connects to the output of the programmable clock circuit 12 on the output line 50 of the clock is connected.

The comparator circuit 16 should be the binary complement (inverted or reversed amount entered) from the counter circuit 14 to the binary amount in the corresponding, at the output connections of the Counter circuit 20 present stages add up, so that there is a binary summation of these two amounts results. This summation appears at output terminals 78, 80, 82, 84 and 86 of the comparator circuit 16. The output signals appearing on these lines are fed to the decoding circuit 24 and therein as the difference in increase between those stored in counters 14 and 20, respectively Amounts shown.

The blocking circuit 18 is a logic circuit and is used to store the values in the memory or counter 14 to decode stored amounts regardless of the state of the counter circuit 20. The blocking effect occurs whenever the input to interlock circuit 18 is high. the

The input line to the blocking circuit 18 is 88 and, like another line 90, is shown grounded with a further control input the comparator circuit 16 is connected. Either or both of these compounds can be used at Need to include additional arrangements so that their input signal is large under certain conditions and other requirements (not shown) for the design of the vending machine are met. the Comparator circuit 16 also has a polling output line 92 on, which is at all times with the exception of the times at a low Level is when the amount stored in the counter 20 is greater than that in the counter 14 stored amount is. In the present circuit, according to a preferred embodiment, the Counters 14 and 20, the comparator circuit 16, the blocking circuit 18 consisting of logic elements, the decoder circuit 24 as well as the internal associated connections all in a single, relatively small one

μ and compact, formed by integrated circuits Part or element included. The details of these circuits are shown in the figures and are intended in detail in connection with FIG. 3 to be described.

- decoding circuit

The decoding circuit 24 is at the output of the comparator circuit 16 and generates output signals,

which control the operation of certain other circuit parts and arrangements including devices on the vending machine. As discussed above, decoder circuit 24 has a plurality of input connections, some of which are connected to output lines 78 to 86 of comparator circuit 16; In addition, the decoder circuit has an input connection to the carry output line 92 from the comparator circuit and a plurality of output lines 94, 96, 98, 100 and 102. These lines go low when active. The output line 94 always goes over to a low level (potential) when the M counter 14 has stored an amount that is exactly equal to the amount. which is stored in the β counter 20. The * is represented in the figure by the term A - B near line 94. on

L / LM / UILI '

aiiiiiitiii TTtI ^ t gtiii uit »j ^ atiitnahm ciui

Output line% always to a low level (potential) when the in the counter 14 stored amount is one or more increments greater than the amount. that in the counter 20 is stored; the voltage on the output line 98 then always goes low. if the amount entered into the counter 14 is two or more increments greater than the amount in the counter 20 is; the voltage on the output line 100 goes low whenever the in the counter 14 the amount entered is three or more increments greater than de: the amount in the counter 20; and the tension on line 102 then always assumes a low level. when the counter 14 is five or more Contains increments than 20 entered into counter. Only one of the decode output lines 94. 96, 98, 100, or 102 may be at a low level at some point, where di < highest observed difference in increase between the amounts entered in the counters prevailing and becomes determinative. Therefore the following applies: Is there such a condition. that the output signal on the Line 102 has a low level, this will prevail and take precedence over possible ones have low levels which may also be on the other three output lines 96, 98 and 100; this selection applies in a similar way to the other lines.

The decoder circuit 24 has two further connections for blocking input signals, one of which is a blocking input signal as "two or more inputs" Lock signal is described as being on one line 104 while the other as "five or more Inputs «lock signal is described, which is on a line 106. Is one of the lines 104 or 106 due to the closing of a respective empty coin switch 108 or 110 to a low level, so they operate to prevent output lines 98 and 102 from entering the decoder circuit Be put into operation; they also control another output line of the decoder with the next highest increase difference so that it takes control. In the case of the Circuit is the output line 100 of the decoder, which is the output line of the decoder for three or more more increments is independent of the other output lines of the decoder, so this Line is not connected in the present circuit. This is because according to the Representation the circuit is primarily switched in such a way that it can be used in a currency system such as the United States of America can be used with an increase of one step or one Increment a five-cent piece, two increments a ten-cent piece and five increments a quarter Dollars, i.e. a 25-cent piece. In a monetary system in which different combinations of increment values are used, it may be necessary to use line 100 as well and provide another associated interlock input connection. In such a case it can too It may be necessary to build in an additional coin switch that allows the different values of the coins is equivalent to.

Sales control

C ^ UoIt, me "6

driven by signals that it receives on a line 120, which serves as the output line of an AND logic element 122. The AND gate 122 has two input connections, one of which is connected to the carry output 92 of the comparator circuit 16 and the other to the input of the β counter 20, which receives a signal each time the counter 20 has stored an amount . which is greater than zero. The counter input signal to the AND gate 122 is on a line 124 and is an indication of the presence of a coded price. A carry output from comparator circuit 14 on carry output line 22 indicates that / 4 counter 14 has stored an amount that is at least equal to the amount stored in counter 20. If these two conditions are present at the same point in time, the AND logic element 122 generates an output signal which activates the sales controller 30. The sales control 30 supplies output signals which characterize the product selection and are given by a further AND logic element 126 to an output line 128 (see FIGS. 1 and 4) of the logic element. The AND gate 126 has three inputs, one of which is the same as that. which is connected to the input of the AND gate 122 via the line 124: the second input is on a line 130, which is an output line of the circuit 30 for the sales control. while the third input is on line 94, which is the output line of decoder circuit 24 if counters A - Bm are equal. AND logic element 126 emits a signal whenever β counter 20 has not formed a sum, so that on the line 124 a signal is present, and if at the same time the Λ counter 14 contains an amount which is not equal to the count display in the ß counter 20. as indicated by the signal on line 94. If the circuit 30 for the sales control is activated by the receipt of an input signal on the line 120, it triggers a delivery function for the purchased item and also causes the refund control 26 to be blocked. The reimbursement is blocked in that an output signal is generated in the sales controller 30, which output signal is sent to the reimbursement controller 26 via a line 132. In this way, the control circuit 28 for the payout is also controlled by a circuit which contains an OR gate 134 which has two input connections

having; one of these receives output signals from sales control circuit 30 on line 136 while the other input from refund control circuit 26 is received on line 138. If one of the two input signals for the OR gate 134 is present on lines 136 or 138, the OR gate 134 generates an output signal on its output line 140, which is sent to the control circuit 28 for the payout and controls it. The Rückerstattungsäteuerschaltung 26 and 28 both have Aijszahlungssteuerschaltung Riickstelleingänge that for resetting the output line 94 of the decoder circuit 24 in case of equality A - B are connected. In addition, the refund control circuit 26 has a switch-operated control input 142 which is connected so that it is put into operation by actuation of a refund switch 144. The refund control circuit 26 also has a blocking output line 146 which is connected to a blocking input of the sales control circuit 30. This connection such. B. the inhibit input signal provided by signals on line 132 prevents the vend control circuit 30 from operating and making a vend when the refund control 26 is actuated. The same applies in reverse when the sales control circuit 30 is first put into operation. The details of the refund circuit 26 are shown in Figures 4 and 5 and will be discussed later.

The circuit 28 for controlling the payout has input connections which are connected to the output lines 96, 98 and 102 of the decoder circuit 24, respectively. In addition, a further, additional input connection from the sales control circuit 30 on the line 148 is provided. This last connection is used to reset the payout control circuit 28 when the vend control circuit 30 receives identical inputs from the counter circuits 14 and 20 indicating equality. This is indicated in the drawings by adding Rab. The sales control circuit 30 has a second output connection to the circuit 22 for the price coding. This is an optional special connection which, as shown, contains a line 150 and an AND logic element 152 (see FIG. 1). This connection is always put into operation when additional arrangements for price coding are required, such as B. is the case when the vending machine is to deliver items with more than one selling price.

Payout control

The circuit 28 for the disbursement control monitors the disbursement of coins to the customer, wherein the coins are dispensed in amounts determined by the total or the stored value in the counter 14, which goes beyond the set sales price; the amounts are in the The number of coins to be paid out is coded by signals transmitted to the circuit on lines 96,98 and 102 receives from the output of decoder circuit 24 For example, a signal on line S5 causes the Payment of a coin with the value of one increment, a signal on line 98 causes the Paying out a coin with a value of two

Increments, and a signal on line 102 will result in the payout, "coin having a value of represents five increments. When each coin is paid out, the programmable clock circuit 12 is actuated to apply a corresponding number of pulses to the counter 20. The connections between the payout control 28 and the clock 12 take place via lines 160, 162 and 164, each with the input lines 52, 54 and 56 of the clock are connected. Line 160 serves as a line at an increase by one step, that is to say with one increment, the line 162 as the line for two Increments and the line 164 as a line with five increments, where in the illustrated circuit I, 2 and 5 represent five-cent, ten-cent, and quarter dollars, respectively. Step on one of these Lines output signals, the clock circuit 12 is energized by a corresponding number of To generate output signals on clock circuit output line 50 which connects to the counter 20 manufactures. At this point in time it is possible to feed pulses to the counter 20 via this connection, because the input line 48 on which the control input signal for the β counter to the clock generator 12 is below Control of the connection from the output control connection 166 to the payout control circuit 28 is brought to a high level.

While the payout process is being carried out, the clock pulses are fed to the counter 20 and not to the / V counter 14; This operating sequence is continued until an amount is added up and stored in the counter 20 which is equal to the amount stored in the counter 14. These two amounts are represented in binary form as mentioned above. If this occurs, an output signal indicating equality appears on the output line 94 of the decoding circuit, with the result that the voltage on the line 94 assumes a low level. It is then possible to reset the payout control circuit 28. This also sets up circuitry to reset counters 14 and 20. The A counter 14 is reset via the line 168 which is connected to an output of the payout controller 28. The β-counter 20 is reset by a further line 170 which receives output signals either from the refund circuit 26 or from the payout control circuit 28. A line 170 is connected to the input for the reset control of the β-counter 20. At the same time, the output line 94 of the decoding circuit indicating the same thing gives a further reset signal to the reset input of the circuit 30 for the sales control. This reset signal is input via a further line 171 when the purchase time has elapsed. If the circuit 30 for the sales control is reset, the signal on its output line 148 assumes a low level; as a result, the resetting of the counters 14 and 20 via the payout control 28 is blocked until the purchase time is over. As will be explained, the reset output generated on line 94 indicating the equality (A = B) is also used to reset the refund controller 26.

Refund Control

The refund controller 26 is shown in detail in FIG. 4 shown and is used in the inventive

Control circuitry to repay in full to a customer or purchaser any deposited amount or amount of memory held in counter 14 so long as its inhibit input is not present on line 132 from sales control circuit 30 to prevent a refund. In order for the reimbursement facility to be able to operate, there should be no signal on the equality-indicating output line 94 of the decoder circuit 24 which corresponds to the equality. If these conditions are met, the buyer can initiate the refund at any time by actuating the refund switch 144. When the refund switch 144 is triggered, the refund control circuit 26 disables the operation of the sale control circuit 30 by a signal generated on the disable output line 146; At the same time, the refund control circuit generates an output signal on the line 138 which is fed to one of the inputs of the OR gate 134 and to the input of the payout control circuit 28. The excitation of the reimbursement control 26 also generates a further output signal on the line 174, this output signal being sent to an OR logic element 172 and from there to the reset input of the counter 20 , as has already been described. If these conditions have been set by the operating sequence of the refund control 26 , the payout control circuit 28 is set in order to control the payout of coins until the 5-counter 20, which is now starting an operating sequence in its reset direction, is brought to a count which is equal to the count that is stored in the counter 14. If this state is reached, an output signal indicating a low level occurs on the output line 94 of the decoder circuit 24 , which indicates the equality, thereby to the refund control 26, the payout control 28 and in turn the counters 14 and 20 in sequence, as mentioned above to postpone.

So far, the structural and operational details of the circuitry of the invention only shown in broad outline, with a detailed description should now follow. Of course many of the circuits and components, including the counter, the comparator circuit, the Locking device and the decoding circuit, as integrated circuits in miniaturized form Assemblies are combined; this can be done by removing all of these and other circuit elements integrated in the same block or chip or in different blocks or chips Circuits are arranged. This allows the same basic building blocks to be used to create Make control circuits with different capabilities and connectivity options; this includes Circuits that can be operated at one or more purchase prices, circuits, at where repayments are made in one or more different coin denominations, including the repayment with the smallest possible number of coins, further circuits with which a full refund can be made, and circuits with which based on the Price for a selected purchase item! the coverage amount of each entered amount is determined for repayment purposes. As far as known is, none of the conventional control circuits has these diverse possibilities, so that this circuit and their construction represent a new generation of control circuits for the stated purposes. The now The following parts of the description explain the structure of the circuit and the operating characteristics in detail the more essential components of the switching arrangement. This includes a description of a switching arrangement for a device with a fixed, specific price (Fig. 4), as well as a switching arrangement for a device

in with two or more prices (Fig. 5).

Fin / finesses of the programmable clock circuit

The details of the programmable clock circuit 12 are shown in FIG. 2 of the drawings. The clock generator 12 shown contains a four-stage binary counter 179 which is constructed from four flip-flop circuits 180, 182, 184 and 186 of the D-type. These flip-flops are clock-controlled by an oscillator circuit 188 which contains a NOR gate 190, an inverter 192, a resistor 194 and a capacitor 1%, which are connected to one another in the manner shown. The oscillator circuit performs clock control whenever the input signal on its input line 198 is low. The input line 198 of the oscillator is the output line of an OR gate 200 and assumes a low level each time the OR gate 200 is on one of its two inputs 202 and 204

in has a low level. An input line 204 to the logic element then always has a signal with a high level. when the binary counter 179 of the clock circuit is reset and a signal with a low level is applied to each input of the OR

Si link 206 caused. The inputs to the ι OR logic element 206 are each connected to the <? - output terminals of the binary stages 180, 182, 184 and 186 . As a result, a signal with a low level is generated one after the other at the corresponding input to a further NOR logic element 208 on its input line 210 .

If a signal is low on input line 34 of the clock, it will be a one of the two input signals to an AND link

link 212. 'n, whose exit with a

a multitude of vol. inputs 214 of a further AND logic element 215 is connected. These conditions have the consequence that the output signal of the AND logic element 215 on the line 216

5 »goes high. Since the line 216 is one of the two inputs of the OR gate 200 when the signal on the line 216 has a high level, this has the consequence that the operation of the clock is blocked. While the input signal on line 214 has a low level, the same signal with a low level is simultaneously also given as an input signal on further input lines 218, 220, 222 and 224 from individual NAND gates 226, 228, 230 and 232 , the outputs of which are each given a SET -Input (set input) of one of the clock flip-flops 180, 182, 184 and 186 connected. If these conditions exist, the result is that the logic elements 206 and 208 transmit a signal with a low level to the NOR logic element 200 via the input line 204 .

when subsequently the signal on clock input line 34, which is the clock input line programming a clock pulse, is high

When the level returns, the input signals to the logic device 200 on the input lines 202 and 204 cause a signal with a low level to appear on the input line 198 of the logic element 190, so that the clocking circuit 2 can oscillate due to this state of the input line. Another NOR logic element 242 is connected to the oscillator circuit, two of its three input connections 244 and 246 being connected to the input lines 202 and 204 of the connection element 200, respectively. If signals with a low level are present on these input lines, the output connection 248 of the logic element will clock and continue until all inputs to the OR logic element 206 have a signal with a low level. This will occur in the case shown, in which there is an input signal on the input line 34 of the clock generator after a clock pulse because in this state it is the next binary state after the set state of the binary circuits 180 to 186

Similarly, if a pulse train of ten pulses is required, a signal J with a low level will temporarily appear at the clock input 14 instead of at the clock input 34; this will start the clock circuit with a previously set count display of 6, as set by the signals on the input lines 250 and 252 of the NAND Verlud '.pfungsglieder 228 and 230. For this state, the oscillator circuit must clock ten pulses until the output line 204 of the logic element 208 changes its state. During this Tsktstcucrung the first binary stage 180 of the counting 179 of the clock receives input signals on the line 254, which is between the output of the logic 3; fungsglicdes 242 and the £ X input of the first flip-flop stage 180 is connected to the output line 46, which is the line. which connects clock circuit 12 to counter 14 when there is a low level signal on control input connection 48 from output line 166 of payout control circuit 28. If a signal with a high level instead of a low level is on the B control output line 48, the output signals of the clock generator 12 are instead assigned to the 4; B-counter 20 passed via line 50.

If the binary clock stages 180, 182, 184 and 186 are set to a count reading below 16, which is the reset count reading, the clock will provide an output signal equal to the number of pulses that exist between these two states. For example, setting a count display of 11 will require five clock pulses to reach the sixteenth or reset pulse state. As soon as a high level signal is applied on the reset line 58 for the clock, the result is that the four binary stages 180, 182, 184 and 186 of the clock circuit 179 are reset even if the clock does not complete its normal operation has finished. This is to prevent any output signal from being generated on the output connection 256 of the NAND logic element 258 in the output of the clock generator 12 (FIG. 2). This is because. that the NAND gate 2 * 58 receives a signal with b> low level at its other f-input 260, which is connected to the reset circuit. This connection contains an inverter 262, the input side of which is connected to the input connection 58 for resetting the clock. The line 58 for resetting the clock is also connected directly to all reset inputs of the binary stages 180, 182, 184 and 186 of the clock. The AND gate 212, which is connected to the input 34 of the clock generator, as well as other, similar inputs of the AND gates 264 and 266 in the circuits for credit entry of the clock 12 are connected to one, two or five incremental or incremental inputs of the clock circuit 12 connected; these logic elements are provided in order to provide isolation for the respective credit input signals and also for the associated input signals to the clock generator from the payout circuit 28, which are received on lines 52, 54 and 56. A preferred embodiment of the input circuit 32 for the credit is shown in FIG. As shown in Fig. 2, the credit entry circuit 32 includes a coin operated switch 270 which is convertible from engaging a normally closed switch contact 272 to engaging a normally open contact 274; if this happens, a capacitor 276 can be charged relatively slowly through a circuit which contains a resistor 278 with a relatively high resistance value. Due to the action of the switch 270, another capacitor 280 can change its state of charge so that its charge equals the charge of the capacitor 276 will. Subsequently, when switch 270 returns to its quiescent state in which it is engaged with normally closed contact 272, capacitor 276 rapidly discharges through another resistor 282 of relatively low resistance to keep the current within the limits of coin switch 270. The rapid discharge of capacitor 276 causes a temporary low level signal to appear on output connection 284. The duration of this temporary low level signal is controlled by the resistance of another resistor 286 and also by the action of capacitor 280 The specific shape and the particular construction of the credit input circuit 32 as shown in the figure has been selected for purposes of illustration only, since numerous different types of credit input circuits can be used to operate the programmable clock circuit 12 in a pulsating manner.

Details of the counter, comparator and decoder

F i g. 3 shows in detail the circuit of the counter 14, the comparator 16, the blocking circuit 18, the counter 20 and the decoding circuit 24. According to the illustration, the counter 14 is a five-stage binary counter made up of five flip-flops 300, 302, 304, 306 and 308 is constructed of the O-type. The first flip-flop stage 300 receives the input signals to the circuit 14 on the line 62, which is the output line of the AND-logic elementfsOisliällc flip-flop? have backs! inputs connected to the reset line 168 from an output of the payout control circuit 28. Each of the flip-flop circuits, with the exception of the first flip-flop stage 300, also has a respective clock input 310, 312, 114 and 316, which is each connected to the previous stage of the counter. For example, the clock input signal becomes the while

Stage 302 is controlled by φ output signals received from the first stage 300, and so is the other stages in a similar manner. That means the following; If input signals are received, they are added and stored in the usual way for such counters. The accumulator circuit 14 also has an output OR gate 318 which has a plurality of inputs, each with each Q output of the counter stages 300 to 308 are connected; the logic element 318 has an output 64 on which a signal with a low level is only present when all five stages of the binary counter are in the state of their maximum count display; this only occurs when the counter has totaled 31 and stored it

each stage 300 to 308 of the accumulator 14 has a respective (^ output terminal 320,322,324,326 and 328; the combined signals present at these terminals represent the binary complement of the summation in the counter 14. The Q outputs are connected as explained above; in addition, they are each connected to a full adder or summing circuit 330, 332, 334, 336 and 338 which are part of the comparator circuit 16. The following truth table shows how the comparator circuit 16 uses the binary numbers which it receives from the five stages of the Counter 20 receives, subtracts from the input signals it receives from the five stages of counter 14 by adding the complements of counter 14 (sum of the ^ outputs) to the Q outputs of counter 20. The complement of the result S is binary Difference.

Allocation table 1 2 4th 8th 16 = 1 1 1 0 0 = 7 A. = 0 0 0 1 1 = 24 Ä = 0 1 0 0 0 = 2 + B = 0 I. 0 I. 1 = 26 S. = 1 0 1 0 0 = 5 S.

The counter 20 thus has five as shown Levels 340,342,344,346 and 348 so that the number of Steps is the same as for counter 14. The individual stages of the counter 20 can be set directly by input signals which are received on the respective input lines 68, 70, 72, 74 and 76; these Stages are clock-controlled by input signals that are received on the ö counter input line 50, and are reset by input signals either from the recovery control sound 26 or received by the payout controller 28. The reset pulses are generated by the OR gate 172 at its output 170 fed, each stage of the counter 20 also has an ^ • output, the individual outputs each identified by reference numerals 350, 352, 354, 356 and 358. Occurring at these outputs Signals are generated by respective NOR linkage m> members 360, 362, 364, 366 and 368 reversed and inverted, respectively; therefore, the NOR gates provide non-inverted binary output signals from the Counter 20. These output signals are respectively applied to adding circuits 330, 332, 334, 6 and 338 in the sequence Comparator circuit 16 given in a similar manner, how the Kingangssignalc are given to the adding circuits from the Λ counter 14.

The barrier input line 88 to the barrier circuit 18 is as shown in Figure 3 with a second Input of each of the NOR gates 360-368 connected. If there is a signal on this input with a high level, this has the consequence that a signal with a low level at the respective outputs 370, 372, 374, 376 and 378 of the logic links; this triggers a blocking function between the B counter 20 and the comparator circuit 16 This would prevent the comparator circuit 16 from receiving signals from the B counter 20.

The comparator circuit 16 contains a parallel carry circuit part 380, the "carry-out" - Control signals on the "carry-out" line 92 delivers Does the signal on the "carry-off" line 92 have one low level, this means that the binary count in dsm B counter 20 is not greater than that binary counter reading in the / l counter 14. The "Öuertragaus" line 92 is a signal with a low as long Levels lead, as the counters are in the same state or in a state in which the .4 counter 14 a has stored a larger total value than the B counter 20. The comparator circuit 16 also has a "carry-on" line 382; is on this line usually a low level signal; this line is used as an additional control parameter for others, possible use cases foreseen in the future; she can z. B. in devices with another Basic structure can be used, which offer additional operating options.

The circuit of the B counter 20 includes another AND gate 384; this logic link has a multitude of input connections that are each connected to the (^ outputs of the stages 340 to 348. A signal is then always present at an output 124 of the logic element 284 low level, we; 1 there is any count in the B counter 20. In other words, delivers the initial signa! the AND gate 384 an indication that the B counter 20 a Has a count that is greater than zero; this output signal is sent to the price coding circuit 22 and applied to the sales control circuit 30 as mentioned above.

The decoding circuit 24 (see FIG. 3) is intended to supply the complement of the sum of the output signals of the counters 14 and 20; this is achieved in the decoding circuit with the aid of inverters 286, 288 and 290 as well as NAND gates 392 and 394, which are connected to one another in the manner shown. The output signals of the decoder circuit 24 are on the output lines 94, 96, 98, 100 and 102; these output signals indicate the various relationships that exist between the values accumulated in the A and B counters 14 and 20, respectively. These conditions are indicated by having a low level signal on the respective output lines. For example, if the amount stored in the / 4 counter 14 is equal to the amount stored in the B counter 20. thus the output signal on output line 94 of the decoder will be low and the output signals on the other output lines of the decoder will be high. From the same point of view, the following applies in a similar manner: If the amount stored in the counter 14 is greater than the amount stored in the fl counter 20, the output signal on the output line 96 becomes a low level

to have. If the amount in the 4-counter 14 is two, three and four increments greater than the amount in the S counter, the output signal on output line 98 will be low. Becomes a Coin tube switch such as Z, B, the coin tube switch 108 for the ten-cent piece is closed, so this indicates that the pipe is empty; then a low level signal is generated on line 104 which corresponds to the Line 396 is connected; this causes the output on line 98 to be disabled. Does the Counter 14 has a carry of three or more increments compared to counter 20, so will the output on line 100 will go low to indicate this condition. These Condition represents one of the possible, available states, but is used in the circuit shown not used; however, it could be used in particular if the Circuit would be adapted to other coin systems. If the Λ counter 14 has five or more increments more than the B counter 20, the output signal on line 102 will go an iron low level, if not at this point the switch 110 for the empty tube with the quarter-dollar pieces is activated, thereby placing a low signal on connected lines 106 and 398 and on the Input to the logic element is generated, which is to the> 5 line 102 belongs to

The decoding circuit 24 has further connection and switching options which are intended to prevent certain output signals from occurring. Has z. If, for example, the signal on output line 98 is low, this prevents the signal on line 96 from assuming a low level associated link, as will be explained later. Correspondingly, the following applies: As soon as the output signal on line 102 is low, it prevents the output signals on lines 96 and 98 from going low due to signals on line 402, line 402 being the output of the to output line 102 Associated link with the inputs of the links that are assigned to the outputs% and 98. The result of this is: If there is a low level signal on the blocking> 5 line 398, the> 2 output signal on the line 98 will assume a low level for each count value in the Λ counter that is two or more ( 5, 6, etc.) is greater than the amount that is stored in the β-counter 20. Similarly, if both inhibit input lines 3% and 398 are low at the same time, the signal on the> 1 output line 96 will go low for any count in the I counter 14 that is one or more increments greater than that the amount in the ß-counter 20 is as soon as a five-increment coin such. B. a quarter of a dollar is not available for repayment or refund, the m> circuit, as shown, indicates that instead a two incremental coin such as. B. a ten-cent stick should be paid back; are also ten-cent pieces are not available, then the circuit indicates that repayments should be made only in a μ Inkreme'it corresponding coins, namely five-cent Stückcn. It follows from this that the present circuit for any known coin system without taking into account the relative incremental values of the coins used can be used, although some smaller ones Changes to the connections may be required.

The decoding circuit 24 has a further inverter 404 which is connected between the output output line 92 of the comparator circuit 16 and the various output logic elements of the decoding circuit 24. E.g. is stored. The output signals on line 406 are applied to the inputs of a multiplicity of decoder-output gates which contain a NAND gate 408; this logic element is the gate which generates the output signals on the line 94 to indicate the state in which there is equality between the amounts stored in the counters 14 and 20. The state of equality is, as indicated above, by a signal with a low level indicated on line 94; this always occurs when the signal on the output line 410 of the NOR gate 412 has a high level due to a signal with a low level <vl on its input line 414. This is the case when the inverted or inverted output signal 5, on the Line 416 from the first stage of the adding circuit 330 indicates a zero state and if the other input signal to the logic element 412 on the line 418 as a function of the inverted output signals of the other adding circuit 332, 334, 336 and 338, which are used as input signals for a further NAND Gating element 419 occurs, has a low level. The output signal of the NAND gating element 419 is on the line 418 and on the connected line 420, whereby the state of the NAND gating element 419 indicates a zero state. Under these conditions, a further NAND logic element 424 will indicate this state and generate a> 1 function on its output line 96 in that a signal with a low level occurs when this is on a line 426 (which is connected to the output line 94 of the logic element 408 The output signal led to it has a high level, which indicates that no equality A = B is present , which is the> 1 logic element. The conditions just described also require that a further input signal to the logic element 424 on the line 428 has a high level, which indicates that the amount in the / t counter 14 is not less than the amount in the counter 20 that the signal on input 430 to logic element 424 has a high level. which indicates that there is no k5 state and that the signal on the other input line 432 of the logic element 424 also has a high level, which indicates that there is no> 2 state.

Another NAND gate 434 is provided at the output of the decoding circuit and the > 2 output line 98 assigned; this linking

function element provides an output signal with a low Level when (1) the signal on input line 436 is high, indicating that the Payer 14 has an amount that is not less than the Amount in counter 20, (2) the inhibit input on line 396 is high so that the Logic element is not blocked, (3) the signal on input line 420 from the output of the NAND logic 419 is high, and (4) the input signal it is on on a line 402 (output line 102) is also high, indicating that no > 5 state is present

Another, the> 3 output line 100 of the NAND gate 440 associated with the decoder provides a signal having a low level around the State> 3 to be shown. Although this state in the is not used, it is available and occurs when the logic element input on line 406 to a Time has a high level when on the other input line 442 of the logic element as well a high level signal is the line is connected to the output of the NAN D logic element 392. A signal is present on this line high level when the input signal of the logic element on line 444 due to operation another NAN D gate 446 which generates a high level output signal The inputs of the NAND gate 446 are each connected to the outputs of the Inverter circuits 386 and 388 are connected which produce inverted forms of the output signals of the adder circuits 330 and 332. The NAND gate 392 also depends on input signals which it then receives from the output of a further NAND logic element 448 in particular if signals with a low level are present on these inputs. The NAND gate 448 has direct Input connections to the outputs of adding circuits 334,336 and 338 which are the adders which counters 14 and 20 belong to the third, fourth and fifth stages, respectively.

Another NAN D gate 450 of the decoder is in connection with the > 5 output line 102 is provided. The NAND gate 450 then produces a low output on line 102 when (1) its input on line 406 is high, indicating that counter 14 has an amount the nick} saved is less than the amount the Stored in counter 20 is (2) a high level signal on inhibit line 398 so that it is not blocked, and (3) also has a signal on its other input line 452 The line 452 is connected to the output of the NAND gate 394 and always delivers a signal with a high level when the input signals to the logic element 394 from the Adding circuits 336 and 338 in comparator circuit 16 have a low level or if so other input on line 454 is low. The line 454 is with the Output of another NAND gate 456 connected, which has two inputs, one of which with the output of inverter circuit 390 on line 458 and the other on line 460 with the Output of another ,, NAND logic element The NAND gate 456 is connected will always provide a low level signal at output 454 when the output signal of the adder circuit 334 generated by the inverter 390 of line 458 is inverted or vice versa, one is high and its other input on line 460 from NAND gate 462 also has a high level. The NAND gate 462 provides a high output signal when

ίο either the output signal of the first stage serving adder circuit 330 or the output signal of serving as the second stage adder circuit 332 is low The in F i g. 3 control circuits provide a

is a high degree of adaptability and choice in its design and operation; Farther As illustrated, they can be used in a variety of different operational circumstances; this includes, for example, several different ones Purchase prices, different coin values, and a variety of choices in terms of the produced Outputs. These possibilities are evident in the circuit shown in that the control for the sales control device, the payout tax facility, the refund control facility and the other, associated circuits and switching elements are created.

Sales control details at a purchase price

F i g. Fig. 4 shows details of the circuit which is particularly designed for a vending machine control, in which only one price is provided In contrast to this, a circuit is shown in Fig.5 provides the control circuit for a vending machine ten is intended to serve with two prices and will be described later. The circuits according to FIGS. 4 and 5 also contain the details of the associated facilities for refund control and the Payout control. The sales control 30 is by the presence of a signal on its control input! gsleitung 120 controlled with the output of the UN D logic element 122 connected; st As already described, the AND Ver logic element 122 input signals from the transfer Output of the comparator circuit Ib, which is based on the Line 92 and, when the carry output signal is low, is used to indicate that the value stored in the counter 14 is equal to or is greater than the value stored in counter 20; the AND gate 122 also receives signals from the B counter 20 on the £> 0 line 124, which indicates that the B counter 20 has stored an amount greater than zero so that on a low level signal is generated on line 124.

The purchase price entered in the B counter 20 becomes introduced by price coding circuit 22 via UN D logic gate 126; on his exit Link 128 is always a signal with a high level when the value stored in the counter 20 is greater than zero. This condition is fulfilled when there is a signal on the decoder output line 94 is high, indicating that

fi5 Equality between those in counters 14 and 20 stored values / i is present, and if a signal mil high level is on a further input line 470 to the logic element 126. On line 470

If a high signal occurs iti depending on a wedge State which results at an inverter circuit 472 at the point in time when at the automatic vending machine (not shown) a selection is made. This change causes a current to flow from an input control terminal 474 (which is connected to the vending machine) flows to an electro-optical device to activate, which is shown as optical coupling device 476. The switch 476 is operating by a mode switch 478. which causes the signals on the input line 480 of an inverter 472 will be low at the time the output is on the line 128 of the logic element 126 goes high, whereby circuits are built up to the Enter the price in the Ä-counter 20. The real one Input is made by placing high level signals on designated lines 68-76; these

io was at a high level until the input signal to the logic circuit 506 on line 510 hoc! and stayed high until the low signal at output 492 allows capacitor 514 to discharge through resistor 516, capacitor 514 and resistor 516 are connected in parallel and between the base of transistor 5If and ground. Resistor 516 and capacitor 514 serve to operate transistor 518 in the forward direction and cause the input signal to logic circuit 50f on line 510 to go low.

Another AND logic element 520 is provided see to the y-ar flip-flop 490 through signals which is received on its input port 522 whenever the refund control 26 is set, or by signals received on its other input line 524

pn cinH 7WiVnPn Hip PrpislfnHiprcrhaltw.ia OJ u / prHpn u / pnn on ptnpr ΛιιςααπαςΙριΙιιησ

and the stages of the β counter 20 are switched. This> i> The sequence depends on the setting of a large number of switches connected to lines 128. These switches are indicated generally by the reference numeral 481, with their compound Adjustment states result in the sales price. > ■>

As described in pending U.S. Patent Application Serial Number 31 380 3 contain the elements belonging to the optical coupling device 476 circuit resistances 482 and 484, a capacitor 486 and a diode 488. manner as shown on the) _Π are interconnected. These elements and their interconnections enable the coupler 476 to vibrate or pulsate when a selection is made in the vending machine. The mode toggle switch 478 is shown in the drawing in a position in which stored amounts are paid back until a product is selected. If the operating mode switch 478 is moved to its opposite position, this has the consequence that the set m sales price is transferred to the counter 20 in the manner described, as soon as a y-Ar flip-flop circuit 490, also in the sales control circuit 30, is reset. If the / Ar flip-flop 490 is clock-controlled or brought to a low state by a signal on its control input a 120 from the logic element 122, the signal on its (? Output terminal 492 goes to a low level, whereby its y-input 494 and his / c input 496 also go low in order to prevent possible further clock controls of the flip-flop and to disable the refund control 26 by a signal appearing on the refund lock 132 (to keep its reset state low). The point in time of sale is the point in time at which a vend relay 498 is energized and its contacts 500, which are in engagement with a stationary contact associated with a line 502, are toggled and come into engagement with a stationary contact associated with a line 504 ; this time of sale is controlled by input signals or responses from the y-Ar flip-flop circuit 490 via lines 508 and 510 are passed on and through a NAND gate 506. The input line 508 is connected to the ^ output terminal 512 of the flip-flop 490 and has a high level signal as soon as the / -Ar flip-flop 490 itself changes to a high level a low level signal occurs. This state results in ¹ »if the signal at the input 530 to the logic element 526 has a low level after the point in time of the sale, and if the signal at its other input 532 also has a low level, which indicates that the the same counting display is present in the two counters 14 and 20. This occurs either when the stored amount equals the sale price. or if the payment of change, as added to the sales price entered in the β-counter, causes the amount stored in counter 20 to be equal to the amount stored in counter 14. If the amount stored in the counter 14 is not equal to the amount stored in the counter 20 after the time of the sale has passed, as is indicated on the line 510, the output signal of a further one connected to the line 510 goes Inverter 534 on line 536 high. This high level signal is applied as a control input to the OR gate 134 in the control circuit to the payout controller 28 and causes a high level signal to appear on line 140, which is the control input line to the payout controller 28.

If payment is to be made on the basis of a signal with a high level on the control input line 140, then a payout motor 540 energizes. This is done because then there is also a high level signal on the Input line 542 of a further NAND link. if the amount stored in the counter 14 is not equal to the amount stored in the counter 20 is. Because therefore the NAND gate 544 at this point in time signals with a high level at its has both inputs 542 and 140, a signal with a low level will appear at its output 548, so that transistor 550 is driven forward through zener diode 552. The zener diode 552 is in the base circuit of transistor 550 in series with a current limiting resistor 554 and with other series resistors 556 and 558 connected, which are connected to one another in the manner shown. The Zener diode 552 is used to isolate the motor feed and the logic circuit. A another resistor 560 and a capacitor 562 are in a circuit in parallel with the payout motor

540 connected in order to suppress the Moior noise. Resistor 558 then ensures that transistor 550 is switched off when it is not operated in the forward direction by NAND gate 544. The counting molor 540 is excited. so it will operate means to pay out one increment of "coin". However, if motor 540 is operated in conjunction with relay 564 , as will be explained later, it will pay out two increments of coins; if motor 540 in conjunction with one If further relays 566 are operated, it will pay out coins with a value corresponding to 5. The relay 564 used with 2 increments is energized when signals ι -, with a high level occur on the two input lines 570 and 572 of a NAND logic element 568 the input line 572 is then a high level signal when the input signal Gehl to an inverter circuit 474 on a line 576 to a low level. This occurs when a signal of>_(> low level on the> 2-line 98 .

The relay 566 for the five increments is energized when the NAND gate 578 on lines 580 and 582 has input signals with a high level. The input signal on line 580 goes high 2> during a payout due to a high signal present on the payout input control line 140 ; the signal on input line 582 goes high when a low level signal is on an _<η input line 586 of an inverter circuit 584 . Line 586 is connected to the> 5 output line 102 from decoder circuit 24.

The payout control circuit 28 has output connections 160, 162 and 164 which are connected to the respective y, input lines 52, 54 and 56 of the clock generator 12 , as shown in FIGS
is. The outputs from the payout control circuit 28 provide intermittent low level pulses which program the clock circuit 12 so that the m clock circuit will generate one, two, or five clock pulses at a time. The lines 160, 162 and 164 of the payout control circuit 28 are each connected as outputs of OR gates 588, 590 and 592 , which always deliver pulses when the 4, voltages on a line 594 under control of the operation of the payout motor 540 is low Assume level, with the payout motor 540 actuating a motor pulse switch 596 via a mechanical link. The temporary closure of -, switch 596 causes the output pulses appearing on line 594 to be generated by a pulse shaper circuit formed by resistors 598, 600 and 602 and capacitors 604 and 606. The pulse shaper circuit is similar to the pulse shaper circuit used in credit entry circuit 32 and described in conjunction with FIG. 2 will be described. If the signal on line 594 is clock-controlled to a low level, the OR gate 588 will deliver the clock-controlled output signal with a low level on line 160 for one increment if the> 1 output signal on line 96 is also at the same time is low. Similarly, OR gate 590 will provide an output lamp on line 162 when the> 2 output on line 98 is low; when the> 5 output on line 102 is low at one point in time. with a low signal on line 594 , a pulse on line 164 occurs. When the motor switch 596 closes, the capacitor 606 in the pulse shaper circuit discharges when each coin is paid out; This causes an inverter circuit 608 that a high level signal is produced on an output line 610, which is the flourSteuerleitung, which also bears the reference numeral 48 in FIG. I. This signal causes the clock generator 12 to send signals to the S counter 20 instead of the / 4 counter 14. Thus, a signal on the line 48 causes the clock pulses to be directed to the counter 20 during the payout operation. If the value stored in the β-counter 20 is then reduced to the amount which, during the payout, is equal to the value stored in the 4-counter 14 , a signal on the line 94 which represents this equality becomes a low Assume level, so that there is a signal with a low level at the output 528 of the logic element circuit 526 , which is located in the sales control circuit 30 . This low-level signal is connected to an input 612 of a further logic element 614 in the disbursement control circuit 28. If the signal at the other input 616 of the logic element 614 goes to a low level due to the state on the output line 140 of the logic element 134 , the output signal of the logic element 614 on the line 618 will go to a low level, so that the counters 14 and 20 are reset by signals which are on the reset output lines 168 and 170 , which are controlled by an inverter 620 and a logic gate circuit 622, respectively. These two circuits are temporarily clocked by a circuit that includes a capacitor 624 and a resistor 626 .

Refund Control Details

Referring to Figure 4, details of the refund control circuit 26 which is provided are shown. to return an amount that has been thrown in and added or saved if no purchase or sale is achieved. The reimbursements are made under the control of the operator or a customer operable reimbursement switch 144 when the movable switch contact is moved from its normal to its repositioned position. When the switch 144 is activated, a control input signal is thereby applied to an input line 630 of the jk flip-flop 632 , and the signal at this input goes high and then low. As a result, flip-flop 632 has a low level signal at its Q output 634 . This also keeps the signals at the j and i inputs 636 and 638 low, so that further changes in the state of the flip-flop are prevented, although additional changes on the input line 630 could occur. The barrier output line 146 provides blocking output signals from the reimbursement control 26 to the sale control circuit 30, to prevent the sale control circuit 30 is set during the refund activity. This is accomplished by holding the / -A-F! Ip-F! Op circuit 490 in its reset state by applying the low level signal on line 146 to the reset input 640 . A

Capacitor 642 and resistor 644 are also connected to the output circuit of refund flip-flop 632 to provide a low level signal to one of the inputs of logic gate circuit 622. The logic element 622 was described above in connection with the payout controller 28; its output line 170 is connected to the reset input R _{h of} the f1 counter 20. As already indicated, the payout controller 28 is controlled by a high level signal on the control input line 140, which is connected to the Q output line 646 of the refund flip-flop 632 through the logic element 134. If the payout controller 28 causes the counter 20 to have stored an amount equal to the amount stored in the counter 14. As stated above, an output signal will appear on line 94, this output signal being the signal for A = B ; this output signal is low and causes the refund control circuit 26 to be reset by a reset input signal which is applied to the reset input line 648 of the flip-flop 632. This signal is fed via a logic element circuit 650, one input of which is connected to line 94 and the other to line 132. It is then caused that the input signals on the two input lines 542 and 140 of the NAND gate 544 in the repayment control circuit 28 go to a low level; as soon as this happens, the repayment will be terminated.

Sales control details
(more than a price)

Figure 5 shows an alternate embodiment of the vending control circuit 30 of the invention in which more than one vending price can be used. Sales control lines 660 and 662 on the right-hand side of FIG. 5 supply input signals in order to monitor the selection in the vending machine and to apply a control potential which is available on a further line 664 for two different purchase prices. A purchase price is determined with the help of switches 666, 668, 670, bT2 and 674 and set in the device; these switches are located in a price coding circuit which is located in the lower left corner of FIG. 5 is shown; the other purchase price is set and determined in the circuit by setting another set of switches 676,678,680,682 and 684, which are also located in the price coding circuit 22. If a selection is made in the sales control circuit 30, a path results either from the sales control line 660 or from the sales control line 662, so that current flows from the line 686 through an optical coupling device 688 or 690 Resistors 692 and 694 limited and rectified by associated diodes 696 and 698. The current flowing through these circuits causes the corresponding optical coupling device 688 or 690, each containing a light emitting diode 700 or 702, to irradiate an associated phototransistor 704 or 706. In the drawing, the light emitting diodes 700 and 702 are separated from the associated transistor sections 704 and 706 of the same arrangements are shown. However, this is only intended to increase the clarity and clarity of the drawing; in actual construction, each diode is placed in the same package with its associated phototransistor. A price selection has been carried out and the

Ί the respective phototransistor 704 (or 706) is saturated (i.e. a highly conductive current path between its collector and its emitter), then clock pulses are sent to the clock input terminals 708 (or 710) of the respective 7-A ^- -FHp-flop circuit 712 and 714 given. this will

ίο happen as long as the withdrawal control line 140 is not activated or has a low signal. If this happens, one of the Flip-flops 712 or 714 put into operation and the other not; the one of them who has a signal

ii low level at its (^ -output 716 or 718 will cause the other, opposite flip-flop to be held in the reset state will. This is achieved with the aid of a circuit, the cross-coupled logic elements 720 or 722 contains. These links are intended to ensure that only one of the Sales relay 724 or 726 can be energized. Transistors 728 and 730 are in respective Output circuits of the y'-Ar flip-flops 712 and 714

2ϊ provided for the connection between the sales relays 724 and 726 and the associated (^ -connections 732 and 734 of the flip-flops 712 and 714.

The reset inputs 736 and 738 of the flip-flops 712 and 714 are activated by the logic elements 722

controlled in respectively 720, which for the necessary low Reset states as soon as the other, opposite flip-flop 714 or 712 receives input signals is switched on, which is connected to the respective input terminals 744 or 746 of the logic

J5 members occur at the times when a Output line 748 of a further AND logic element 750 has a signal with a low level.

The logic element 750 should always exert a reset effect in the reset circuit when a further optical coupling device, namely the optical coupling device used for resetting 756, is activated; this occurs during the issue of the item when the carry-out line 92 from the decoding circuit 24 receives a signal of high level. This happens again when the Λ counter 14 stores an amount which is smaller than the price stored in the counter 20, as well as when due to a signal a line, such as B. on line 758 in Figure 4, total reset or reset of the total he follows.

The vending control circuit 760 in FIG. 5 (lower right corner) is switched so that during the Delivery of an object current through the optical coupling device 756 and through a light emitting diode (LED) 762 can flow. Resistor 764 and diode 766 are in series with of light emitting diode 762 to control the magnitude and direction of current flow.

The light emitting diode 762 of the optical coupling device 756 is located in the same housing or jacket with a phototransistor 768. As soon as the selection of a particular item is carried out and the clock control of one of the y-Ar flip-flops 712 or 714 is effected, a line 770 given a signal with a high level with the help of an OR gate T / 2 , the inputs 774 and 776 of the OR gate

77? are connected to the Q output terminals 732 and 734 of the fiip-flops 712 and 714, respectively. The same high-level signals also appear at the respective input terminals 782 and 784 of wider AND gates 786 and 788 and cause a high-level signal to appear at the gate output 790 or 792 of the gates 786 and 788. The other input signals on lines 794 and 796 to the same gates are also high because they are connected to an output terminal 798 of an inverter circuit 800. The high level signal appearing on line 770, discussed above, is delayed somewhat by the influence of a capacitor 802, which causes the output signal of inverter circuit 800 on line 798 to go low at a somewhat later point in time, so that the The high level signal supplied to the price coding circuit 22 is temporarily clocked. The circuit just described also includes an OR gate 804, upon the input of which 806, under the control of signals received on the payout line 140, a high level signal is given to prevent any coding occurring during a payout.

If the purchase price is coded by the coding circuit 22 on the basis of a signal on one of the tier lines 790 or 792, an output signal will appear on the coding output lines 68 to 76 which connect the encoder to the ZJ counter 20. The stored or summed value entered into the λ> counter is then compared in the comparator circuit 16 with the stored or summed value in the / 4 counter 14; as a result, a clock output signal is generated on the control line 120 of the sales controller 30 if the amount stored in the counter 14 is equal to or greater than that in the counter 20. If the credit stored in counter 14 is insufficient to complete a sale, then the carry output signal on line 92 causes another line 808 (FIG. 5) to have a low signal around that of the binary Reset flip-flops 712 or 714 that triggered this process. However, if there is sufficient credit to provide the clock control of a further y-Jt flip-flop circuit 810 in the vending control circuit 30, the low-level signal at its Q output terminal 812 has the effect of causing a capacitor 814 to become through a resistor 816, resulting in a delayed line through an associated transistor 818 The signal with a low level, which is generated on the output side of the transistor 818, is also applied to an input terminal 824 of a further OR gate 826. The gate 826 in the circuit according to FIG. 5 is similar in structure and operation to the logic element S26 in the circuit according to FIG. 4. It also has similar ports and connections. The circuits belonging to the logic element 826, including the flip-flop circuit 810 and its connections and the associated circuit parts, are similar to the elements described above with reference to FIG. 4 were described.

If a signal with a low level is given to the input terminal 824 of the logic element 826, a signal with a low level is generated at the logic element output on the line 828. This happens as soon as a signal with a low level on the other logic element input line 830 to the logic element 826 which indicates that either the value stored in the two counters 14 and 20 is the same or that the value stored in the counter 14 exceeds the purchase price. The low-level signal generated on the output line 828 of the logic element 826 is applied to an input connection 832 of a further logic element 834 and used to reset the y-jt flip-flop 810. The flip flup 810 can also be reset by a signal which is fed on the line 808 if a signal with a high level occurs at the output terminal 92 of the comparator circuit 16 a low level signal appears.

A further logic element 836 is provided in the circuit assigned to the flip-flop 810 in order to to control the inhibit operation of the refund control circuit 26 based on a signal that this on the Line 132 is fed from the output of the logic element 836. This circuit is then available Available if on the Q output line 812 of the Flip-flops 810 have a low level signal while on line 770, which is connected to the input of a another inverter 838 is connected, a signal of high level is.

So that purchases or sales can be carried out with even higher purchase prices, only additional switches for the price coding as well as assigned circuit parts for the logic elements used for isolation and the sales control must be added, with all of these elements in a manner similar to that described above, with one another can be connected. Moreover, although the present invention has been explained using D-type flip-flops for counters 14 and 20, the same effects can be obtained using jk flip-FL * ^ for these elements - other bistable elements

can be achieved. Dii. .jmrnier- or storage device can also ring counters, shift registers, switching memories, counters that can count in both directions, and contain other binary storage arrangements. Furthermore, the facilities required for use were selected in the comparator or decoder circuit, as described, by means of exclusive-OR gates, symbolic or half adders and other conventional arrangements and techniques be replaced. The device for generating the pulse may be similar to that in the floating one American patent application, Serial Number 2,67,558 (Levasseur) is described on the Applicant of the present application has been assigned. Other suitable pulse generating arrangements are also already known and can be used. Furthermore, the types and Combinations of links and other elements, as well as their interconnections in some Cases significantly changed in comparison with the specific embodiments described here without the basic thought and the

29 30

Basic effects and operational processes, as they belong here to magnetic devices, are similar

are compiled and described. Can perform functions. In certain areas

Furthermore, for operational or cost reasons on the circuit described, however, the use

Some elements and features of the described formation of photodiodes are preferred because of the

Do without circuit: be. For example, the 5 types of signals they generate as well as the type of Refund control, the feature that the out signals that the circuit process and respond to

Counting takes place in several coin values, and can respond. These elements are also relative

Use of photodiodes by others, similar small, reliable and relatively maintenance-free. Arrangements are replaced to which electrical and

In addition 5 sheets of drawings

Claims (1)

Claims; 1. Control device for a vending machine with a clock that generates coin value pulses for a generated first accumulator, with a second accumulator for the purchase price of the goods, with a Comparator comparing the quantities stored in the two accumulators and with a associated with the comparator, the output of the goods only after entering a certain amount enabling locking device, characterized by the following features: