DE2432979C3 - Device working with mixed number representation for multiplying two complex numbers and adding a third complex number to the product - Google Patents

Description

according to claim 2, characterized in that ge ^ tensteuervornch

e
4. A component tax forecast

fr (F? g 7) contains: an exponent substitution (H g · η _{dhs nale (nu n) die}

blank circuit (73J ω _{u in G} , _eh .

S expressed complex as output

Ä ^ · ^{the absolute}

^V t is the difference between the exponents as well as the value of the L " ¹ " ^ "_signs; a form of an assigned sign ^^ ^ ^

arrangement 74.7S. / £ _accordingly

(.0

<> s w J

^has ; ^{U sl} t "n

m 78

«G coefficient

irwhen the sign signal has a did and a circuit arrangement generating exponent output

The second

Ss5ä

zeicnncu circuit arrangement

; ₇ ^U if the u ei ^ overflow condition signal (CMO) ll multiplier (20, responds and

lom

ien mil g
modify.

by dividing _e d multiples of their base number

The invention relates to a device of the type specified in the preamble of claim 1.

Convolution in the period can be replaced by multiplication of transformations in the frequency space will. Methods of this type are particularly suitable for the extraction of frequency components aperiodic waveforms using Fourier transform or Fourier analysis

proceedings.

By developing fast Fouricr transforms (FFT), the application of Fourier analysis to digital filter methods has become possible, see e.g. B. the publication of

R. Shi ve Iy, "A Digital Processor to Generate Spectra in Real Time," IEEE Tran, on Computers, May 1968, pp. 485-491. You can ζ. B. So separate a useful signal from an interfering signal by a real _ze j _t _DJgiialfilterung, and a known method ^ for this purpose is referred to as><Pipeline FFT "method, because the raw data are fed serially into a circuit arrangement and this in the Run through processing like a pipeline. In digital filtering, the input signals are sampled at specific data points, which represent the amplitude and phase information, and reduced to complex binary numbers, which are then processed further into weighted pulse function values. The processing takes place through ordered complex multiplication in combination with complex additions.

The input and output data can usually be represented by fewer binary digits than are required for the complex arithmetic operations in order to avoid a loss of counting digits. Binary numbers ("pipeline FFT numbers") with around 15 digits are therefore usually used for processing, which represents an acceptable compromise between accuracy and computing speed, and ² log N complex computing stages are required for N data points. If one works with fixed point representation in these stages, one needs a large number of bits to represent each value, while with floating point representation many additional functions are required, which practically negate the advantage of using a smaller number of digits.

The present invention is accordingly based on the object, in particular for the Implementation of fast Fourier transforms (FFF) and Fourier analyzes suitable device to create that is relatively easy to set up and still works quickly.

F i g. 7 is a circuit diagram of an exponent control device;

F i g. 8 a circuit diagram of a multi-point weighting or coefficient level and

F i g. 9 is a block diagram of a complex adder-subtracter.

The principal complex arithmetic processes in an FFT stage are illustrated by the butterfly diagram in FIG. 1 shown. For N sampling points, the complex operation is performed (N / 2) intrlog., / V) times. The term "int ⁽² log N)" means the smallest integer that is equal to or greater than ² log N. The input values of a single operation according to FIG. 1 are complex numbers Z ₁ and Z ₂ .

In the butterfly diagram according to FIG. 1 the following steps are shown: A connection of nodes representing complex values solid lines mean that the complex input value is multiplied by a complex one Constants, d: e in the circle of the end or output node. A connection between means a complex input value and an output node by a dashed line, that this complex input value is added to the resulting product.

In Fi g. 1, the node 10 means the complex value Z, with the polar coordinate representation

Z ₁ =

A _x exp (/ «,)

The node 12 means the complex value Z ₂ . which can be written as follows:

Z ₂ =

The complex constant W _k is equal to exp (/> \). the

According to the invention, this task by means of the 40 resultant nodes 14 and 16 signify the combined values Z and Z The complex

features specified in claim 1 solved.

Further developments of the invention are in the unclaimed claims marked.

The invention makes use, inter alia, of the from the publication ZAMP 4, 1953, Page 313, section a, known measure when adding two floating point numbers with different Exponents to adapt the smaller exponent to the larger one.

The device according to the invention enables such complex arithmetic functions to be performed at high speed to calculate, it is therefore particularly suitable for pipeline and other FFT systems.

In the following exemplary embodiments of the invention with reference to the drawing 5; explained in more detail. It shows

F i g. 1 a graphical representation of the complex arithmetic operations in an FFT-Slufe,

F i g. Figure 2 is a block diagram of a preferred one Embodiment of the device according to the invention <> manure.

F i g. 3 is a block diagram of a complex

Multiplier,
F i g. 4 a circuit diagram of a sign control

training.

F i g. 5 is a circuit diagram of a half adder, FIG. 6 a circuit diagram of a setting weighting

or coefficient acoustics.

plex output values Z _x and Z ₂ . The operation shown in FIG. 1 is shown. so write as follows:

complex can be

z; = z, + w _k z ₂

Z'2

= Z ₁

-W, Z ₂ .

Or in polar coordinates:

and

Z; = A _x exp (/ W,) + A ₁ e \ pij (y-> _k +

Z ₁ = A _x

- A _: cxp (/ (« _t +

The one represented by the SchmeUerling diagram complex operation is equivalent to the following complex matrix multiplication:

Z ₂ = 1 U ₁
1 -IV ₁ Z ₂

( 'S Because of the addition in the complex Fourier operation are the complex values usually represented in kartesischcn coordinates.

The complex input serials are the sum of in-phase components l / i and quadruple components (Q) (components with 90 phase difference), d. H.

Z ₁ = A _x cos H _x - JA _x sin H ₁ - I _7x - jQ _7A

The use of floating point control in arithmetic operations complicates the implementation of a processor or arithmetic unit for FFT solutions. The components / _Z1 and Q ₇₁ are therefore normally encoded as simple p-digit binary words. The number of quantization bits (p) required can be quite large and depends on the number of transform coefficients ΙΛ '). which are to be calculated. When the number of quantization bits at the input nodes is p i. is the number of bits required for a V dot FFT. to avoid saturation in the processor, same

ρ = P ₁ -r int ("log ΛΊ.

For example, in the case of the digital filter that works with two 1024-point FFTs with eight-bit input ^{quantization, quantization with 18 bits is required in the last stage of the ünt (3} log ΛΊ; stages "of the FFT calculation. This increase the number of bits in the processor can be avoided to some extent by renormalizing (dividing by 2) the data at each stage where saturation is feared, but the points where saturation may occur may be lower because of the changes in the Unfortunately, the nature of the input data to be transformed cannot be precisely predicted.

The floating point representation given here forces both the / and the Q samples of a complex Value to the same floating point level, i.e. h .. both values of the ordered pairs have the same exponent. This is simultaneous with a representation of the scan data (and intermediate results I. in the shape

Z ₁ =

Z ₂ = (a + Jb) IT.

Using this technique, it is possible, for example, for a / or Q word to be carried ^{or transmitted as 2 w} times zero, where M is an integer if the magnitude of the / or Q component of a complex word is equal to the other exceeds 2 ^P , where ρ is the number of quantization bits used. A simulation of this process by means of a computer showed no impairment of the functionality as a result of this property.

To further simplify the implementation, the floating point exponents are only used in the positive Changed direction. That is, even if a particular sample has / and Q components. the little

n are less than the maximum level, no provision is made to pad these words and match the floating point exponents / v. zoom out.

The effective computational interference level that based on computer simulation of digital filters for the cases 9. 11 and 1 3 bits (including sign) estimated, fluctuates between -35 and -45 dB. related to the signal peak value With a floating point processor, a 9-bit representation results in a computational interference level of -7OdB. which is 25 dB better than with fixed point versions with 13 bits. A level of - "OdB would probably be require a quantization of about 18 or 19 bits. A multiplier just like him for the realization 9-bit quantization is required. has a complexity level of only 64 compared to 324 for the 19-bit processor. which corresponds to a cost reduction of about 80%.

F i g. Figure 2 shows a preferred embodiment of a device for performing the complex operations in floating point representation according to the invention. The mantissa of the complex value Z ₂ signals representing a. b and the signals c and J representing the complex constant \\ ' _k are fed to a complex multiplier 20 as input signals. The complex product occurring at the output of the multiplier is coupled to a weighting or coefficient stage 23. (The small letters in the circles that are inserted into the lines representing the lines indicate the number of wires in the line concerned. The p-bits of the mantissa value contain the sign bit.)

The signals x representing the mantissa of the complex value Z _1. y are fed to a further weighting or coefficient stage 24. The coefficient stages 23 and 24 are controlled by an exponent control device 26 to which signals are applied which represent the exponents of the values Z ₁ and Z ₂ . The purpose of the coefficient stages 23 and 24 is to bring the complex numbers in floating point representation to the same exponent, so that proper addition and subtraction in a complex adder and subtracter unit 28 is possible. The equalization of the exponents of the values of the complex numbers in floating point representation takes place in that the bits of the value with the smaller exponent are shifted to the right by a number of levels equal to the difference between the exponents. The exponent control device 26 is further controlled by a signal from the complex multiplier 20 to correct the exponent values in the case of the product overflow.

The output signals from the complex adder and subtracter unit 28 become coefficients stages 27 and 29 are supplied to adjust the output values when in the adder and subtract, respectively a carryover or borrowing may occur.

The larger de exponents π and m are taken as the starting exponent, to which 1 is added when the complex multiplier 2 supplies an overflow signal, and for what purpose in each one Stage added by adders 21 and 22 a 1 win if in the complex adder and subtract! unit 28 a transfer or an exchange occurs.

The complex output values of the described and shown in FIG. 2 are:

ζ; = UC I. = ad jh) 2 ^m X Y n U 2 '" m Jl if in' < η 7'ι (ad f ./V) 2 "' X > included = (A '- ac π '"+ ^X if in' < η are - bd + ι! r 2 ^m I! if in' > η a ' (ac Y - "■ ₊ V if in" η = ad - bd) 2 (J if in' < η (ad + be + > + he); 2 1 V if in' < η - bd - if in' η χ ' if m ' η - bd) 2 + be - ν + be) 2

m " = hi + CAiO,
ιη = MAXUn ". η) + C.4C.

η '= MAX (In ". ιι) + COD.

The symbol MAX (m ".n) means a size that is equal to the larger of the two sizes in" and η . The abbreviations used have the following meanings:

CAiO overflow signal from complex multiplier;

C-4C carry from complex adder:
COD borrow from complex subtracter.

CMO. CAC and CSB can each have the value O or 1.

A device according to the invention for performing complex FFT operations can be used for serial or parallel data processing is possible be sated. In the case of serial operation, the outlay on equipment is small at the expense of the time required, while in the case of parallel operation, a high working speed due to the high expenditure on equipment must be bought. In the following, for example, an embodiment operating in parallel is described, and based on the related Explanations should not be a problem for the person skilled in the art, easily a serially working one Specify embodiment.

The logic elements represented by appropriately labeled circuit symbols work according to the following rules:

An exclusive OR element (XOR element) delivers a True output when the input signals are complementary, i.e. h_ if that is an input signal a correct input signal and the ancere is a wrong input signal. If both input signals are correct signals or incorrect signals, that is Output signal a false signal. f> 5

The values "correct" and "incorrect" are represented by two voltage values. According to the usual Agreements, the logic value "correct" is represented by the higher voltage value can also be used as a logical one (L) or simply as »high are designated. The logic signal "false" is represented by the low voltage value and < can be designated as a logical zero (O) or as "low".

An AND element supplies the output signal L only when all input signals are equal to L. If any of the input signals is equal to 0, the output signal is also 0.

An OR gate supplies the output signal I whenever at least one of its input signals is equal to L. The output signal is only 0 if all input signals · are equal to 0. An inverter or negator supplies an output signal! the inverse of the input signal. that is, its complement is. When the input signal is a 0. is there: output signal equals L; if the input signal is L then the output signal is 0.

Instead of the links shown in the drawing, other links can also be used members are used, e.g. B. the NOR gate (there: an OR gate with negated output signal corresponds) or the NAND gate (which corresponds to an AND gate with a negated output signal). Tue < Possibilities of substitution of this type are known to the person skilled in the art, so that in the explanation de Invention only AND gates, OR gates, inverters or negators and the general functions of circuit units or blocks.

F i g. 3 shows a more detailed circuit diagram of the ir FIG. 2 complex multiplier 20, shown only in block form. The signals representing the values α and c are fed to a multiplier 30 as input values; the signals corresponding to / and d to a multiplier 31: the signals corresponding to α and d to a multiplier 32 and the signals corresponding to b and c to a multiplier 33. The multipliers 30, 31, 32 and 33 are all known binary multipliers, how they z. B. ir a publication by C. Ghest, "Multiplyin Made Easy for Digital Assemblies" in the magazine "Electronics". Nov. 22nd 1971. pp. 56-61.

Sign control circuits 302, 312, 322 and 332 are coupled to the output terminals of the binary multipliers 30, 31, 32 and 33 and are controlled by output signals from XOR gates 301, 311, 321 and 331 to which the sign bits de; associated value-signal pair are supplied with S _a denotes the sign bit of the value α , etc.

Each input value of the binary multiplier 3 (up to 33 includes p-1 bits. Only bits dei p-1 respectively from the product of the various multipliers highest points as the output signals using the product signals are applied to sign control circuits (hereinafter referred to "sign circuits") 302, 312 , 322 and 332 , respectively, to set or adapt their sign. The way in which the sign circuits work depends on the form in which negative numbers are represented.

The 1's complement is obtained by inverting each ei Binary digit of the value formed. So the 1's complement of 1010010 is 0101101.

The 2's complement is formed by adding a binary I to the 1's complement. The So the 2's complement of 101 (X) IO is 0101110.

F i g. 4 shows an example of a circuit arrangement which can be used as a sign circuit. It contains an XOR element 301 which supplies an output signal 0 corresponding to a positive sign if the operand signals are the same. ie. if both are positive (ie have the logic value 0) or both are negative (ie have the logic value! "). The output signal of the XOR element 301 has the logic value 1 if the operand signals are different.

The output signal of the XOR element 301 forms the one input signal for each of p \ XOR elements 41 43, of which FIG. 4 only three are shown. The second input signal for the XOR elements 41-43 is in each case a bit signal.

If the output signal of the XOR element 301 has the logic value 0, the output signals of the different XOR elements 41 43 each have the same logic value as the associated bit input signal. That is, the bit signals are not changed when the operand signals are the same.

When the output of the XOR gate 301 ^ 5 has the logic wcr * I. the output signals of the XOR gates 41-43 are each the logical complement of the relevant bit input signal. This means that the bitsigna] is inverted each time the operand signals are different. The output signals of the XOR elements 41-43 are therefore the 1's complements of the input data.

However, if the 2's complement of the input data is required, the value 1 must be added to the 1's complement. For the addition of a 1, p- \ half-adders 44-46. only three of which are shown, connected to the outputs of the XOR gates 41-43.

A half adder yeasts depending on two input signals each two output signals, the be referred to as sum or carry signal. The sum output signal has the logic value 1, when the input signals are complementary. The carry output signal only has the logic value 1 when both input signals have the logic value 1. From this it can be seen that a half adder can be implemented with the aid of an XOR element and an AND element, as shown in FIG. 5 shown is.

If the XOR element 301 in the circuit arrangement according to FIG. 4 supplies an output signal with the logic value 0 to the half adder 44, its sum output signal has the same value as the output signal of the XOR element 41. Furthermore, such an output signal from the XOR element 301 causes the carry output signal to have the logic value 0 . The sum output signal of the half adder 45 therefore has the same value as the output signal of the XOR element 42, and the carry output signal of this half adder has the logic value 0. The same conditions apply to all other half adders, since the first input signal always has the logic value 0 has. So if the output signal of the XOR element 301 has the logic value 0, the output data are the same as the input data.

However, if the output signal of the XOR element 301 has the logic value 1, the half-

addicrer 44 46 is the 1's complement of the input data coupled, and the first input of the half adder 44, which corresponds to the lowest Bitstclle «If an input signal with the logic value 1 is drawn ·

> stirs. The resulting output signal is then there « - Complement of the input data.

The ρ-] output signals of the sign circuits 302 and 312 (Fig. 3) form the data input signals of a subtracter, and the p- \ output

> signals of the sign circuits 322 and 332 form the data input signals "of an adder 36. The subtracter 34 receives fine sign input signals from the XOR gates 301 and 311. while the adder 36 receives the sign input signals.

> receives signals from the outputs of the XOR gates 321 and 331 .

The output signals of the subtracter 34; ind des Adder 36 each consist of p-1 result signals, a borrower or surrogate simiaf and one Sign signal. ""

The subtracter and adder operate in a known manner (see e.g. the Applicants the commercially available integrated logic function circuit SN 74 181), so that a more detailed explanation is not necessary.

The result bits from the subtracter 34 and the adder 36 become a coefficient circuit 37 or 39, the task of which is to extract the data bits from the subtracter in the event of a borrower or a carry from the adder to change accordingly. Both results must be adjusted or be changed because they both have the same mantissas Represent exponents.

If a borger occurs in the level of the subtractor 34 assigned to the highest digit and / or a carry occurs in the level of the adder 36 assigned to the highest digit, at least one input signal of an OR element 36 to which borrower and carry are fed has the logic value 1. and it accordingly supplies an output signal CMO with the logic value 1. which indicates an overflow from the complex multiplier.

The CMO signal becomes the exponent control device to increase the correct exponent value in the event of an overflow.

If an overflow occurs, the outputs from the subtracter 34 and adder 36 are each shifted to the next lower bit position, and a correct bit MSB is put into the next bit position. The correct bit MSB is defined as the sign bit or borger bit for the coefficient stage 37 downstream of the subtracter 34 or the sign bit or carry bit for the coefficient stage 39 downstream of the adder 36.

The borrow (or carry) bit represents a bit value of a higher position. The reason for introducing the sign bit is that the empty MSB should be the same as the sign. So meant z. BUÜI0110 the number +22, whereby the bit in front of the binary point is the sign. A shift by ^an if " ^{elIe to the} right (division by 2) results in -nn," ¹¹ ' ^{which is + Π} - on the other hand, 1.101010 means the number -22 in the 2's complement representation. ^{When shifted} by one bit position to the right -n be ^the 'Resuhat' -ΠΟΙΟΙ, so that it represents the number l 1 in the 2-complement representation, u The empty position in the positive number was filled with a υ and m in the negative number with a 1 .

F i μ. fi / cig! a circuit arrangement which is able to perform the above-described function of a coefficient stage. It contains an inverter 61 to which a control signal corresponding to the CMO signal from the OR gate 35 (FIG. 3) is fed. The circuit arrangement also contains p- \ groups of AND and OR gates, such as the AND-ODLR-Glicd group 62, of which only three are shown to simplify the drawing. Each UN D-OR element group corresponds to an input data bit position. A first AND gate of each group is made to pass by the inverted control signal. The other input signal of the first AND element of each group is the corresponding image signal of the input data.

The second AND element of each group is brought into the ready-to-pass state by the control signal, and the other input signal (with the exception of the MSB group) is the bit signal assigned to the next higher hit position. The second input signal of the second AND element in the MSB- LJND-OR element group is the output signal of an OR element 64, to which the sign signal and the borrower (or carry) signal are supplied as input signals.

When the control signal CMO has the logic value 0. the inverted control signal has the logic value 1, which causes the bit input signals to be passed through to the output lines of the same bit positions that carry the adjusted data.

When the control signal has the logic value 1. the bit input signals are passed through to the output lines carrying the adjusted data of the next lower bit position and the MSB output signal is a bit value as defined above.

The p-1 output signals from the coefficient stages 37 and 39 (FIG. 3) together with the associated sign bits form the output signals of the complex multiplier 20 in FIG. 2. These signals are fed to the coefficient stage 23, and the input signals corresponding to Z ₁ (x. Y) are fed to the coefficient stage 24. The coefficient stages 23 and 24 are controlled by q output signals from the exponent control device 26, respectively.

The task of the exponent control device 26 is to feed either the coefficient stage 23 or the coefficient stage 24, but not both, an adjustment or coefficient factor and to pass the larger exponent through to the output adders 21 and 22. The inputs to the exponent controller 26 are the exponents m and n, each consisting of q bits. If a CMO signal occurs, the exponent m must be increased by 1.

F i g. 7 shows one suitable for performing the functions of the exponent controller 26 Circuit arrangement.

The q bits of the exponent m are fed to an adder 71 which operates in the same way as the cascaded half adders described in connection with the sign control and shown in FIG. 4 are shown. The first input signal of the first half adder, which has q stages, is the CMO signal. The output signals of the adder 71 are binary. equals m if the CMO signal has the logic value 0, or

a binary value equal to m + 1 if the CMO signal has the logic value 1. This value is denoted by m ".

The signals representing the values in ″ and η are input to a subtracter 73. The output signals of the subtracter 73 are q bits representing the value of the difference in ″ - η and a sign bit. Suitable subtractors are known, so that an explanation can be dispensed with. In order to form the absolute value of the difference, a device for forming the 2's complement can be installed in the subtractor. as described above in connection with FIG. 4, can be used to modify the output value when the pre / cichen bit has the logic value 1 and indicates a negative value.

A sign bit of the logic value 1 indicates. that the exponent η is greater than the exponent m " , so that the binary output width from the complex multiplier 20 (FIG. 2) must be shifted to the right by m" -η bit positions. The sign bit is therefore fed as an input signal to q AND gates, the other input signals of which are the q difference bits which indicate the value in "- η

The sign bit is also fed to q AND gates 77 as an input signal, the other input signals of which are the q bits which represent the value of η .

The output signals of the q AND gates 77 are fed to the output adders 21 and 22 (FIG. 2 | via q OR gates 79. (The designation xq in the figure means that each switching element stands for q logic elements.)

The sign bit is inverted by an inverter 75, so that the sign bit of the logic value 0 is lost in the logic value 1 if in "is greater than η . This condition then enables the q AND gates 76 to use the difference bits to the coefficient stage 24 (Fig. 2 | in order to shift the bits of the value η by m "- η bit positions to the right. The output signal of the logic value 1 from the inverter 75 also makes q AND gates 78 open, so that the / n "signals are coupled to the output adders via the q OR gates 79.

F i g. 8 shows a circuit arrangement which can perform the function of a coefficient stage. To simplify the representation, the input data are represented here by eight bits and the difference value from the exponent control device by three bits D2 °, D2 ¹ and Dl ¹ .

The in F i g. 8 shown coefficient level setzi consists of three columns, each with eight AND-OR member groups. The transmission state de: The first of the two-input AND members of each group in each column is thrucl controlled a difference bit. The second AND element of each group w j-d by an inverted difference bi controlled.

The other input signals for the second AND elements of each group are the associated bit signals « In the groups of the first column, the associated bit signals are the input data bits, in de second column the output signals of the ODEP elements from the corresponding stages of the first Column and in the third column the output: signals of the OR gates from the corresponding Steps of the second column. The initial signa

Lt

the OR gates of the third column are the adjusted data output signals.

The other input signals of the first AND elements of each group are those other input signals which are fed to the second elements, which correspond to positions i bit positions higher than the associated stages. The value of ι depends on the column number c according to the equation / = 2 ^c ~ ^l , ie for the first column / = I, for the second column i = 2, and for the third column i = 4. The remaining The sign bit is fed to inputs for reasons that have been explained above in connection with the coefficient stages of the complex multiplier.

The difference bit controlling the respective column also represents a difference value equal to i. The adjusted data output signals are thus equal to the number corresponding to the difference value be input data signals shifted to the right by bit positions.

The difference bit D 2 ° means the difference value 1. If D2 ° = 0, the input bits are not shifted. If D2 ° = 1, the input bits are shifted one bit position to the right, ie in the direction of lower digit values.

The difference bit D2 ¹ means the difference value 2. If D2 ^l = 0, the bits from the first column are not shifted. If Z) 2 '= 1, the bits from the first column are shifted two bit positions to the right.

The difference bit D2 ¹ means the difference value 4. If D2 ² = 0, the bits from the second column are not shifted. When D2 ² = 1, the bits from the second column are shifted four bit positions to the right.

If one assumes, for example, that the difference m "-n has the value 5, then D2 ² = 1. D2 ¹ = 0 and D2 ° = 1.

Bit 7 (i.e. the bit of the 7th position) with the logic value 1 should now be followed by the coefficient level will.

The value D2 ° = 1 causes the bit 7 fed to an AND element 80 to appear as the output signal of an OR element 81.

The value D2 ¹ = 0 is inverted by an inverter 82 into the logic value 1, so that the output signal of the OR element 81 fed to an AND element 83 occurs as an output signal at an OR element 84.

The value D2 ² = 1 has the effect that the output signal of the OR element 84 fed to an AND element 85 appears as an output signal at an OR element 86.

The input data bit 7 becomes this adjusted data output bit 2, i. That is, there is a shift by five bit positions to the right.

The coefficients rank 23 and 24 in FIG. 2 included two of the in F i g. 8 shown circuit arrangements.

The values x, y representing Z ₁ are designated by x "and y" after the adjustment. The values representing ac-kd and ad + bc are designated with a " and b" after the adjustment.

The adjusted data output bits from efficiency stages 23 and 24 in FIG. 2 become the complex Adder and subtracter unit 28 is supplied, the structure of which is shown in FIG. 9 shown in more detail is.

The circuit arrangement according to F1 g. 9 contains two adders 91 and 93 which add the binary values a " and x" or b " and / '. The circuit arrangement also contains two subtractors 92 and 94 for subtracting the binary value x" from a " and y" from b ". .

The adders and subtractors are known circuit arrangements that are not described too will need.

The carry output signals from the adders 91 and 93 are input to an OR gate 95 which provides an output signal CAC. The signal CAC controls the output adder 21 and the coefficient structure 27 (FIG. 2) to which the sum bus, the output signal bits and carry bits are supplied as input signals.

In a corresponding manner, the Borger output signals are combined in an OR gate% to generate a signal CSB which controls the coefficient stage 29 and the adder 22 (FIG. 2). The difference bits, output signal bits and borger bits form the input signals for the coefficient stage 29 (Fig. 2).

The sign signals S ₀ and S _h ■■ are the sign output signals from the subtracter 34 and adder 36 (FIG. 3). The sign signals S _x and S are the sign input bits of the complex value Z ₁ U, y).

The sign bits S n, S _h -, S _x and S _y from the complex adder and subtracter unit are the output sign bits.

The data output signals from the complex adder and subtracter unit 28 in FIG. 1 are adjusted accordingly when the signal CAC or the Signa! COD occurs. Each number in a pair of complex numbers must be adjusted for the complex multiplier in the manner described above. The coefficient levels 27 and 29 can be achieved by using two of the steps shown in FIG. 6 be written and shown there circuit arrangement can be realized for each coefficient stage The control signal for the coefficient stage 27 is there; Signal CAC and for the coefficient stage 29 da: signal CSB.

The output adders 21 and 22 correct the exponent output signal c according to the Justic tion.

These adders can be implemented with half adders in the manner described above.

For this 5 blood! drawings

Claims (2)

Patent claims: 15 1. Device for multiplying a first complex number Z ₂ = (a + jb) 2 ^m in floating point representation with a third complex number and adding a second complex number Z ₁ = (x + jy) 2 " to that obtained in the multiplication Product, characterized in that the third complex number ^W k - c + jd is represented in fixed point representation; that signals (c, d), which express the third complex number expressed in fixed point representation, and signals (α, b) , which represent the mantissa of the first complex number (Z ₂ ) expressed in floating point representation, are fed to an input circuit (30, 31, 32, 33) of a complex multiplier (20 in FIG. 2; FIG. 3), the output of which Provides signals which represent the product p = ([ac-bd] + j [ad + bc]) 2 " ; that signals representing the exponent (m, n) of the first and second complex numbers (Z ₂ , Z ₁ ) expressed in floating point representation are supplied to an exponent control device (26 in FIG. 2; FIG. 7) provides the output signals (through gates 74 and 76 in FIG. 7) indicating the relative magnitudes of the exponents of the complex numbers expressed in floating point and output signals (of 79) indicating the larger exponent; that the output signals of the exponent control device (26) two coefficient stages (23 and 24 in Fi g. 2) are fed, which the signals (a \ b ') from the output of the multiplier (20) and the signals (x, y) accordingly change the mantissa of the second complex number in such a way (in a ", b" or :: ", / ') that the number with the smaller of the two exponents is represented with the larger of the two exponents; that the modified signals ( α ", b", x ", v" and sign bits) are fed from the two coefficient stages (23, 24) to an adding circuit (28 in FIG. 2; 91, 93 in FIG. 9), which output signals (a " + χ ", Sa ' etc.) corresponding to the complex sum of the modified signals and possibly corresponding to a carry; and that the carry output signals (CAC) are fed to a sum exponent circuit (21 in FIG. 2) which the signals which the represent the larger of the two input exponents when a carryover occurs in the sense of an increase ng of the exponent changes by one unit and generates output signals (m ') that represent the exponent of the complex sum. 2. Device according to claim 1, characterized by a subtraction circuit (92, Fig. 9). to which the modified signals from the first and second coefficient stages (23, 24) are applied to produce output signals representing the complex difference and borrower [CSB] of the modified signals and a difference exponent circuit (22 in Fig. 1). which is supplied with the Borger output signal (CSB) in order to modify the signals representing the larger input exponent value to produce output signals representing the exponent of the subtracter output signals. 30th 35 40 45 50 ■ x Finrichtung according to claim 2, characterized ge-3. Euincmung _sums e _X component circuit ^ke Tn ^e Π fferSzexponentkreis adder for ^d ^ S? biponent values by 1 in Abden transfer or borrower signals