DE2431374A1 - Semiconductor with double silica coating - having very thin thermal and thicker pyrolytic layer, minimising change in dislocation ratio - Google Patents

Semiconductor with double silica coating - having very thin thermal and thicker pyrolytic layer, minimising change in dislocation ratio

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Publication number
DE2431374A1
DE2431374A1 DE2431374A DE2431374A DE2431374A1 DE 2431374 A1 DE2431374 A1 DE 2431374A1 DE 2431374 A DE2431374 A DE 2431374A DE 2431374 A DE2431374 A DE 2431374A DE 2431374 A1 DE2431374 A1 DE 2431374A1
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Prior art keywords
semiconductor
layer
oxide layer
approx
semiconductor device
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DE2431374A
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German (de)
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Andreas Dipl Phys Csillag
Gerhard Laessing
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Licentia Patent Verwaltungs GmbH
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Licentia Patent Verwaltungs GmbH
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Priority to DE2431374A priority Critical patent/DE2431374A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A semiconductor device, consisting of a semiconductor monocrystal with a (partial) oxide coating on its surface, has an extremely thin coating (pref. 200-700 angstroms thick) of SiO2 produced thermally and then a thicker coating (pref. ca 1 mu m thick) of SiO2 deposited pyrolytically. The semiconductor device is used in the prodn. of diodes, transistors and integrated circuits. The proportion of dislocations in the epitaxial layer of the device undergoes minimal change in the prodn. of the passivating oxide coating.

Description

"Halbleiteranordnung aus einem einkristallinen Halbleiterkörper" Die Erfindung betrifft eine Halbleiteranordnung aus einem einkristallinen Halbleiterlcörper mit einer die Halbleiteroberfläche zumindest teilweise bedeckenden Oxydschicht."Semiconductor arrangement from a single-crystal semiconductor body" Die The invention relates to a semiconductor arrangement made from a single-crystal semiconductor body with an oxide layer at least partially covering the semiconductor surface.

In der Halbleitertechnik ist es üblich, die Oberfläche der Halbleiteranordnungen mit einer Isolierschicht zu versehen, durch die die im Halbleiterkörper vorhandenen pn-Übergänge passiviert werden. Die Isölierschichten dienen gleichzeitig als Diffusionsmaske und als Träger für die elektrischen Anschlußleitbahnen. In vielen Fällen besteht die Isolierschicht aus Siliziumdioxyd. Diesem Material wird vor allem dann der Vorzug gegeben, wenn der Halbleiterkörper aus Silizium besteht. Die Oxydschicht kann dann durch thermische Oxydation des Halbleitermaterials hergestellt werden.In semiconductor technology, it is customary to use the surface of the semiconductor arrangements to be provided with an insulating layer through which the existing in the semiconductor body pn junctions are passivated. The insulating layers also serve as a diffusion mask and as a carrier for the electrical connection interconnects. In many cases it exists the insulating layer made of silicon dioxide. This material then becomes the most preferred given when the semiconductor body consists of silicon. The oxide layer can then be produced by thermal oxidation of the semiconductor material.

Neuerdings werden zahlreiche Halbleiterbauelemente und integrierte Schaltungen hergestellt, bei denen der Halbleiterkörper eine oder mehrere epitaktisch gebildete Halbleiterschichten aufweist. Diese Epitaxieschichten haben in der Regel eine konstante Dotierung Es hat sich nun gezeigt, daß bei der thermischen Oxydation derartiger Epitaxieschichten die an der Oberfläche der Epitaxieschicht vorhandenen Störstellen in das Innere der Epitaxieschicht abgedrängt werden. Auf diese Weise erhöht sich die Störstellenkonzentration unmittelbar unter der thermisch erzeugten Oxydschicht und fällt zum Inneren der Epitaxieschicht hin ab. Wird nun in diesen Bereich mit einem Störstellengradienten ein pn-übergang eingebracht, so nimmt die erzielbare Abbruch spannung des pn-überganges ab. Wird der pn-übergang tief in die Epitaxieschicht eindiffundiert, um auf diese Weise den pn-übergang in den Bereich konstanter Dotierung zu legen, so muß die Halbleiteranordnung während einer relativ langen Zeit einer erhöhten Temperatur ausgesetzt werden. Dabei dringen Störstellen aus dem im allgemeinen sehr hoch dotierten Halbleitergrundkorper in die Epitaxieschicht ein und erzeugen ao in der Epitaxieschicht wiederum einen unerwünschten Störstellengradienten. Diese Veränderung der Störstellenkonzentrationsverhaltnisse in der Epitaxieschicht ist besonders bei Kapazitätsvariationsdioden unerwünscht. Außerdem muß bei diesem Verfahren eine relativ dicke Spitax.eschicht verwendet werden.Recently, there are numerous semiconductor devices and integrated Circuits manufactured in which the semiconductor body is one or more epitaxially having formed semiconductor layers. These epitaxial layers usually have constant doping. It has now been shown that with thermal oxidation such epitaxial layers are those present on the surface of the epitaxial layer Impurities are displaced into the interior of the epitaxial layer. In this way the impurity concentration increases immediately below that generated thermally Oxide layer and falls towards the inside of the epitaxial layer. Is now in this A pn junction is introduced into the region with an impurity gradient, so the achievable breakdown voltage of the pn junction. If the pn junction goes deep into the Epitaxial layer diffuses in, in order to create the pn junction in the area To put constant doping, the semiconductor device must during a relatively exposed to an elevated temperature for a long time. In this way, imperfections penetrate from the semiconductor base body, which is generally very highly doped, into the epitaxial layer ao and in turn generate an undesired impurity gradient in the epitaxial layer. These Change in the impurity concentration ratios in the Epitaxial layer is particularly undesirable in the case of capacitance-varying diodes. aside from that a relatively thick Spitax layer must be used in this process.

Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, eine llalbleiteranordnung anzugeben, bei der die Störstellenverhältnisse in der Fpitaxieschicht durch die Erzeugung einer Oxydpassivierungsschicht an der Oberfläche möglichst nicht verändert werden. Diese Aufgabe wird bei einer Halbleiteranordnung der eingangs beschriebenen Art erfindungsgemäß dadurch gelöst, daß die Oberfläche des Halbleiterkörpers mit einer extrem dünnen Schicht aus thermisch erzeugtem Siliziumdioxyd bedeckt ist und daß auf diese Schicht eine dickere Schicht aus pyrolitisch abgeschiedenem Siliziumdioxyd aufgebracht ist.The present invention is therefore based on the object of a Specify semiconductor arrangement in which the impurity ratios in the epitaxial layer by creating an oxide passivation layer on the surface, if possible not to be changed. In the case of a semiconductor arrangement, this task is addressed at the outset described type according to the invention achieved in that the surface of the semiconductor body is covered with an extremely thin layer of thermally generated silicon dioxide and that on this layer a thicker layer of pyrolytically deposited silicon dioxide is upset.

Die thermisch erzeugte Oxydschicht weist vorzugsweise eine Dicke von 200 bis 700 Å auf. Dagegen ist diese pyrolitisch erzeugte Oxydschicht etwa 1 /um dick.The thermally generated oxide layer preferably has a thickness of 200 to 700 Å. In contrast, this pyrolytically produced oxide layer is about 1 / um thick.

Bei der Erzeugurlg einer derart dünnen Oxydschicht durch thermische Oxydation ist die Zahl der von der OberflAche verdrSngten Störstellen äußerst gering. Das Konzentrationsgefälle an der Oberfläche der Epitaxieschicht fällt daher praktisch nicht ins Gewicht. Das pyrolitisch erzeugte Oxyd läßt nur noch ein unbedeutendes Wachstum der thermisch erzeugten Oxydschicht zu. Das pyrolitische Oxyd wird bei einer relativ niederen Temperatur erzeugt, so daß sich dabei keine nachteiligen Diffusionsvorgänge im Inneren des Halbleiterkörpers abspielen. Das pyrolitisch erzeugte Oxyd wird noch bei einer erhöhten Temperatur verfestigt.When creating such a thin oxide layer by thermal Oxidation is the number that is displaced from the surface Imperfections extremely low. The concentration gradient on the surface of the epitaxial layer is therefore practically insignificant. The pyrolytically produced oxide leaves only an insignificant growth of the thermally generated oxide layer. The pyrolytic Oxide is produced at a relatively low temperature, so there is no play disadvantageous diffusion processes in the interior of the semiconductor body. That Oxide produced by pyrolysis is still solidified at an elevated temperature.

Die hierfür erforderliche Zeit ist jedoch so gering, daß auch hierdurch keine störenden Veränderungen der Dotierungsverhältnisse hervorgerufen werden.However, the time required for this is so short that it also does this no disruptive changes in the doping ratios are caused.

Die Erfindung soll im weiteren noch anhand eines Ausführungsbei spiel es näher erläutert werden.The invention is further based on a Ausführungsbei game it will be explained in more detail.

In der Figur 1 ist der hochdotierte Halbleitergrundkörper 1 dargestellt auf den eine Epitaxieschicht 2 geringerer Dotierung aufgebracht ist. Die Dotierung in der Epitaxieschicht ist über deren gesamten Querschnitt konstant. Die flaibleiteranordnung wird zunächst in eine oxydierende Atmosphäre eingebracht, um die dünne thermisch erzeugte Oxydschicht herzustellen.The highly doped semiconductor base body 1 is shown in FIG on which an epitaxial layer 2 of lower doping is applied. The doping in the epitaxial layer is constant over its entire cross section. The flaible conductor arrangement is first placed in an oxidizing atmosphere to thermally remove the thin to produce generated oxide layer.

Dies geschieht; bei einer Temperatur von ca. 1000 0C während einer Zeit von 50 Minuten. In einer trockenen Sauerstoffatmosphäre bildet sich dabei an der Haibleiteroberfläche eine ca.This happens; at a temperature of approx. 1000 0C during a Time of 50 minutes. It forms in a dry oxygen atmosphere the semiconductor surface has an approx.

700 i dicke Oxydschicht 3.700 i thick oxide layer 3.

Bei 400 QC findet danach in eineinReaktor eine pyrolitische Zersetzung von Silan mit Sauerstoff statt. Hierbei scheidet sich auf der dünnen Oxydschicht 3 eine etwa 1 /um dicke Oxydschicht 4 ab. Danach wird die Hableiteranordnung etwa 5 Minuten lang-bei einer Temperatur von etwa 1100 C getemperte Dabei verfestigt sich die Oxydschicht. Der Temperprozess wird vorzugsweise in einer Schutzgasatmosphäre durchgeführt.At 400 ° C., a pyrolytic decomposition then takes place in a reactor of silane with oxygen instead. This separates on the thin oxide layer 3 an approximately 1 / µm thick oxide layer 4. After that, the semiconductor array is approximately Heated for 5 minutes at a temperature of about 1100 ° C., solidified the oxide layer. The tempering process is preferably carried out in a protective gas atmosphere carried out.

Gemäß Figur 2 wird in die Doppeloxydschicht ein Diffusionsfenster 5 eingeätzt, durch das in den Halbleiterkörper Störstellen eindiffundiert werden, die im Inneren der Epitaxieschicht einen pn-übergang 6 erzeugen. Das Diffusionsfenster 5 kann gleichzeitig als Kontaktierungsfenster benutzt werden. Dann wird nach der Reinigung der Halbleiteroberfläche in diesem Fenster ein Metallkontakt 7 abgeschieden. Die Rückseite der Halbleiteranordnung wird mit einem weiteren Kontakt 8 versehen.According to FIG. 2, a diffusion window is made in the double oxide layer 5 etched in, through which impurities are diffused into the semiconductor body, which generate a pn junction 6 inside the epitaxial layer. The diffusion window 5 can also be used as a contact window. Then after the Cleaning the semiconductor surface in this window a metal contact 7 is deposited. The rear side of the semiconductor arrangement is provided with a further contact 8.

Bei einem Ausführungsbeispiel konnte festgestellt werden, daß bei einer Diode der beschriebenen Art der Serienwiderstand um etwa 20 % reduziert werden konnte. Etwa um den gleichen Faktor konnte die Güte der Diode verbessert werden. Es sei darauf hingewiesen, daß der erfindungsgemäße Aufbau der Isolierschicht auch bei Transistoren und integrierten Schaltungen Verwendung finden kann.In one embodiment it was found that at a diode of the type described, the series resistance can be reduced by about 20% could. The quality of the diode could be improved by about the same factor. It should be noted that the inventive structure of the insulating layer can be used in transistors and integrated circuits.

Claims (7)

P a Ü e n t a n s p r ü c h eP a Ü e n t a n s p r ü c h e (öl) Halbleiteranordnung aus einem einkristallinen Halbleiterkörper mit einer die Halbleiteroberfläche zumindest teilweise bedeckenden Oxydschicht, dadurch gekennzeichnet, daß die Oberfläche des Halbleiterkörpers mit einer extrem dünnen Schicht aus thermisch erzeugtem Siliziumdioxyd bedeckt ist und daß auf diese Schicht eine dickere Schicht aus pyrolitisch abgeschiedenem Siliziumdioxyd aufgebracht ist.(oil) Semiconductor arrangement made from a single-crystal semiconductor body with an oxide layer at least partially covering the semiconductor surface, characterized in that the surface of the semiconductor body with an extremely thin layer of thermally generated silicon dioxide is covered and that on this Layer a thicker layer of pyrolytically deposited silicon dioxide is applied is. 2) Halbleiteranordnung nach Anspruch 1, dadurch gekennzeichnet, daß die thermisch erzeugte Oxydschicht ca. 200 bis 700 2 dick ist. 2) semiconductor device according to claim 1, characterized in that the thermally generated oxide layer is approx. 200 to 700 2 thick. 3) Halbleiteranordnung nach Anspruch 1, dadurch gekennzeichnet, daß die pyrolitisch erzeugte Oxydschicht ca. 1 /um dick ist. 3) semiconductor device according to claim 1, characterized in that the pyrolytically produced oxide layer is approx. 1 / µm thick. 4) Halbleiteranordnung nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, daß die Doppelschicht auf einem Halbleiterkörper angeordnet ist, der auf seiner der Isolierschicht zugewandten Oberflächenseite eine epitaktisch gebildete, gleichmäßig dotierte Halbleiterschicht aufweist. 4) semiconductor arrangement according to one of the preceding claims, characterized characterized in that the double layer is arranged on a semiconductor body, the one on its surface side facing the insulating layer one epitaxially has formed, uniformly doped semiconductor layer. 5) Verfahren zum Herstellen einer Halbleiteranordnung nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, daß auf die auf einem Halbleitergrundkörper angeordnete Epitaxieschicht konstanter Dotierung in einer oxydierenden Atmosphäre bei ca.5) Method for producing a semiconductor device according to one of the The preceding claims, characterized in that on a semiconductor base body arranged epitaxial layer of constant doping in an oxidizing atmosphere at approx. 1000 0C eine dünne Oxydschicht durch thermische Oxydation aufgebracht wird, und daß danach durch Zersetzung von Silan in Sauerstoff bei einer Temperatur von ca. 400 C auf die dünne, thermisch erzeugte Oxydschicht eine wesentlich dickere oxydschicht pyrolitisch abgeschieden wird.1000 0C a thin oxide layer is applied by thermal oxidation and that thereafter by decomposition of silane in oxygen at a temperature from approx. 400 C to the thin, thermally generated oxide layer, a much thicker one oxide layer is deposited pyrolytically. 6) Verfahren nach Anspruch 5, dadurch gekennzeichnet, daß die Halbleiteranordnung nach der Abscheidung der dicken Oxydschicht zur Verfestigung der Oxydschicht bei ca. 1100 C getempert wird.6) Method according to claim 5, characterized in that the semiconductor device after the deposition of the thick oxide layer contributes to the solidification of the oxide layer is tempered approx. 1100 C. 7) Verfahren nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, daß in die Oxydschicht nach ihrer Herstellung ein Diffusionsfenster zur Eindiffusion eines pn-überganges in die Epitaxieschicht eingebracht wird.7) Method according to one of the preceding claims, characterized in that that in the oxide layer after its production a diffusion window for diffusion a pn junction is introduced into the epitaxial layer.
DE2431374A 1974-06-29 1974-06-29 Semiconductor with double silica coating - having very thin thermal and thicker pyrolytic layer, minimising change in dislocation ratio Ceased DE2431374A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855823A1 (en) * 1977-12-26 1979-06-28 Tokyo Shibaura Electric Co METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
DE3138340A1 (en) * 1981-09-26 1983-04-14 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Process for producing planar components
DE3708474A1 (en) * 1987-03-16 1988-09-29 Licentia Gmbh Majority-carrier semiconductor component and method of fabricating it

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855823A1 (en) * 1977-12-26 1979-06-28 Tokyo Shibaura Electric Co METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
DE3138340A1 (en) * 1981-09-26 1983-04-14 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Process for producing planar components
DE3708474A1 (en) * 1987-03-16 1988-09-29 Licentia Gmbh Majority-carrier semiconductor component and method of fabricating it

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