DE2423130A1 - CIRCUIT ARRANGEMENT FOR CONVERTING DIGITAL SIGANLES, IN PARTICULAR PCM SIGNALS, INTO CORRESPONDING ANALOG VOLTAGES - Google Patents

Description

SIEI ^ EMS -AKTIENGESELLSCHAFT Munich 2,

Berlin and Munich Witteisbacherplatz 2

VPA 74/6069

Circuit arrangement for converting digital signals, in particular PCM signals, into corresponding analog ones Tensions

The invention relates to a circuit arrangement for converting digital signals consisting of individual bits, in particular PCM signals, in these corresponding analog voltages, using a series-connected from Transverse resistances and the resistance chain conductor network that is connected to them, whose shunt resistances each have a resistance value R and whose leakage resistances each have the Resistance value 2R possesses, with those ends of the bleeder resistors that are connected to the shunt resistors Opposite ends, a voltage corresponding to the bits of the respective digital signal can be applied and where of the connection point of a bleeder resistor and at least one transverse resistor that of the respective digital Signal corresponding analog voltage can be removed.

A circuit arrangement of the type mentioned above is already known (US Pat. No. 3,051,938J. In this known circuit arrangement the resistors of the resistor ladder network are made up of individual discrete resistors. However, this requires a not inconsiderable amount of space with himself. This known circuit arrangement is therefore only poorly suited for circuits that are particularly small are to be carried out.

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A digital-to-analog converter is also known (US Pat. No. 3,646,587) in which a large number of field effect transistors existing switchable resistors each with a current path and a control electrode in such a way with one another is connected that all current paths are parallel to each other. The resistance values of the relevant current paths are included in the ratio of powers of two to each other. The control electrodes of the relevant field effect transistors are with connected to the output electrodes of further controlling field effect transistors, which are individually defined by the bits of the The digital signals to be converted in each case are controlled and the digital signals associated with them are therefore switchable Resistance to make the used field effect transistor conductive. With the current paths lying parallel to each other of the first-mentioned field effect transistors, an amplifier is connected on the input side, the output side of the respective, output voltage corresponding to the digital signal. Although all of the transistors provided in this known digital signal / analog signal converter are made up of MOS field effect transistors can be formed, brings the use of field effect transistors as switchable resistors with resistance values, those in the known digital signal to analog signal converter in question in a ratio of powers of two to one another stand, considerable difficulties in terms of the implementation of such a circuit with it, namely a A large number of differently sized field effect transistors must be provided.

The invention is now based on the object of showing a way of how with a relatively small number of different components to be measured can be managed to convert a digital signal into an analog signal in a space-saving design to implement.

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a circuit arrangement of the type mentioned above according to the invention in that all "resistors of the 7 / resistor ladder network are formed by the source-drain paths of MOS transistors, of which the transverse resistors forming MOS transistors are always in the conductive state and with their source-drain paths javeils a V / resistance value of R and of which the MOS transistors forming the leakage resistors are in the conductive state with their source-drain lines each have a resistance value of 2R, that with the cross resistances of the resistor chain line network MOS transistors forming two groups of the leakage resistors of the Y / resistor ladder network forming MOS transistors are connected, of which the MOS transistors of the one group of MOS transistors with their ends opposite to the ends juxtaposed with the Forming transverse resistances of the resistor ladder network MOS transistors are connected, are at a fixed potential and of which the MOS transistors of the other group of MOS transistors with their ends which are opposite the ends which are connected to the transverse resistances of the resistor ladder network forming MOS transistors are connected to a certain other potential, and that they each have one electrode on one and the same Electrode of a cross resistor of the resistor ladder network forming MOS transistor connected MOS transistors of the two groups of MOS transistors with their Gate electrodes are connected to alternatively activated outputs of a control circuit, the input side each one Bit of the respective digital signal can be supplied.

The invention has the advantage that they are dimensioned in different ways and with particularly few small executable MOS-Transis.toren gets by to digital

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To convert signals into these corresponding analog voltages.

According to an advantageous embodiment of the invention, the control circuits each contain two inverters connected in series, at their outputs the gate electrodes of the MOS transfetors are connected, which are connected together to one and the same electrode as a cross resistance of the Y / 'resistance ladder network serving MOS transistor "are connected", and also the inverter is first in the series circuit One bit of the respective digital signal can be fed to each inverter. This has the advantage of a special one low tax expense.

According to yet another useful embodiment of the invention the inverters are formed by MOS transistors. This advantageously results in a particularly low level circuitry effort for the inverters,

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According to yet another useful embodiment of the invention are formed by MOS transistors with the source-drain paths of the MOS transistors forming the inverters Load resistors connected in series. This has the advantage that all circuit elements of the circuit arrangement are implemented according to the invention by MOS transistors and thus with particularly simple connections between the individual circuit elements can be done.

According to yet another useful embodiment of the invention the MOS transistors forming said load resistances are formed by KOS transistors of the depletion type. This has the advantage that it is possible to manage with gate control voltages which are equal to the sink voltages which are the KOS transistors forming the inverters.

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ung According to yet another embodiment of the invention, at Occurrence of / digital signals that eixier in addition to the amplitude the corresponding analog voltage indicating bits or at least one sign bit indicating the polarity of this voltage include the specific other potential of two potential sources switched to "alternately effective" by the sign bit released, which supply potentials with different polarity. This results in the Varte.il that on relatively simple way also sign bits in digital signals can be taken into account with regard to the delivery of corresponding analog voltages.

According to yet another expedient embodiment of the invention is the one at the ends of the resistor ladder network lying MOS transistors, each forming a bleeder resistor, each have an additional MOS transistor with its source-sink path connected in parallel that

always in the conductive state is ürid "thereby" the ""

Has resistance value 2R. This is relatively easier It is also ensured that each one corresponds to a leakage resistance MOS transistor in the resistor ladder network such an equal resistance value is connected in parallel.

According to yet another useful embodiment of the invention are the transverse resistances of the resistor ladder network constituting MOS transistors are formed by enhancement type MOS transistors. This results in the advantage that the MOS transistors in question make direct use of the highest negative or positive Supply voltage can be controlled in the conductive state.

According to yet another useful embodiment of the invention are the leakage resistances of the 7 / iderstand's chain conductor network constituting MOS transistors are formed by enhancement type MOS transistors. This results in

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the advantage that it can be done in a relatively simple manner without separate circuitry to the relevant ϊ / IOS-T ran sis tor s when not required in the non-conductive state to convict.

According to yet another useful embodiment of the invention are all KOS transistors in a common integrated circuit included. This has the advantage of a particularly small size for the entire Circuit arrangement according to the invention. In addition, this measure opens up the possibility of advantageously Circuit arrangement according to the invention in one complete to use integrated encoder working according to the iterative method, as already proposed elsewhere (German note P 23 15 986.6-31).

The invention is explained in more detail below using an exemplary embodiment with the aid of a drawing.

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The circuit arrangement shown in the drawing contains as an essential component a chain ladder network, which, as will be seen below, is a V / resistor chain ladder network represents. This ladder network is made up of MOS transistors realized. The chain conductor network in question includes those as transverse resistances with their source-sink routes exploited and series-connected MOS transistors T1a to T1m, here by means of MOS transistors of the enhancement type may be formed with p-channel. Also belong to the relevant ladder network with their source-sink routes as leakage resistors in the mentioned ladder network exploited and with their one (main) electrodes with the source-drain paths of the MOS transistors T1a to T1m to the Connection points A, B to E connected MOS transistors

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T2a, T2b to T2n and T2a ', T2b' to T2n ^! which may be formed here by MOS transistors of the enhancement type with p-channel. The connection point M can for example be the connection point from which an analog voltage can be taken which corresponds to a digital signal, the bits of which - as will be seen further below - are used to control the resistor ladder network. The MOS transistors T2a * to T2n 'belong, as will be seen further below, to a first group of MOS transistors forming bleeder resistors, and the MOS transistors T2a to T2n belong to a second group of MOS transistors which form bleeder resistors. The MOS transistors belonging to the first group have their other (main) electrodes at a fixed potential, in particular at ground; the MOS transistors belonging to the second group are, as will become apparent, at a certain other potential, the polarity of which can preferably be changed.

As cross resistances in the resistor ladder network MOS transistors T1a to T1m, which are used with their source-drain paths, each have the in the conductive state Resistance value R; the other MOS transistors of the aforementioned MOS transistors used as leakage resistors each have the resistance value 2R in the conductive state. In the locked state, all of the mentioned MOS trans-

5 sistors have a resistance value greater than 10 R.

The source-drain paths of the past in the resistance ladder network at the ends of the MOS transistors T2a 'and T2n is respectively connected nor a MOS transistor T2x b w. T2y parallel with its source-drain path ^f. These MOS transistors T2x and T2y have in the conductive state between their

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Source and its sink each have the resistance value 2R.

The ^T orelektroden of the MOS transistors T2x, T2y and T1a to T1m are commonly connected to a negative voltage leading connection point -U1. If those of the depletion type with a p-channel are used for these MOS transistors, the relevant MOS transistors are conductive when a potential difference is present at their source-drain path.

Those with their one main electrode - source or sink - with one and the same main electrode - source or sink - one of the forming the transverse resistances of the Vidarstands ladder network MOS transistors T1a to T1m connected MOS transistors T2a, T2a 'or T2b, T2b' to T2n, T2n '- one of which to the one Group of bleeder resistors forming MOS transistors and the others belong to the second group of bleeder resistors forming MOS transistors - are with their gate electrodes at the outputs of an associated control circuit St1, St2 to Stn connected. These control circuits St1, St2 to On the input side, the bits of the digital signal to be converted into an analog voltage are fed to Stn, specifically at input connections el or e2 or en »

The control circuits St1 to Stn are jiveils in the present case formed by two inverters connected in series made by MOS transistors; these are the MOS transistors Ti11, Ti12 or Ti21, Ti22 or Tin1, Tin2, which can be of the enrichment type with p-channel. The source-sink routes of this MOS transistors are each in series with a load resistor used MOS transistor TU 1, T112, T121, T122, Tln1 or Tln2 between a terminal -U1 carrying a negative voltage and one carrying a positive voltage Connection point + U2. The last-mentioned MOS transistors here are of the depletion type with p-channel, in order to achieve the full at the connection point -U1 voltage present at the gate electrode of the particular to be controlled MOS transistor of the MOS transistors T2a, T2a 'to T2n, T2n · available. The gate electrodes of one

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MOS transistors, namely the MOS transistors Ti11, Ti21 or ". Tin1 in the individual control circuits St1 or St2 or" Stn are directly connected to the input connections el, e2 and en. The gate electrodes of the respective control circuit St1, St2 to Stn still belonging and as used in inverters MOS transistors Ti12, Ti22 to Tin2 are on the Connection point of the source-drain path of the MOS transistor forming the respective other inverter of the relevant control circuit Ti11 or Ti21 or Tin1 and the associated a MOS transistor T111 or T121 forming a branch resistance or Tln1 connected. The sink electrodes each to a control circuit St 1 or St2 / or. Stn belonging and I'OS transistors each forming an inverter are with connected to the orelectrodes of the two MOS transistors, which act as leakage resistors of the Y / resistor ladder network with their source-sink lines each with one and the same electrode of a cross resistance of the relevant MOS transistor forming a resistor ladder network are connected. ·

In connection with the control circuits previously considered St1 to Stn should also be noted that, in deviation from the above-explained relationships, possibly also in the following manner can have proceeded: The gate electrodes with their source-sink lines at a common electrode of a transverse resistor of the MOS transistor forming the resistor ladder network - and acting as leakage resistors MOS transistors can each be connected to a control circuit in which the bit of the bit to be converted digital signal for direct control of the gate electrode of one of the mentioned MOS transistors and via a single one Inverter for controlling the gate electrode of the other of the mentioned

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!.! OS transistors is used.

The MOS transistors forming a leakage resistance of the resistor ladder network in each case for the second group belonging MOS transistors T2a, T2b to T2n are with their ends which are opposite the ends with which the relevant MOS transistors with which the shunt resistances of the 7 / resistance chain conductor network imagesTlaOS transistors T1a until Tim are connected, jointly connected to a line to which a certain potential can be applied. With the The line concerned is in the present case two through MOS transistors formed voltage divider connected to their respective tap. The two voltage dividers s + ellen, as will become clear, separate potential sources which can be effectively switched alternatively. The one voltage divider comprises the two KOS transistors T3o and T3u; these MOS transistors can be those of the enhancement type with p-channel

be. The other voltage divider comprises the two MOS transistors T4o and T4u; these MOS transistors may be of the p-channel enhancement type. The one voltage divider forming MOS transistors T3o and T3u are with their source-drain paths in series between the one negative Live connection point -U3 and earth connected. The MOS transistors belonging to the other voltage divider T4o and T4u are with their source-drain paths in series between the connection point carrying a positive voltage + Ü2 and ground connected. The connection points of the source-drain lines belonging to the two voltage dividers MOS transistors T3o, T3u, T4o, T4u are connected to one another. The gate electrodes each belong to a voltage divider MOS transistors are also connected to one another. The gate electrodes of the MOS transistors T3o and T3u are directly on one Singangsanschluss possibly connected; the gate electrodes to the other voltage divider

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belonging MOS transistors are also connected to one another. The gate electrodes of the MOS transistors T3 ° and T3u are connected directly to an input terminal ev; the gate electrodes of the MOS transistors T4o and T4u belonging to the other voltage divider are connected to the drain of a MOS transistor Tv operated as an inverter, the source of which is connected to ground and the gate electrode of which is connected to the aforementioned input terminal ev. The sink of the MOS transistor Tv, which can be of the enhancement type with p-channel, is connected to a voltage terminal -U4 carrying a negative voltage via a MOS transistor TIv which is used as a load resistor and which can be of the depletion type with p-channel. The input connection ev is supplied with a bit of the digital signal to be converted, which is to be loaded as a sign bit, provided that the respective digital signal, in addition to the amplitude of a corresponding analog signal, also has a polarity or sign of this analog signal specifying bit includes.

After the structure of the circuit arrangement shown in the drawing has been explained according to the invention, let us now consider the operation of this circuit arrangement in more detail.

In the absence of an input signal at the input connections el to en - which corresponds to the absence of "1" bits and thus the presence of "O" bits - let the MOS transistors Ti12 or Ti22 or Tin2 be in the individual control circuits St1, St2 or Stn conductive. An "O" bit is formed here by a positive voltage and a "1" bit by a negative voltage. This means that all of the MOS transistors T2a ', T2b ^! or T2n ^f conductive. Occurs at one of the entrance ports

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e1, e2 to en have a "1" bit, the MOS transistor Ti11 or Ti21 or Ti2i or Tin1, which is respectively directly controlled thereby, becomes conductive. As a result, the MOS transistor operated as an inverter directly controlled by this MOS transistor and also operated as an inverter - which was previously in the conductive state - is converted into the non-conductive state. This means that the gate electrode connected to this last-mentioned MOS transistor, the MOS transistor of the first group of MOS transistors T2a 'to T2n ^r, each forming one leakage resistance, becomes non-conductive. For this, however, the MOS transistor connected to the second group of MOS transistors T2a to T2n each forming a leakage resistor, connected together with this MOS transistor with the same electrode of a MOS transistor forming a transverse resistance of the resistor network, is controlled to be conductive. As a result, a certain voltage is applied to the connection point, for example A, of the source-drain path of this MOS transistor with the MOS transistor in question, which forms a transverse resistance of the resistance conductor network. This voltage is reduced by a factor of 2 from connection point (e.g. A) to connection point (e.g. B) due to the MOS transistors of the resistor ladder network, which are in the conductive state.

The polarity of the jev / hasty connection point A, B to M two each as leakage resistors of the resistor ladder network serving MOS transistors such as the MOS transistors T2a and T2a ', and at least one of a transverse resistor forming MOS transistor, such as the MOS transistor T1a * depends on which of the two voltage dividers mentioned above is effectively switched. Which one? of the two voltage dividers are effective is switched depends on whether an "0" bit or a "1" bit occurs at the input connection ev

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"O" bit on - that is a positive voltage in the present case - the MOS transistors Tv and T3o, T3u should be blocked; in this case the IiOS transistors T4o, T4u are conductive, whereby there is a positive voltage on the line connected to their sink-source lines. However, kick at the input connection ev a "1" bit - that is a negative voltage in the present case - so the MOS transistors Tv and T3o, T3u be in the conductive state. In this case, the MOS transistors T4o, T4u are non-conductive State. This means that there is now a negative voltage on the aforementioned line.

With regard to the circuit arrangement shown in the drawing Finally, it should be noted that this only consists of MOS transistors that are directly connected to one another. In order to the circuit arrangement in question is ideally suited for a full integration. As already mentioned at the beginning, the circuit arrangement in question can also in an analog signal-to-digital signal converter operating according to the iterative method with built-in, in such a way that a only dirch a single monolithic integrated circuit realized analog signal-digital-signal converter is present, in which inter alia the circuit arrangement according to the invention is included.

For the operation of the circuit arrangement according to the invention explained above, the following voltages have been used: An the node -ΪΓ1 a voltage of -24V, at the node + U2 a voltage of + 5V, at the node -U3 a voltage of -5V and one at node -U4 Voltage of -12V.

For the MOS transistors, deviating from those explained Conditions of the other type as well

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and / or the other channel can be used; in this This case results in a corresponding change in polarity and, if necessary, in the level of the voltages to be provided.

Regarding the voltage that the gate electrodes of the leakage resistors in the MOS transistors forming the resistor ladder network ? 2a to T2n and T2a * to T2n 'is to be supplied, is final also noted that the aim is to select this voltage to be relatively high; the higher this voltage / can be chosen, namely, the easier the linearity requirements are with regard to the control of the said MOS transistors over a large working range to meet.

10 claims

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Claims (10)

24231 Sponsorship claims f1) / circuit arrangement for converting digital signals consisting of individual bits, in particular PCM signals, into analog voltages corresponding to these, using a resistor ladder network consisting of series-connected cross resistors and leakage resistors connected to them, whose cross resistances each have a Y / have resistance value R and its bleeder resistors each have a resistance value 2R, where a voltage corresponding to the bits of the respective digital signal can be applied to the ends of the lead it v / i of the stands opposite the ends connected to An analog voltage corresponding to the respective digital signal can be taken from the connection point of a lead resistor and at least one transverse resistor, characterized in that all resistors of the 7 / resistor ladder network are formed by the source-drain paths of MOS transistors of which the MOS transistors (T1a to T1b) forming the transverse resistances are always in the conductive state and with their source-drain paths each have a resistance value of R and of which the MOS transistors (T2a, T2a , T2b, T2b 'to T2n, T2n') in the conductive state with their source-drain paths each have a Y / resistance value of 2R, that the leakage resistances of the V / resistance ladder -; ^ '-. Network-forming MOS transistors (T2a, T2a ·, T2b, T2V to T2n, T2n ') form two groups of MOS transistors, of which the MOS transistors (T2a * to T2n ^f ) of a group of. MOS transistors with their ends facing the ends VPA 9/610/4185 - 16 - 3847/0643 opposite, which with the transverse resistances of the Vrid Resistance ladder network forming MOS transistors (T1a to T 1m) are connected at a fixed potential lie and of which the MOS transistors (T2a to T2n) of the second group of MOS transistors with their ends that the Opposite ends with which the cross resistances of the MOS transistors (Tiabis T1m) forming the resistor ladder network are connected on a specific different potential, and that each with its one electrode on one and the same electrode has a transverse resistance of the resistance chain ladder network MOS transistor (e.g. T1a) connected MOS transistors (e.g. T2a, T2a ') of both groups of MOS transistors with their gate electrodes are connected to alternatively activated outputs of a control circuit (St1, St2, Stn), the one bit of the respective digital signal can be supplied on the input side. 2) Circuit arrangement according to claim 1, characterized in that the control circuits (St1, St2 to Stn) each contain two inverters connected in series, at the outputs of which the gate electrodes of the deiJMOS transistors (e.g., T2a, T2a ') are connected, which are connected together one and the same electrode one as the transverse resistance of the MOS transistor (T1a) serving as a cross resistance of the resistor ladder network, and that one bit of the respective digital signal can be fed to the first inverter j in the series circuit. 3) Circuit arrangement according to claim 2, characterized in that the inverters are formed by MOS transistors (Ti11, Ti12j, Ti22; Tin1, Tin2). VPA 9/610/4185 - 17 - 509847/0643 4) Circuit arrangement according to claim 3, characterized in that load resistors formed by MOS transistors (TU 1, T112; T121, T122; Tn1, Tn2) are connected in series with the sink-source paths of the MOS transistors forming the inverters. ■> 5) circuit arrangement according to claim 4, characterized in that that the MOS transistors forming said load resistances are formed by MOS transistors of the depletion type. 6) Circuit arrangement according to one of claims 1 to 5, characterized in that upon the occurrence of digital signals indicative of next to the amplitude of a corresponding them analog voltage bits still at least one polarity "include that voltage indicative ^v orzeichenbit that beEfcLmmte other potential two potential sources, which are activated alternately by the sign bit and which supply potentials of different polarity. 7) Circuit arrangement according to one of claims 1 to 6, characterized in that the one lying at the ends of the resistor ladder network, each a leakage resistor forming MOS transistors (T2a 'T2n') each have an additional, always in the conductive state MOS transistor (T2x, T2y) is connected in parallel with its source-drain path, which has a resistance value 2R in the conductive state of this MOS transistor. 8) Circuit arrangement according to one of claims 1 to 7, characterized in that the transverse resistances of the resistor ladder network forming MOS transistors (T1a to T1m) are formed by MOS transistors of the enhancement type. VPA 9/610/4185 - 18 - 503847/0643 9) Circuit arrangement according to one of claims 1 to 8, characterized in that the MOS transistors forming the leakage resistors of the chain conductor network are formed by MOS transistors of the enhancement type. 10) Circuit arrangement according to one of claims 1 to 9, characterized in _t that all the MOS transistors are contained in- a common integrated circuit. VPA 9/610/4185 509847/0643