DE2418969A1 - Regenerating and rating cct with flip-flop - has transverse transistor and stages consisting of switching transistor and load element - Google Patents

Abstract

Parallel to each switching transistor there is a driver transistor. A gate connection of each driver transistor is connected to a bit line. There are switching means which are used to separate the parallel connection of the driver transistors and these switching means are controlled together with the transverse transistor. The switching means can consist of transistors, each of which is connected in series to a driver transistor, in which case the gate terminals of the transistors are connected to the gate terminal of the transverse transistor.

Description

Regeneration and Evaluation Circuit The invention relates to a Laying generation and evaluation circuit according to the preamble of claim 1.

Regeneration circuits of this type are known. In the publication v. K. U. Stein, A. Sihling, and E. Doering, "Storage Array and Sense / Refresh Circuit for Single Transistor Memory Cells ", in IEEE Journal of Solid State Circuits SO-7, 1972, pp. 356-340 are such regeneration circuits, as for example for One-IPransi stor storage elements are required, described. they consist of a flip-flop, in which one switching transistor in each flip-flop branch and a load element is arranged in each case, in which the two flip-flop nodes through a cross transistor are connected to one another, and in each of which one bit line is connected to a respective flip-flop node. There is one load element in each case each of a field effect transistor, the gate of which is connected to the drain connection is electrically connected.

In the first phase of the switching process of the flip-flop, in which the Evaluator should begin to tilt according to the information read out the difficulties listed below. After setting the reference state, which is achieved by switching the transverse transistor on, and the one on it then isolating the bit lines by switching the supply voltage is reached, the initial state is obtained after the selected memory element has been read out of the flip-flop reached before the evaluation.

This state can occur for a short time on the bit line capacitances cached and should the flip-flop to flip into the information corresponding to the read out Initiate direction if this is done by reapplying the supply voltages is activated.

However, as shown by experimental tests on integrated circuits may have due to the small size of the single transistor memory element available Charge, the setting of a unique starting condition for the flip-flop to flip be critical. Since the current consumption of such a flip-flop in static operation is relatively large, and additionally the flip-flop due to the unavoidable parameter spread of the components has a preferred position, there is the possibility that the output signal of the storage element is covered by the switch-on signal of the flip-flop. this has the consequence - that the flip-flop tilts on the wrong side.

In addition, there is an undesirable dependency both on the reference voltage, as well as the switch-on signal of the flip-flop from the temporal phase of the flip-flop control clocks.

One object of the invention is to provide a regeneration and evaluation circuit indicate the case of increased sensitivity and increased switching speed offers a mode of operation that is uncritical with regard to the tilting of the flip-flop.

This task is solved by a regeneration and evaluation circuit, according to the invention by those listed in the characterizing part of claim 1 Features is marked.

A major advantage of the invention is the greater sensitivity, through steepening of the flip-flop characteristics, also in the case of one as a result of parameter variance unbalanced flip-flop.

Another advantage of the invention is the shortening of the switching times.

Further explanations of the invention and its configurations go from the description and the figures.

Figure 1 shows the circuit diagram of a regeneration according to the invention and evaluation circuit.

FIG. 2 shows the family of characteristics of an asymmetrical flip-flop.

FIG. 3 shows a further regeneration and evaluation circuit according to the invention.

FIG. 4 shows the clock program for the circuit of FIG. 3.

Figures 5 and 6 show developments of an inventive Regeneration and evaluation circuit.

The flip-flop of the regeneration and evaluation circuit according to the figure 1 consists essentially of the two switching transistors 32 and 42 and the load resistors 31 and 41. The switching transistors and the load resistors are preferably field-effect transistors, especially MOS transistors are used. The gate connections are the load transistors 31 and 41 can be controlled jointly via connection 11. The source electrodes of both load transistors are connected to input 8. Between nodes 1 and 2 of the The cross transistor 5 is arranged in a flip-flop circuit. Preferably it is in this transverse transistor 5 also un a field effect transistor, in particular a MOS transistor, the gate electrode of which can be controlled via the connection 511 is. The gate connection of the switching transistor 32 is connected to the node 2 and the gate connection of the switching transistor 42 is connected to the Knten 1.

The supply voltage VDD lies between points 8 and 9 of the Circuit on.

According to the invention, the two bit lines 10 and 2U are over Driver transistors 33 and 43 are connected to nodes 1 and 2 of the flip-flop for this purpose the bit line 10 to the gate terminal of the driver transistor 33 and the bit line 20 connected to the driver transistor 43. The drain connections of the driver transistors are connected to the flip-flop node. The three terminal of transistor 52 is connected to connected to node 1 and the drain terminal of transistor 43 to node 2. Between the Sourcesushluß of the transistor 33 and the point 9 is a switching means, preferably the transistor 34, arranged in the manner shown in the figure. Between the radio 9 and the Sonroeansthluß of the transistor 43 is also a Switching means, preferably the transistor 44 in the one shown in the figure Way, arranged. The gate terminals of transistors 34 and 44 are in the point 511 summarized. With the help of the transistors 34 and 44, the parallel connection the driver transistors 33 and 43 are canceled.

According to the invention, the driver transistors 35, 43 after reading of a storage element by the potentials corresponding to the information read out on bit line 10 or

20 put into different conductivity states, whereby the flip-flop branches 5 or 4 are loaded differently. The difference in load is proportional the potential difference between the bit lines 10 and 20 and is the initial state, starting from which the flip-flop can tilt9 is suitable.

According to the invention are advantageous over the previously known Method memorized the initial conditions for tilting the flip-flop, since the Readout signal of the storage element not covered by the inrush current of the flip-flop can be.

A dependency of the differential voltage and the switch-on signal of the flip-flop from the temporal phase of the control clocks therefore does not occur.

In the following, with reference to the state diagram shown in FIG an unsyumetric flip-flop, the solution to sensitivity can be explained. An unbalanced flip-flop is present when in the circuit after of Figure 1, the transistors 5, 34 and 44 are blocked. This means that on that There is no potential at connection 511. In the diagram corresponding to this state The dividing line shown in dashed lines and designated by 60 coincides with FIG of the flip-flop states (separatrix) due to the electrical asymmetry of the flip-flop branches 3 and 4 not with the straight line 6i. The separation of the state field works in the way that every initial state of the evaluation that comes to lie in the area Q, that Flip-flop after S1, while a state in area P causes the flip-flop to flip after S2. The characteristics x and y are decisive for this.

By switching on the transistor T5 alone, the state M would be assumed which is in the @ eld P state. This would mean that when reading out of the memory element appearing on the bit line signal of at least the size Vtr / 2 would have to be in order to obtain an output state in the other state field Q.

By connecting the driver transistors in parallel according to the invention 53 and 43 to the switching transistors 32 and 42 of the flip-flop results in a steepening the flip-flop characteristic lines. X becomes x 'and y becomes y'. At the same time results; themselves a reduction in size Vtr / 2 to (Vtr / 2), which shifts the straight line 60 (separatrix) in the direction of M '(straight line 60) and thus a reduction in the Rating threshold means.

In the evaluator and according to the invention shown in FIG In contrast to the circuit according to FIG. 1, regeneration circuits are also additional two inverters 35 and 45 are provided. With the help of this inverter can under use the bootstrap effect achieves a fast switching behavior of the regeneration circuit will. The bootstrap effect is in the @@ iminating Threshold Losses publication in MOS Circuits by Bootstrapping Using yaractor Coupling v. RE.

Joynson, J.L. Mundy, J.F. Burgess and C. Neugebauer in IEEE Journal of Solid State Circuits SC-7, 1972, pages 217-223 in detail. details 5, which have already been described in connection with FIG. 1, tra & ien the corresponding reference numerals.

The bootstrap effect is essentially that be one conductive field effect transistor whose drain terminal is clocked, as a result of the a field effect transistor's own gate capacitance, the gate through capacitive coupling is clocked at the same time. This effect is beneficial for Leitand control of a field effect transistor, with one being applied to the drain terminal increasing control voltage is coupled to the gate via the gate capacitance, so that the Cates voltage is increased, whereby the conductivity of the field effect transistor increases. This effect is increased by putting in parallel the gate capacitance between the gate and drain connections are arranged by a field effect transistor.

The inverter 35 consists of the switching transistor 57, the load transistor 38 and the bootstrap coupling capacitor 39. The inverter 45 consists of the switching transistor 47, the load transistor 48 and the bootstrap coupling capacitor 49. In the from As can be seen in the figure, the gate of the switching transistor 57 of the inverter 55 is or the gate of the switching transistor 47 of the inverter 45 with the node 1 and with connected to node 2 of the flip-flop. To the switching transistor 57 is another Switching means connected in series. For example, there is this further switching means from the transistor 36, which is connected to the point 9 with its source terminal. The gate of this transistor 56 can be controlled via the connection 362 A further switching means is provided at the inverter 45. For example, the Source terminal of the transistor 46, which is connected in series with the switching transistor 47 is connected to the terminal 9. The gate of this transistor 46 is also controllable via the connection 362 The node f71 of the inverter 55 is in the off the way shown in the figure with bit line 10 and the node 471 of the inverter 45 is connected to the bit line 20. The transistor 58 of the inverter 35 has its drain connection to the connection 362 and to its source connection connected to node 371. The gate of load transistor 38 is to the node 2 of the flip-flop connected. Between the gate of the load transistor 38 and the source terminal of the load transistor 38 is the bootstrap coupling capacitance 39. In the corresponding Way is with the inverter 45 of the load transistor 48 with its source terminal connected to the node 471 and with its drain connection to the connection 562. That The gate of load transistor 48 is connected to node 1 of the flip-flop. Between is the gate of load transistor 48 and the source of load transistor 48 the bootstrap coupling capacitance 49 switched.

Since flip-flop nodes 1 and 2 are connected to the gates of inverters 35 and 45, i.e. with the gate connections of the transistors 37 resp.

47 are connected, the transistors are turned on during the flip-flop flip-flop this inverter switched.

The following describes the mode of operation in connection with FIG of the evaluation and regeneration circuit according to the invention according to FIG. 3 will. First, at time t1, the flip-flop is activated by applying the potential # 311 is switched on to terminal 511 and the transverse transistor 5 is switched on by applying the Potential # 511 switched to the terminal 511 conductive. Up to time t2 are the transistors 21 and 22 by applying the potential # 25 to the input 23 switched on, which has the effect that the reference voltage Uref 'at the input 24 is applied, is stamped on the bit lines 10, 20. The component spread of the Switching transistors 21 and 22 go with a correspondingly long duration of the clock # 511 advantageously only very slightly in the reference potentials (precharge voltages) of the bit lines, since the conductivity of the transistors 21 and 22 only changes the time constant of the precharge process.

At the time t2, the transistors 21 and 22 are now over the entry 23 blocked by the fact that the potential # 23 is separated from the input 23. This has the effect that the reference voltage Uref is separated from the bit lines 10 and 20 will.

At time t3, the transistor becomes, for example, via word line 16 22 of the one-transistor memory element 11 is switched on. This flows the Information contained in the capacitor 13 of this memory element is transferred to the bit line 10. As indicated in FIG. 4, the embossed on the egg line 10 is thereby Voltage Uref changes, while the voltage Uref preserved. At time t4, the transverse transistor is switched off by switching off the @@ entiales @ 511 blocked to input 51 @. This causes dis transistors 5, 34, 44 are placed in the blocking state. It follows that how Shown in the figure #, the plip-flop tilts into one of its stable Lagan. Therefor the curve masts 70 and 72 are in the water. The tension is then on the note 1 U1 and the voltage U2 at the enotes 2.

With the help of the additional inverters 35 and 45 is used the bootstrap effect a faster switching behavior of the regeneration and bad value circuit reached (characteristic curves 71 and 73). Since the flip-flop nodes 1 and 2 are connected to the gates of the Inverters 35 and 45, more precisely the node 1 with the gate of the transistor 37 and the enotes 2 are connected to the gate of the switching transistor 47, are during when the flip-flop flips over, the transistors of these inverters are switched. If e.g.

U1 decreases and U2 increases, the transistors 37 and 48 block, the transistors 47 and 38 become conductive. This is in the bootstrap coupling capacitor 39 of the load transistor 38 creates an inversion layer so that by applying clock # 362 to the Terminal 362 (time t5) the bit line 10 is switched up by means of the bootstrap effect can be. At the same time the load transistor 48 is saved and the clock # 362 cannot couple due to the lack of an inversion layer on the coupling capacitor 49. The bit line 20 lies across the switching transistor which is conductive from the flip-flop with the voltage U2 47 and during the Clock # 562 Conductive transistor 47 on Dimensions.

The circuit in FIG. 5 shows a further possibility, the reference potentials to be applied to the bit lines (precharge).

For this purpose, there are each between a bit line and a flip-flop node Transistors inserted. Between the flip-flop node 1 and the bit line 10 is the transistor 52 in the manner shown in the figure and between the bit line 20 and the node 2 of the flip-flop, the transistor 53 is inserted.

Both transistors can be controlled jointly via input 54. The reference potential is determined here by the W / L ratios of inverters 5 and 4. The W / L ratio is the ratio of the channel width W to the channel length L understood a field effect transistor, which is a measure of the conductivity of the Transistor is.

The reference potential is when the clock pulse 311 is applied to the terminal 311 or of the clock 511 to the terminal 511 generated by voltage distribution, wherein the series connection of transistors 31 and 32 or 41 and 42 as a voltage divider works.

That generated in this way by dividing the supply voltage VDD The reference potential is made conductive by switching the transistors 52 and 55 with the Clock 54 impressed on bit lines 70 and 20. The cycle 54 is subsequently again switched off, so that the bit lines 10, 2U from the nodes 1 and 2 are electrically again lying separately. The rest of the operation runs according to the clock program in FIG 4 starting at time t3.

With this method of impressing the reference potentials on the bit lines 10 and 20, the component spread of the transistors 51 and 32 and 41 and 42 is significant more one than in the circuit of Figure 3, so that saving an external Reference source and the switching means 21 and 22 in Figure 5, a loss of sensitivity facing.

According to a development of the invention, the transistors 56 and 46 and / or the transistors 54 and 44 combined will. A regeneration and evaluation circuit, be the transistors 36 and 46 and 34, respectively and 44 are each reduced to one transistor. FIG. 6 shows the switching means The transistor 441 serves here, which with its source connection with the source connections of the switching transistors 32 and 1.2 and with its drain connection to the switched together Source terminals of the driver transistors 33 and 43 is connected.

The gate terminal of the transistor 441 is connected to the gate terminal of the Cross transistor 5 connected.

The further switching means can also consist of a transistor 361, the one with its source connection with the source connections of the switching transistors 52 and 42 of the flip-flop and with its drain connection to the interconnected source connections the switching resistors 7 and 47 of the inverters 55 and 45 are connected. The gate terminal of transistor 361 is connected to terminal 362.

The particular advantages of the circuits described lie in their memorization the initial condition for toggling the flip-flop at the flip-flop node, as in FIG Significant shortening of the schitzzeit when regenerating the information "1". Of the Additional expenditure on switching elements and connection lines is achieved through the gain of a smaller evaluation threshold justified, since according to an advantage of the invention a larger number of memory elements are connected to one and the same bit line than was previously possible.

8 claims 6 figures

Claims (8)

P a t e n t a n s p r ü c h e 1. Regeneration and evaluation circuit with a flip-flop with two feedback inverter stages, each of which consists of one Switching transistor and a load element designed as a transistor exist, and with a transverse transistor between two flip-flop nodes, d u r c h e k e n n n z e i c h n e t that in each case a driver transistor in parallel with a switching transistor (32, 42) (33, 43) is arranged that a gate terminal of each driver transistor (33, 43) is each connected to a bit line (10, 20) that a switching means 934, 44, 441) is provided, with the help of which the parallel connection of the driver transistors is separable, the switching means 934, 44, 441) together with the transverse transfer (5) is controllable. 2. regeneration and evaluation circuit according to claim 1, characterized g e it is not indicated that the switching means consists of transistors (34, 44), one transistor (34 or 44) in series with a driver transistor (33, 43) is connected, and the gate terminals of transistors 934 and 44) with the gate terminal of the transverse transistor (5) are connected. 3. regeneration and evaluation circuit according to claim 1, characterized ge k e n n n z e i c h ne t that the switching means consists of a transistor (441), that this transistor (441) with its source connection with the source connections of the switching transistors (32, 42) and with its drain connection with the interconnected Source terminals of the driver transistors (33, 43) is connected and that the gate terminal of the transistor (441) is connected to the gate terminal of the transverse transistor (5). 4. regeneration and Pewerterschaltung according to claim 1, characterized g e k e n n n z e i c h n e t that two inverters (35, 45) each with one Switching transistor (37, 47), a load element (38, 48) designed as a transistor and a bootstrap Capacitor (39, 49) are provided that further switching means (36, 46, 361) are provided, with the aid of which the inverter (35, 45) can be switched on and off, that in each case a switching transistor (37, 47) of the inverter with its drain connection each with a bit line (10, 20) and with the source terminal is connected to the further switching means (36, 46, 361) that the further switching means with the source connections of the switching transistors (32, 42) of the flip-flop is connected so that the switching means can be controlled via a connection (362) is that the gate of the switching transistor (37) of the inverter (35) with the Node (1) of the flip-flop and the gate terminal of the switching transistor (47) of the inverter (45) is connected to the node (2) of the flip-flop that the designed as a load element Fransistor (38 or 43) with its source connection to the bit line (10 or 20) and its drain connection is connected to the connection (362) that the gate connection of the transistor (38 or 48) designed as a vice element with the opposite side Node (2 or 1) of the flip-flop is connected, and that between the get connection and the drain connection of the transistor (38 or 48) designed as a load element the beststrap coupling capacitance (39 or 49) is provided. 5. regeneration and evaluation circuit according to claim 4, characterized g e -k e n n n z e i c h n e t that the further switching means consists of transistors (36 or, 46), with one transistor (36 or 46) in series with a switching transistor (37 or 47) of the inverter (35 or 45) is switched, and mobei the Cateau connections dar both transistors (36 and 46) are connected to one another. 6. regeneration and evaluation circuit according to claim 4, characterized g e - indicates that the further switching means consists of a transistor (361), that this transistor (361) with its source connection with the sonr connections the switching transistors (32, 42) of the flipf @@@ and with its drain connection with the shattered the S @@@@ shot the Rel @@ widerst @@@ e @@@@@ which is @@@@ @@@@@@@@ is and that the Gate connection of the transistor (361) to the connection (362) ... is connected. 7. regeneration and evaluation circuit according to one of claims 1 to 6, by the fact that two transistors are used for precharge (21, 22) are provided, the drain connection of a transistor (21 or 22) is connected to a bit line (20 or 10) that the two source connections of the transistors (21, 22) are connected to one another at a point (24), wherein at this point (24) the reference voltage Uref is applied, and that the two transistors (21, 22) can be controlled jointly via a connection (2) 8. Regeneration and evaluation circuit according to one of claims 1 to 6, characterized in that the Precharge transistors (52, 5 ») are provided, the transistor (52) with its drain connection to the bit line (10) and with its source connection is connected to the node (1) of the flip-flop and that the transistor (55) with his Drain connection to the bit line (20) and its source connection to the node (2) of the flip-flop is connected and that the transistors (52, 5n) are common across a connection (54) can be controlled.