DE2418936C3 - Regeneration and evaluation circuit with a flip-flop and method for its operation - Google Patents

Description

IU ₀ = (

- U ₀ ) ^

This information voltage swing is calculated for the binary "1"

11 /, = U ₁ - u _Rl .j ■ _c ^ -

The invention relates to a regeneration and evaluation circuit according to the preamble of the patent claim 1 or claim 2.

In equations 1 and 2, Cs is the storage capacity, Ce is the bit line capacity, and U \, Uo is the information voltage in the memory cell. The evaluation is carried out by comparing the two node voltages. For an equally good evaluation of the binary “0” and the binary “1”, the voltage swing should therefore be Δ U \ = Δ LO. Equations 1 and 2 give the reference voltage:

LW = 1/2 ((7, + Ο,)

This voltage can be adjusted with known circuits

.15 do not set, since after the closing of the transverse transistor the two nodes discharge to ground until the threshold voltage Uj of the switching transistors of the evaluator is reached. This is usually around 1 V, while a more favorable reference voltage is around 4 V, for example. The result is that the binary "0" is badly evaluated in known circuits.

Since the signal available on the bit line is very low after reading out, it is desirable to amplify this signal before regenerating. The one according to the invention Regeneration and evaluation circuit achieved by the additional transistor gain effect can, independently on the size of the readout signal of a binary "1", the amount LW can reach, while with known ones Preamplifications a certain gain of the output swing is achieved.

The object of the present invention is to provide a circuit that, compared to

ss the known regeneration and evaluation circuits has a significantly higher sensitivity.

This object is achieved by a regeneration and evaluation circuit as mentioned at the beginning, by the in the characterizing part of the claim

do 1 or 2 listed features is marked.

An advantage of the regeneration and evaluation circuit according to the invention is that when activated of the transverse transistor between the two bit line capacitances during the charging process

(> s discharge to ground can take place because the additional transistor is locked at this moment.

Another major advantage of the invention is that when you turn on the additional transi-

store a pre-amplification, described in more detail below, becomes effective, through which a high Interference immunity can be achieved during operation

Further explanations of the invention and of its configurations can be found in the figures and in FIG Description of the invention and its developments. the

F i g. 1 shows the circuit diagram of a first regeneration and evaluation circuit according to the invention; the

FIG. 2 shows the clock program for explaining the mode of operation of the circuit according to FIG. 1; the

F i g. 3 shows the circuit diagram of a further development of the circuit according to FIG. 1; the

F i g. 4 shows the circuit diagram of a second regeneration and evaluation circuit according to the invention.

The flip-flop of the regeneration and evaluation circuit according to FIG. 1 consists essentially of the two switching transistors 32 and 42 and the load resistors

31 and 41. Preferably used as switching transistors are field effect transistors, the load resistors 31 and 41 are also preferably field effect transistors, the gate terminals of these transistors are controlled together via the terminal 311th The source electrodes of both load resistors are connected to the supply voltage VOo via the common terminal 8. Between nodes 1 and 2 of the regenerate.! In the device that are connected to the bit lines 10 and 20 , the transverse trans, disruptive 5 is arranged. This transverse transistor 5 is preferably also a field effect transistor, the gate electrode of which can be controlled via the connection 51. The gate connection of the switching transistor

32 is connected to node 2 and the gate connection of switching transistor 42 is connected to node 1.

The two source connections of the switching transistors 32 and 42 are electrically connected at point 9. According to the invention, the additional transistor 14, which can be controlled via the connection 141, is arranged between this point 9 and the connection 7, which represents the second connection to the supply voltage V >> . Preferably, the transistor 14 is also a field effect transistor. The supply voltage Von is applied between terminals 7 and 8.

MOS field effect transistors are preferably used as transistors 31, 32, 41, 42 and 14.

1 also shows a one-transistor memory element 21, which consists of the field-effect transistor 22 and the capacitor 23 connected in series therewith. The gate of the selection transistor 22 is connected at the point 27 to the selection line 26 and can be controlled via this.

In the following, in connection with FIG. 2, the mode of operation of the regeneration and evaluation circuit according to the invention according to FIG. 1 to be described. First, the transverse transistor 5 is switched via the terminal 51 with the clock φ 51 at the time fi. At this time, the auxiliary transistor according to the invention is locked 14, it is achieved that when activating the cross transistor 5 with the clock Φ 51, a charge-reversal between the two parasitic bit line capacitances 101 and 201 takes place, wherein on the bit lines, the ideal reference potential

Urcf = 0.5 (i / s', +)

sets, since no discharge to ground via the two switching transistors 32 and 42 can take place because of the blocked additional transistor 14. The value _re U r is achieved only approximately, since the parasitic source-drain capacitance 142 of the auxiliary transistor 14 to the voltage IM = £ / 10/20 - t / must be loaded up.

In the formulas given above, L / »and L / st denote the voltages present on the bit lines 10 and 20 at the time fc after the flip-flop has flipped, and Ut denotes the threshold voltage of the switching transistors 32 and 42.

After the bit lines are now approximately charged to the potential U _re f , after the transverse transistor has been switched back to the blocking state at time t ₂ , at time ti by applying the potential Φ 26 to the selection line 26, the transistor 22 of, for example, the One-transistor memory element 21 is switched on. This has the effect that the information stored in the capacitor 23 of this storage element changes the voltage t / 20 depending on the type of this information. After the information has now been read from the memory element 21 , the additional transistor 14 is switched on at the time u with the aid of the potential φ 141 which is applied to the terminal 141. As a result, according to the invention, the source potential Uh of the switching transistors 32 and 42 falls, and the switching transistor whose gate is at a higher potential becomes conductive earlier. This causes a pre-amplification, which is briefly described below.

In FIG. 2, the reading and evaluating is one stored in the memory element 21 '<■: shown, wherein a change in voltage Δ U occurs when reading the time i3 at the bit line 20 as a read signal, where i / 20 (I ₁₎ - Urcf + AU!. As a result of the additional transistor 14 being switched on , the voltage Un drops and in this case the transistor 32 will begin to conduct when the condition Un < i / 20 (o) - Ur _{12 is} met, where Um is the threshold voltage of the acoustic transistor 32. The transistor 42 remains blocked as long as the condition Un> U \ a - Ur ₁₂ applies, where Ur _{12 is associated with} an increase in the difference Δ U ' between the potentials U \ ₀ and U ₂ I) , which means an amplification of the read signal.

After activating the flip-flop with the aid of the potential Φ 311 at the time l ·, it flips into the position corresponding to the information, whereby a higher level of immunity to interference is achieved because of the increased voltage difference at the nodes due to the preamplification.

If, as shown in FIG. 2, the potential Φ 311 is switched off at time t _b before the potential Φ 141 at time ti , the bit line capacitance previously charged to the potential Uso can still be entirely over the switching transistors and the additional transistors 14 0 volts discharged. The potential Us \ , on the other hand, is retained except for a voltage loss caused by parasitic coupling capacitances of the load transistors. This advantageously increases the distance between the information potential.

3 shows a circuit diagram of an embodiment of the regeneration and evaluation circuit according to the invention. Here the gate connections of the additional transistor 14 and the load transistors 31 and 41 can be controlled jointly via the connection 71. As a result of the substrate control effect, the additional transistor 14 becomes conductive earlier than the two load transistors 31 and 41, and the above-mentioned prediction results again.

Strengthening. The substrate control effect is understood to mean the fact that the threshold voltage is increased in a transistor if, instead of the substrate voltage U _m t, there is an effective substrate voltage U'j "(, = Usub + U) between the source electrode and the substrate. Also in the exemplary embodiment According to FIG. 3, when the clock Φ 71 is switched off, the potential t / si is retained, while the potential Uso tends to 0 volts because of the delay in the additional transistor 14 when it is switched off.

For the two circuits according to FIGS. 1 and 3 is after switching off the selection cycle Φ 26 at the time the evaluation process ended.

The F i g. 4 shows the circuit diagram of a further evaluation and regeneration circuit according to the invention. Details of Fig.4, which are already in In connection with the other figures have been described, have the corresponding reference numerals. the The circuit according to this figure shows two additional transistors 33 and 43, one additional transistor in each case each one inverter is arranged in the manner shown in FIG. The two gate connections the additional transistors 33 and 43 are on the

ίο common connection 331 can be controlled by potential Φ 331. This further regeneration and evaluation circuit according to the invention can optionally be operated with one of the two control rates described above.

For this purpose 2 sheets of drawings

Claims (5)

Patent claims: 1. Regeneration and evaluation circuit with one consisting of two cross-coupled inverter stages Flip-flop, with one inverter stage each made up of a switching transistor and a load transistor which are connected in series with one another and wherein the two inverter stages are on the load element side the first connection of the supply voltage and the switching element side to the second Connection of the supply voltage can be connected, with a transverse transistor between the two Flip-flop node, with at least one 3-bit line connected to a node of the flip-flop, characterized in that a common additional transistor (14), which is connected via the gate terminal (141) is dispersible, as switchboard side Connection of the two inverter stages to the supply voltage (7) is provided (FIG. 1). 2. Regenerating and evaluating circuit with a flip-flop consisting of two cross-coupled inverter stages, one inverter stage each consisting of a switching transistor and a load transistor, which are connected in series with one another and the two inverter stages are connected to the first connection of the supply voltage on the load element side and can be connected to the second connection of the supply voltage on the switching element side, with a cross transistor between the two flip-flop nodes, at least one bit line being connected to a node of the flip-flop, characterized in that an additional transistor (33, 43) in each of the two inverter stages is used as the switching element side connection is provided with the verso ^r supply voltage and that the gate terminals of additional transistors (F i g. 4) via a common connection point (331) can be controlled. 3. A circuit according to claim 1 with a common connection for controlling the gate connections of the load transistors, characterized in that the gate connection of the additional transistor (14) is connected to this terminal (71) (Fig. 3). 4. Circuit according to one of claims 1, 2 or 3, characterized in that the load transistors (31, 41), as switching transistors (32, 42) and as additional transistors (14, 33, 43) MOS field effect transistors are used. 5. A method for operating a circuit according to one of claims 1 to 4, characterized in that a reference voltage U _n t is set on the bit lines (10 to 20) by »Leitendw switching the transverse transistor (5) (time t \), that, after the transverse transistor (5) is turned off (time ^), the selection transistor (22) of a memory element (21) is turned on via a selection line (26), that then the additional transistor (14) or the additional transistor pair is turned on that then the load transistors (31, 41) are made conductive (time ft) and that the load transistors (31, 41) before the additional transistor (14) or the additional transistor pair (33, 43) are switched off (time it,). Such known regeneration circuits are z. B. required for one-transistor memory elements one bit line each connected to one node of the flip-flop of the regeneration circuit. In front At the beginning of the readout, a bit line is precharged to a reference potential (precharge). This process is described in detail in the literature "Electronics" Sept. 13, 1973, pages 116 to 121. To evaluate the information in the memory elements, it is necessary to precharge the bit line to a reference voltage Uref before reading it out. The information voltage swing AUu AUa on the bit line is calculated for the binary "0"