DE2414239B2 - Method and apparatus for compressing a binary information sequence - Google Patents

Description

The invention relates to a method for compressing a binary information sequence which was obtained by scanning a graphic template line by line and from groups one in each case the same large number of bits, in which the individual groups are checked to see whether they are only bits of the first type (e.g. logical ZERO) or at least one bit of the second type (e.g. logical ONE) and at in which a group identifier bit is generated which distinguishes the two possible cases, in which further when the first case occurs (namely: the group only contains bits of the first type) representing the entire group Group only the flag bit is generated, and when the second case occurs (namely: group contains at least one bit of the second type) a further subdivision of the group into blocks of bits one the same number is made in each case, which are individually checked to see whether they are only bits of the first Type or at least one bit of the second type, and in which a block identifier bit for each block is generated which distinguishes the two possible cases, in which, furthermore, when the first case occurs (namely: the block only contains bits of the first type), only the block identifier bit representing the block is generated and in which when the second case occurs (namely: group contains at least one bit of the second type) the block is accepted unchanged in addition to the block identifier bit.

In DE-OS 15 12 654 a method for compressing a digital pulse train is described, in which the incoming pulse train is broken down into groups of 64 bits each. Each group will respond examines whether it is only white information (for example, logical ONE) or at least black information (for example, logical NULL). A group identifier bit is used for the group examined in this way that distinguishes the two specified cases. If the entire group only contains white information, in this way, only the identifier bit for this group is transmitted as a representative in the coded pulse train. Is in If this group also contains black information, the group is further subdivided into Subgroups of 16 bits each, which in turn are examined to see whether they are only white information or contain at least one piece of black information. For each such subgroup there is a separate one Flag bit is generated that distinguishes these two possible cases. Those subgroups that are now also contain black information, are subdivided again into blocks of 4 bits each, an which the same investigation is performed again and a block flag is generated which denotes the distinguishes between the two possible cases. Immediately after each block flag indicating that the him associated block also contains black information

contains, the block consisting of 4 bits closes unchanged in the original data sequence. The data sequence encoded in this way therefore contains for each data group an interleaving of identifier bits and bits to be transmitted unchanged.

A similar coding can be found in DE-AS 12 96 182, in which a digital information sequence in consecutive groups of 8 bits each is divided. A "will be consecutive groups then checked to see if they just white information or also contain at least black information. Follow several groups with only white information each other, they are combined in a data word, the first bit of which is an identifier bit represents that indicates that several groups are grouped together became. The following partial word consisting of 8 bits gives the number of only white information containing groups again. Any group that also contains black information is put together unchanged reproduced with a flag indicating that it is such an uncharged Data sequence is.

The present invention is based on the object of a method and a device for Specify compression of a digital information sequence in which the compressed data is clearly arranged are organized and therefore easy to process.

Based on the above method, this task is given by the characterizing part of the main claim solved.

Advantageous developments of this method as well an apparatus for performing the method are specified in the subclaims. Hereinafter the invention is explained in more detail with reference to the figures. It shows

Fig. 1 is a schematic view of a graphic document;

2 shows a schematic representation of binary information, generated by scanning the document of Figure 1> :;

3 shows a representation of binary information corresponding to FIG. 2 after recoding into the delta form;

Fig.4 shows a similar representation as Fig.3, the shows how extremely short pulses can be suppressed without excessive loss of resolution;

F i g. 5 is a tabular view of part of a compressed information sequence according to the invention;

Figure 6 is a block diagram of a compression system according to the invention; and

Fig./ a block diagram of an expansion system which is used to restore the compressed information expand.

In Fig. I a two-dimensional graphic document is shown, the graphic information in the form an irregularly dark area. Although the present method is specifically designed for use in is suitable for a facsimile system in which a two-dimensional graphic document is scanned it also includes other applications. In general it can be said that this procedure can be used wherever a binary image information sequence is present, which can be subdivided.

Fig. 1 illustrates a commonly used regular orthogonal scanning system in which each line 1 through 20 is divided into one hundred discrete bits. It is scanned in a known manner by liiifcs to the right and from top to bottom. A pulse train produced by scanning the entire document therefore contains 2000 discrete bits of information. Assuming that a positive pulse is generated for any area having a density above a certain value, and that no pulse is generated if the density of an area is below that value, then scanning of the document calls for FIG . 1 shows an electrical pulse chain according to FIG. 2 , in the case of successive lines for ease of illustration

ίο are arranged vertically. Each line becomes a divided into a predetermined number of blocks. In the present case there are ten blocks from 0 to 9 are numbered.

The basic concept of the present method is that there is greater efficiency for compression graphic information is obtained by only the graphic information of the blocks which contain pulses, which is shown in FIG. 2 the dark areas of the graphic document is equivalent to. In addition, this procedure can also be used with L ^ er ^ unnteri i -vorprirnicrungsnicttioucri κοΓΠυϊΠϊβΓΐ be, to achieve an even higher level of efficiency. FIG. 3 shows the pulse chain from FIG Conversion to the delta form. In this operation

confused! di <* first line reproduced without change. the the second line is then compared bit by bit with the first line. A logically negative or "delta white" signal, which is shown in Fig. 3 as no pulse. is generated when the corresponding Bi * .s of two lines are equal, while a logically positive or »delta black M signal, shown in Fig. 3 as a positive pulse is generated when the corresponding bits of two lines are different. The delta modulation therefore defines, instead of the area of the document itself, its outline. The process is used for subsequent Repeats lines in such a way that a particular line is compared with the previous line (not with the delta form of the previous: line) until all lines have been converted. The effectiveness The compression by this method results from the strong correlation between neighboring ones Lines of most graphic documents so that the ratio of the "delta black" information to the "delta white information is generally quite low.

V) In many applications the efficiency of the compression can be increased still further by using pulses with a length below a certain value, for example »delta black pulses. which consist of only one bit, as in FIG. 4 shown in phantom.

be suppressed. Although this method, hereinafter referred to as modified delta modulation results in a slight loss of resolution, it is acceptable in many practical cases. A »delta black «pulse, the leading or trailing edge of which is only one Bh from an adjacent block removed could also be suppressed.

FIG. 5 shows part of the pulse chain from FIG. 3. where only those blocks that contain "delta black" information are maintained and marked with line and

(. '· Block signals are combined. A logically positive Signal »1« indicates a line or a block that contains a "delta black" information, which consists of at least one bit, while a logical negative signal »0« one line or one block

■ 'indicates that there is no "delta black" information owns. If a certain line (such as line I in the example) does not contain any "delta black" information, only a negative line signal "0" is supplied. if

at least one block of a certain line at least contains one bit of "delta black" information, a positive line signal "13" is generated. The line signal a block signal follows, which indicates which of the blocks of this line is arranged in a consecutive row, where the blocks that do not contain any "delta black" information are omitted.

In the example of FIG. 3 and 5, line 1 does not contain any "delta black" information, so only one negative line signal »0« is generated. In line 2, however, are bits 58 to 60 of block 5 and bits 61 to 68 of block 6 "delta black". Therefore a positive line signal "I" is generated, which is a block signal follows. Bits 0 to 9 of the block signal correspond to blocks 0 to 9 of the corresponding line; bits 5 and

6 of the block signal for line 2 are therefore positive "I", which indicates that blocks 5 and 6 contain "delta blacktt information. Dem Blocksi crnal fnlfjpn Hip RIrSr ¹ IfP S nnrf ft in rtipcpr Ppihpnfrtlcrp

Similarly, in line 3, blocks contain 4 to 7 »delta black and white information, which is why bits 4 to

7 of the block signal are positive "I", while the rest are negative "0".

The present method is also applicable to a case where the pulse train without prior Conversion to the Delte form as generated by the scanner, compressed. Likewise is the method is also applicable to a case where the pulse train is continuous rather than in lines to be divided. In this case, the information is compressed in a certain arrangement, in which one Block signal the blocks that contain pulses follow. If the pulse chain is divided into lines, they have Compressed data has the general form "line signal + block signal + blocks," which contain pulses.

F i g. FIG. 5 shows an apparatus and a system for compressing graphic information according to FIG method described above in which only blocks containing positive pulses are maintained. It is assumed that the input information is encoded in the form of an electrical pulse train which is shown in a certain number of blocks of equal length and a certain number of lines is divided, where each row has the same number of blocks. The input information shall take the form of F i g. 2 own.

An optionally used delta converter A has a shift register 10 and a comparator 12. The converter A is not required if the information is already supplied in delta form or if it is to be compressed directly from the form of FIG. The input information is fed to the input of the shift register 10 and at the same time to an input of the comparator 12. The output of the shift register 10 is connected to another input of the comparator 12. The output of the comparator 12 is connected to an input of a logic register 14 of a first device B and also to the input of a buffer register 16 of a second device C. An output of the logic register 14 is connected to the input of a block register 18 which has a bit capacity which is equal to the number of blocks per line (10 in the case described) , each bit corresponding to a specific block position in the line. Outputs of block register 18 and the buffer register 16 are connected to inputs of a logic gate 20, whose output is connected to one input of a mixer 22. A third device D has a logic unit 24 which has an input 26 and whose output is connected einerr other input of mixer 22 is connected. The input 26 of the logic unit 24 can either have one or both outputs 28 and 30 de; Logic register 14 or the buffer register 16 be connected. A third input of the mixer 22 is connected to another output of the block register 18.

In operation, the first line is in the shift register 10 and the comparator 12 initiated, with as well

ίο the shift register 10 as well as the buffer register 16 di < Have the capacity to store the entire row. Di <second line is then introduced; the first wire without change in the buffer register 16 and there: logic register 14 transferred. When the second line when it arrives, it is compared bit by bit with the first line; a logically positive »1« or a »delti black «signal is passed into the buffer register 16 and the logic register 14 if the compared bits;

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»Delta white signal is stored in the buffer register 16 unc the logic register 14 given when the compared bits are equal. During the comparison process wire the contents of the shift register 10, which previously contained the first line, successively bit by bit through the second « Line replaced. When the operation is complete, the shift register 10 contains the second row and is ready for use the introduction of the third line. During the process " The fourth line was transferred into the delta form and into the buffer register 16 and the logic register 1 <

μ initiated. The buffer register 16 therefore contains the entire 100 bits of the delta information converted by converter A. This process is repeated for each line.

The logic register 14 is arranged in any known manner in order to examine the output of the converter A bit by bit and to decide which of the blocks contains "delta black & white information. A logically positive signal" I "will correspond to a block containing a" delta black «-Informatior

4n, stored in each bit of the block register 18, while a logically negative signal "0" corresponds to the blocks that do not contain any "delta black" -! Informatior are stored in the bits of the block register 18. In this way, the FIG. 5 shown block signal compiled. The logic gate 20 has access to the contents of the buffer register 16 and receives the block signal as a control input in front of the block register 18; the logic register 20 is equipped in any known manner to sequentially pass the blocks which are stored in the buffer register 16 and contain »delta blackw information, under the control of the block signal from the block register 18 . Both the block signal and the blocks containing “delta black” information are fed to mixer 22

The logic unit 24 is with the buffer register 16 or connected to logic register 14 or both and provided in any known manner to detect to be able to determine whether the processed line "delta black" -In-

wi formation contains; if this is the case, the

Logic unit 24 sends a logically positive signal "1" to Mixer 22 and a logic negative signal "0", if

this is not the case This signal is the line signal.

The mixer 22 combines the line signal that

(- ■ "■ Block signal and the blocks, the» delta black «-1 nfor mation contained in the second predetermined arrangement as follows: line signal + block signal (if the line signal is positive) + blocks that »delta

black «-lrifonnation included (if the / express signal is positive).

The output of the mixer 22 is to a transmission element /. out, which can be provided. to the compressed information essentially unchanged iik-r a transmission channel to a Fmpfangseinhen to transmit to her a Radio, -ägerwellc for radio transmission / u modulate or around with it a ray of light for transmission modulate using lasers or fiber optics. The transmission link /. is supposed to be the connection between a Create a transmission unit and a receiving unit, which is not the subject of the invention in detail.

Fig. 7 shows an expansion unit which serves to the delta information from the compression kit of I'ig. 6 diverge, and the original assemble graphic information. The F.inhci are the line signal, the block signal and the blocks, the cine »delta blackrt information contained in the Flip-flop 40. the block register 34 or the buffer register 32 is stored. When the Zcilcnsignal in the flip-flop

s 40 is logically negative "0", indicating that the If the processed line has no "delta black" information, the comparator 18 reads the content of the Shift register 42 unchanged. When the line signal is logically positive "I", indicating that

κι contains the line "delta black" information the following process stall:

While the previous line was being processed, the delta representation of this line was with lcls des Kompanitors 38 expanded into the original form and

r> output. Also, the expanded form was the previous line stored in the .Slider register 42, what from the following description becomes rural. The first logic gate 36 can be used in any

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Transmission link /. a system for transmission and for receiving graphic information encoded in the form of an electrical pulse train. Fine again Gabecinrichtung, which serves to the expanded output of the Finhcil of F i g. 7 in a visual form too transferred does not form part of the invention.

No first storage device has a buffer register 32, while a second storage device has a block register 34; the buffer register 32 and the block register 34 are associated with the buffer register 16 and the block register 18 of FIG. 6 similar. The buffer register 32nd da. Block register 34 and a flip-flop 40 have inputs that are connected to the output of the transfer element /. are connected; they store the blocks that contain delta black information, the block signal or the line signal. Fin logic gate 36 similar to logic gate 20 of FIG. 6 has inputs which are connected to the outputs of the buffer register 32 and of the block register 34, and an output which is connected to an input of a comparator 38. The comparator 38 has a further input which is connected to the output of the flip-flop 40, and supplies at its output the expanded or exploded graphic information which has been put together or converted into its original form. A delta graphics inverter has a shift register 42, the input of which is connected to the output of the comparator 38 and the output of which is connected to another input of the comparator 38. The input of an inverter 44 is connected to the output of the shift register 42, while its output is connected to yet another input of the comparator 38. The mode of operation of the receiving unit of FIG. 7 is essentially complementary to that of the transmission unit of FIG. As mentioned above.

in the block register 34 through the blocks one after the other. If a bit of a block signal that corresponds to a certain Block corresponds to is logically positive, the logic gate 36 leaves the corresponding block to the comparator 38 by. If the bit is logically negative, it generates

2Ί logic gate 36 a block without pulses. In this The compressed delta information is expanded to the standard Dclla form.

For the reasons explained above, the Dclta-Inverier to be used optionally; if he provided

jo, he works like this.

The previous time is in expanded and inverted form from the shift register 42 and the The output of the logic gate 36 is simultaneously fed to the comparator 38 and compared bit by bit. If that

si delta input bit of that processed by logic gate 36 Line is logically negative. indicating that the corresponding bits of the two rows are the same, selects the comparator 38 has its direct input from the shift register 42 and leaves the bit from

4Ii shift register 42 to the output of the comparator 38 pass without change. However, if the bit from logic gate 36 is logically positive, meaning that the bits of the two rows are different, comparator 38 selects its input from inverter 44 so that the bit from shift register 42 is logically inverted at the output of comparator 38 appears. Since each bit of a line is inverted from the delta to its original form, the inverted form is stored in the shift register 42 in order to replace the corresponding bit of the previous line; after a line has been processed and output, a copy of the final shape is stored in shift register 42 for comparison with the next line

In addition 5 sheets of drawings

Claims (4)

Patent claims: 1. Method for compressing a binary information sequence obtained by scanning by lines a graphic template was obtained and from groups of an equal number of Bits consists in which the individual groups are checked to see whether they are only bits of the first type (e.g. logical ZERO) or at least one bit of the second type (e.g. logical ONE) and in which a group identifier bit is generated which distinguishes the two possible cases, in which, furthermore, when the first case occurs (namely: group only contains bits of the first type) only the flag bit is generated representative of the entire group, and in the case of Occurrence of the second case (namely: group contains at least one bit of the second kind) a the group is further subdivided into blocks of bits of the same number, which are individually checked to see whether they are only bits of the first type or at least one bit of the of the second type, and in which a block identifier bit is generated for each block that contains the distinguishes between two possible cases, in which, furthermore, when the first case occurs (namely: Block only contains bits of the first type), only the block identifier bit is generated to represent the block and in the case of the occurrence of the second case (namely: the group contains at least one bit of the second type) the block is accepted unchanged in addition to the block identifier bit, d a by characterized in that the group of bits represents the information sequence of a scan line and the block identifier bits assigned to each line are formed as a continuous sequence of bits and that those blocks of this sequence of bits remain unchanged in the order in which they occur are connected in the original information sequence, the at least one bit of the second Art included. 2. The method according to claim 1, characterized in that the binary information is consecutive Lines are recoded using the delta modulation method before compression. «5 3. The method according to claim J or 2, characterized in that the blocks, the at least one Containing bits of the second kind are examined to determine how many are immediately consecutive Bits of the second kind are contained in each block and that these successive bits are suppressed if they are below a certain number. 4. Device for performing the method according to one of claims I to 3, characterized in that a line memory (16) is provided in which the binary information of a line can be stored, that a logic register (14) is also connected to the input of the line memory is, to which the information of a line can also be fed and which generates the identifier bits, that a block register (18) is connected to this logic register and stores the identifier bits, that to the line memory (16) and the block register (18) a logical Unit (20, 22) is connected, ""> which generates binary information for each line in the following order:
Line identifier bits, block identifier bits, block information. 5, device according to claim 4 for performing the method according to claim 2, characterized in that that one having a shift register (10) and a comparator (12) connected to it Delta converter (/ ψ is provided, and that the Delta converter connected on the output side to the line memory (lö) and the logic register (14) is.