DE2413569A1 - CONTROL DEVICE FOR AN ELECTRONIC COMPUTER - Google Patents

Description

Control device for an electronic computer The invention relates to a control device for an electronic computer, in particular a numerical controller for machine tools and an interrupt controller for an electronic computer having a lookahead memory device.

In conventional numerical control devices for machine tools and the like is a special control unit for each machine tool, e.g. Lathe, drill or milling machine, provided. For example, as shown in Fig. 1, are for controlling (and / or regulating) a machine tool 1 several devices is provided, i.e. a numerical control unit 2, an automatic tool changing circuit 3, an automatic workpiece changing circuit 4, a matching control circuit 5, a direct numerical control circuit 6 and a relay circuit 7. These devices are designed so that they have special functions for the operation of the machine tool exercise.

In this control device, therefore, it is extremely difficult to comply with the operating rules or functions of the machine tool 1 in addition to change. Around To overcome these difficulties, one has standardized parts and unified ones Devices developed, but these parts and devices are still unsatisfactory, since the degree of normalization and unification is limited.

In order to overcome these disadvantages, there is a numerical control device has been developed with a data processing device. As Fig. 2 shows, contains this data processing device 8 all for the operation of the machine tool 1 required functions, i.e. the functions of the numerical control unit 2, the automatic tool change circuit 3, the automatic workpiece change circuit 4, etc., as described with reference to FIG. 1.

With the help of the data processing device 8, additional Carry out changes to a program, so that the machine tool 1 as a function can be controlled by the changed program. It is also possible if none the aforementioned control functions are exercised, i. e.

as far as conventional numerical control functions are concerned, leisure in the program sequence to increase the number of axes to be controlled at the same time, to increase the control speed and to control several machine tools to take advantage of. These controls are based on the functions of a computer, the arithmetic operations according to a saved program.

Fig. 3 is a block diagram showing a data processing state in the data processing device according to FIG. 2, which has a main memory 9 for storing programs or data, a register 10 for storing data and an arithmetic unit 11 for arithmetic processing in the Main memory 9 and data stored in register 10. If only the one shown in FIG Data processing device for the various control operations of the machine tool is used are the program processing time and, accordingly, the control operations the machine tool 1 limited. Therefore, if the computing speed of the data processing device is increased, this improves the possibility of using the machine tool on different Ways to control.

The following functions are used in a numerical controller Required with the data processing device: 1) A program must run at high speed are processed.

2) Part of the program must be in a permanent memory (also read-only memory called) and another part of the program in a read-write memory (the is suitable for writing and reading).

In the event that the program is fixed or will not be changed, it is appropriate to store it in a permanent memory from the standpoint of stability. However, a read only memory has the disadvantage that it cannot be used as a data storage device for a Universal processing can be used. There are also additional changes of a numerical control program is unavoidable. For this reason must a read-write memory can be provided in the device. As read-write memory a core memory can be used.

3) Processing data must be indexed.

Often the case occurs that, for example, in a program for Control of three axes' tX "," Y "and" Z "the control programs for the axes are the same, but the data to be processed for the axes are different are. In this case, the function of indexing the processing data is advantageous.

An interrupt controller is in electronic computers known per se. One such conventional interrupt controller is however, disadvantageous in certain respects. In the conventional interrupt controller the memory is not fully used. If e.g.

an interrupt request is granted, the access must to the memory at each cycle to be interrupted for a while to a waiting time for establishing an interruption. Further, when an interrupt request occurs even if a previously read instruction is a conditional jump instruction, which is to be referred to a status register must contain the content of the status register deferred or shielded to be able to use the jump instruction (the branch condition) so decide that the interruption is enforced and that for this operation required time is relatively long.

The invention is based on the mentioned disadvantages and to eliminate troubles associated with a conventional numerical control device and a conventional interrupt controller in an electronic one Calculator occur. Furthermore, a numerical control device is to be created, in which a program is processed at high speed, a part of the program stored in a read-only memory and another part in a read-write memory and processing data can be indexed.

In addition, an electronic computer is to be created in which the efficiency of the memory increases, but the time to run a program and the programming work is reduced.

To solve this problem, a numerical control device with a data processing device, a main memory and a file register contains as a storage device, provided according to the invention that the main memory a program and the file register stores data.

Furthermore, in an interrupt controller for an electronic Computer with a memory for storing programs and data, with a control unit, an instruction register for storing a program instruction fetched from the memory having a decoder for interpreting that stored in the instruction register Program instruction, with an instruction address counter for controlling addresses in the memory and with a computing unit, which is dependent on commands from the control unit is controllable, it is ensured that an interrupt control unit is provided, in the case of a request to interrupt, the interruption deferred and the next command to be executed is executed if it this instruction is a conditional jump instruction, and if the as The next command to be executed is an unconditional command, the command register in the control unit is deleted and an uninterruptible address immediately after Completion of the execution of the command currently being executed from the Memory is read.

The invention will be described below with reference to the accompanying drawings explained in more detail.

Fig. 1 illustrates a conventional numerical control device for a Machine tool in the form of a block diagram.

Fig. 2 shows a conventional numerical control device having a Data processing preparation is shown schematically in the form of a block diagram.

3 shows the data processing states in the data processing device according to Fig. 2 in the form of a block diagram.

Fig. 4 shows the structure of a data processing device in a numerical control device according to the invention in the form of a block diagram schematically.

Fig. 5 shows an embodiment of the data processing device in the form of a block diagram.

Figure 6 illustrates an embodiment of an interrupt controller according to the invention in the form of a block diagram.

Fig. 7 shows the relative timing of various signals for represents the case that the command read is an unconditional jump command acts.

Fig. 8 shows the relative timing of various signals for represents the case that the command read is a conditional jump command acts.

Detailed Description of the Invention Figure 4 illustrates an embodiment a control device in an electronic computer, which is a numerical control device for machine tools according to an aspect of the invention acts. This numerical control device contains the main memory 9, the register 10 and the Arithmetic unit 11, which have already been mentioned, and further a file register part 12 as a data storage device embodying the invention is newly provided.

In a conventional data processing device (or a Universal computer) without a file register part 12, both data and programs processed in the main memory 9, i.e. it is a frequent access to the main memory necessary. As a result, the processing speed is the conventional one Data processing device relatively small.

In the device according to the invention, the data mentioned all processed in the file register part 12. If a high-speed storage, e.g., solid-state memory used as the file register part 12 can be process the data at high speed.

Also, memory areas for programs and data are from each other separated so that it is possible to store programs in a read-only memory. Further this facility has the advantage that programming by indexing a File address can be simplified.

An embodiment of the numerical control device is shown in will be described in more detail below, reference being made first to FIG. Of the File register part 12 contains a file register 101, a file address register 102, a file index register 103 and a file address calculation circuit 104.

The file register 101 is used to store data in a Program should be used. The file register is a solid-state storage part, like a read-write memory in the form of an integrated circuit, most suitable which has a high access speed and expands its storage capacity can be.

Since the data is stored in the file register 101, they need not to be read from the main memory 110.

This main memory 110 stores only programs to which the file register always has access. As a result, the processing can be speeded up while the main memory 110 can be a read-only memory.

The file address register 102 is used to address data that are to be read from the file register 101. The file index register 103 is used to change the file address if necessary. The file address storage circuit 104 effects an address change by adding the contents of the file index register 103 to a file address contained in the operand part of an instruction a file address entry without changing the file address and performs address calculations of the file register 101 in response to the command.

The numerical control device according to FIG. 5 also contains a computing unit 105, a register 106 and the main memory 110.

The arithmetic unit 105 is designed in such a way that it receives data from the file register 101 and the register 106 as a function of those stored in the main memory 110 Programs added or subtracted. The register 106 is used to store Calculation results of the arithmetic unit 105.

The numerical control device also includes a storage index register 107, which is used to change the addresses of the main memory 110, and an address arithmetic circuit 108, which is an input to the (input signals for the) command address counter 9 (also Called program counter) causes (resp.

generated), which will be discussed in more detail below.

This address arithmetic circuit 108 has the four indicated below Functions: 1) Selecting address data when a memory reference command is supplied from the address part of a command and the transmission of the selected address data into the instruction address counter 109.

2) When a memory reference command requires an index change that Addition of the contents of the memory index register 107 to address data from the address part of the command and the transfer of the addition results to the command address counter 109.

3) The transfer of a fixed interruption address to the instruction address counter 109 when an interruption occurs.

4) With an "exit subroutine" command, the transfer of Output signals from a stack 113, which will be described in more detail below, in the command address counter.

The command address counter 109 is used to temporarily store the memory address an instruction to be read out from the main memory. In this regard, with the exception upon execution of the memory reference instruction, the instruction address counter 109 operates successively increasing the number of addresses stored in the main memory. This means, the instruction address counter 109 reads out an instruction from the main memory 9, and then the address of the command read out is given by the command address counter 109 increased. In this way, the instruction address counter becomes 109 for the next instruction prepared.

The main memory 110 can be either read-only memory or read-write memory be. The main memory 110 is provided with a Command register 111, which is used to store the command read out from the main memory 9, and provided with an instruction decoder sequence control part 112 which is used for decoding the outputs of the command register 111 and for controlling other registers serves.

Reference numeral 113 in Fig. 5 denotes a stack memory, the for intermediate storage of the content, or a memory address, of the command address counter 109 serves. The stack 113 is provided with a stack address register 114 is provided, which is used to control the storage tank 113.

The stack 113 is defined by the stack address register 114 address-controlled, with the data read in first being read out again as the last be when a jump from a main program into a subroutine and the return are requested from the subprogram into the main program, the memory address must be (Return address) to be stored somewhere for return when the jump is performed. If in this case the read-write memory is used as the main memory 110 is used, the return address can be stored in main memory 110. However, when the read only memory is used as the main memory 9, it is special Storage device required to store the return address. According to the invention the stack 113 is used to store the return address. Consequently the function of storing the return address can be omitted in the main memory, so that he can execute a program repeatedly, which speeds up execution a command for a jump to the subroutine is used.

In other words, when returning from the subroutine to the The main memory 110 does not need a cycle for reading out the main program Return address (also called return address), as it is stored in the stack 113 and not in main memory 110 is stored. As a result, can a command to return from the subroutine (or to exit the subroutine) run at high speed.

The operation of the numerical control device is as follows described on the basis of a case according to which, for example, a program "added the in the file register 101 at the address F1 and the data A stored under the Address F2 stored data B and store the addition result at the address F3 ab "is to be executed. It is also assumed that the commands" read the data stored under address F2 of file register 101 in register 106 ", added those in register 106 and those at address F2 of file register 101 stored data "and" store the addition results at address F3 of the file register 101 "at the addresses N1, N2 and N3 of the main memory, respectively 110 are stored.

First, the command address counter 109 is set to the address N1, at which the program begins. The one stored under address N1 of main memory 9 Command is read out first, whereby its actual command part (also operation part called) is set in the instruction register 111 and by the instruction decoder sequence control part 112 is decoded. Here, the command vlies is used at address F1 of the data register 101 data stored in register 106 "is decoded. Depending on this, the file address part of the command word the file register 101 via the file address calculation circuit 104 and the file address register 102 so that the stored under the address F1 Data A are transferred to register 106 via arithmetic unit 105.

Next, the instruction address counter 109 is raised from address N1 the address N2 switched so that the contained therein Command word is decoded in the same way as described. Thus, the previously read out data A of the register 106 to the address F2 of the file register 101 stored data B is added. The result data are transferred back to register 106, that is, the data A + B remain stored therein.

Then the command address counter 109 is set to the address N3, so that the data A + B contained in register 106 under address F3 of the file register 101 by decoding the command word in a manner similar to that described will. This completes the execution of the program mentioned.

The advantages of the numerical control device according to the invention are the following: 1) Since up to now the main memory has processed both programs and data it was not possible to use solid-state memory (read-write memory) to replace as it loses the contents of a program when the power supply is switched off or fails. According to the invention, a program part and a Data part separated from each other and the file register, which only processes data, newly provided.

Therefore, the data to be processed by the file register is hardly transmitted affects a power failure, that is, that of a power failure lost data can be easily restored. Therefore, the Main memory as high-speed solid-state memory (read-write memory) and high speed data processing can be achieved.

Furthermore, the use of the file register means that there is no storage element for data processed in main memory have been, i.e. the only main memory processing programs can, as usual, be made of inexpensive memory Build components. The price increase due to the use of the file register is therefore relatively small compared to the advantages that the increase in Operating speed provides.

2) The use of the file register in addition to main memory leads to convertibility between read-only memory and read-write memory processing a program.

3) The indexing method can be used for data consists in changing the index of the data in the file register. This leads to a Simplification of programs.

Fig. 6 shows a further embodiment of the control device for an electronic calculator that is an interrupt controller acts according to a further aspect of the invention. The interrupt controller contains an instruction address counter 601 (also called a program counter) for storage the memory address of a command to be executed whose output signals MADo to MADe form the input address signals of a memory 602, an instruction register 604, a decoder 605 for storing an instruction that is currently being executed for decoding the output signals IRo to IRm of the command register 604 into commands, such as a conditional jump instruction and a NOP instruction, an arithmetic unit 606 and a memory address arithmetic unit 603.

The interrupt control device further comprises an interrupt control unit 612 on. This interrupt control unit 612 includes a circuit 610 that controls the Determination of the order of priority during the interruption and one of the Output lines Mo to Mn that meet the interrupt requirements L. , L1 to Ln correspond to a circuit 0 611, which upon receipt of the output signal the circuit 610 output signals INT - ADo - INT - AD or interrupt fixed addresses outputs, and an interrupt request storage circuit 609 for storing a Interrupt request INT - REQ up to its grant, whereby the circuit 609 by an interrupt request grant signal INT - ACK (also interrupt request acknowledge signal called) is reset.

The interrupt request signal INT-REQ forms an input signal a flip-flop circuit 608 while the interrupt request acknowledge signal INT-ACK into the flip-flop circuit 608 with the aid of a clock pulse signal INT-CLR is enrolled.

The interrupt control unit 612 also includes an inverter 609 (also called the NOT element or inverter) through which the interrupt request signal INT - REQ is inverted and fed as an inverted signal to flip-flop 608, and a circuit 607 for determining a conditional jump instruction. This circuit 607 determines whether the output of the memory is a conditional jump instruction acts.

When a command has been read out from the memory 2 and a Interrupt request on one of the interrupt request lines L0 - Ln appears, the output of the memory 2 is checked by the circuit 607, to determine whether or not it is a conditional jump instruction.

If it is not a conditional jump instruction, a Output "O" of the circuit 607 inverted by an inverter 618 and a AND gate 613 supplied. As a result, the output of the flip-flop circuit becomes 608 from AND gate 613 turned on, whereby an interrupt execution signal INT is formed by an AND gate 616 with the aid of a clock signal CLKO is turned on, so that an instruction register reset signal INR - CLR the one Input CLR of the command register 604 is fed, which is reset to the NOP command after the command currently being executed has been executed.

During the execution of the NOP instruction, the interruption fixed address output signal becomes of the circuit 611 via a memory address arithmetic unit 603 into the instruction address counter 601 is transferred to the contents of the memory under the fixed interruption address read out.

When the detection circuit 607 does not accept the read command as identifies a conditional jump instruction, the interrupt control in carried out in the manner described above. However, if it is used as a conditional jump instruction is identified, the interrupt signal is withheld so that the conditional Jump instruction is executed before the interruption, even if the interruption request occurs when reading out the conditional jump command. That is, even if the interrupt request signal is generated by the flip-flop circuit 608, so is the detection circuit 607 generated output signal inverted by the inverter 618 and fed to the AND gate 613, so that the interrupt request signal is disabled.

As a result, the negative output of the AND gate 613 becomes inverted by an inverter 617 and with the aid of a clock signal CLKO through a AND gate 615 switched through, so that the command reset signal is one input CLK of the command register 704 and consequently the output or the output signal of the memory, i.e. the conditional Jump command, in the command register 604 is transmitted upon completion of the current command.

This construction of the interrupt control unit has the advantage that if an instruction read is a conditional jump instruction, it before an interruption is executed so that it is in an interrupt processing subroutine it is not necessary to reset the contents of a status register, d. H. to store and protect. A subroutine for transferring the command into State register to protect it is therefore not necessary, so that the processing time gets shorter. A programmer can therefore easily write interrupt processing programs put up.

Furthermore, if an interrupt request occurs in the case that the previously read command is not a conditional jump command is, continuous access to the memory is possible without the advantage of the look-ahead storage system is impaired.

The mode of operation of the interrupt control device is shown in FIGS. 7 and 8 clearly shown.

Claims (3)

Claims Numerical control device with a data processing device, which includes a main memory and a file register as a storage device, d a d u r c h g e -k e n n z e i c h n e t that the main memory is a program and the file register stores data. 2. Numerical control device according to claim 1, d a d u r c h g e it is not noted that the main memory is a permanent memory and the file register is a read-write memory. 3. Interrupt control device for an electronic computer with a memory for storing programs and data, with a control unit, an instruction register for storing a program instruction fetched from the memory having a decoder for interpreting that stored in the instruction register Program instruction, with an instruction address counter for controlling addresses in the memory and with a computing unit, which is dependent on commands from the control unit What can be controlled is that an interrupt control unit is provided in the event of a request to interrupt the interruption is postponed and the next command to be executed is executed if this instruction is a conditional jump instruction, and if the next instruction to be executed is an unconditional instruction, the instruction register deleted in the control unit and an uninterruptible address immediately after Completion of the execution of the command currently being executed from the Memory is read.