DE2407599B2 - DEVICE FOR CALLING ADDITIONAL PROGRAMS SECURED BY FUNCTION LOCKS - Google Patents

Description

Transfer of the required part of the program to the computer is marked by combining the following features:

a) the function locks or switches (51 'to 516') are in at least two separate, Groups that can be selected individually from the computer (4 ') with the same lock or key Number of switches divided;

b) each function lock or switch (SV to 516 ') of the first switch group is assigned a specific address signal which is the same as the address signal in one of the switches of every other switch group;

c) the outputs (Fig. 2: d- \ to a'-16) switches assigned to the same address signals (SV to 516 ') are each led to a common AND-not element (U 1 to US) ,

1. Computer-controlled device for Ciek'uunische data processing systems for determination
and validation of the selection made
of key-operated function locks, each in the actuated state via a
associated switch a specific address signal for the computer to display the retrievable _ _

speed of the respective function lock associated with retrieval of certain program parts, z. B. Subpronets Output additional program that starts with a gram, after a previous address check controls from the computer when a program word occurs and an address word is output as a validity branch from a comparison address image signal to the arithmetic unit, the retrieved comparison address signal in an From the publication "IBM Technical Disclosure

Address comparator checked for correctness 15 Bulletin, Vol. 11, No. 11, April 1969, p. 1502 and is, with a signal to 1503, as well as from the German Auslegeschrifi

10 78 790 it is also known to compare address signals coming from different memory registers with one another.

In the case of electronic data processing systems for commercial purposes, especially those that work with program-controlled computers, it is customary to provide certain additional programs: ie or program parts to carry out daily closings, incoming goods and the like using electrical function locks, These function locks are in the "On" position independently of one another via the associated key to bring and deliver certain address signals to the computer in this position, the üei assigned »flags« the desired ones in a special additional program memory assigned to the computer Make existing programs or program parts available for retrieval. To a predetermined positioner

each of which on the output side with 35 of the normal computer program then takes place at a first input (e, '- l to e,' - 8) which routinely exits to this specific via second inputs (e., '- l to e »' -3) with programs with previous query of the switching address images (6 ') in adjustments of the function locks. Since each associated address comparator (1 ') function locks is associated with a very specific additional program, and that a control signal in 40 grams is assigned which, when requested, is only valid depending on the comparison result and not in combination with the

other programs or program parts that can be additionally selected must take precautions which prevents or differs the activation of several locks at the same time simultaneous provision of several additional program parts is prevented.

Appropriate locking devices are already provided on keyboards (Double key lock) known

Switchgroups, with the fixed-value memory becoming 50 (cf. DT-OS 15 24 260 and DT-OS rather in accordance with 22 49 379 specified by the computer (4 '), but with regard to the scarf instructions Stored comparison address range that increases with the number of buttons sen outputs, which in each case grows with each other, are not acceptable if one of them is to be questioned Switches (51 'to 516'), also these function locks within the The first part of the address to be drawn (reference keyboard 55 must be accommodated and wired. Di < drcssc) and its switchgroups, often in modular design and in tion characterizing the second address part of integrated circuit technology built-up keyboard contain; allow the subsequent installation of the radio

e) one of the comparison address images (6 ') to lock, but the locking can be downstream, on the second address parts 60 direction for the buttons not additionally the radio appealing switching device (! 7) to be assigned to tion locks, as this for gan; Switchgroup selection. certain cases are set together with the buttons

Need to become.

2. Device according to claim 1, characterized in that the known devices have in common

indicates that an address comparator at 65 has the disadvantage that when additional known n-bit data selector multiplexer, preferably manually, can be marked and also

is used. addressable subroutines or additional programs

gram parts next to the. already existing pro

rende control line (7 ') to display the comparison result between the address comparator (1 ') and the computer (4') is provided;

d) A freely programmable read-only memory also serves as comparison address images (6 ') a number of storage locations which is at least equal to the number of all available switches

switches. All other switch outputs remain log »0«. As a result, each of the switches Sl to Sn is assigned a certain code combination (address signal), which z. B. for the switch Sl LOLL ...

and for switch S 4 is LLLOI.

4 with the cooperating with the device programmable computer is referred to, the either repeated or via a standard query program, depending on the program parts entered

gxammen the device checking the address validity (address comparator) for checking the validity of the further additional address signals would have to be extended accordingly. However, this has to be carried out with a correspondingly high level of circuit engineering effort. Commercially available facilities cannot be used for the extended address comparison or can only be used to a limited extent, and only if the selection of all addresses to be checked corresponds to

Possibility of not using the comparator used - ίο eTnma ^ nYchef ^^ or

increases. ^D - ·

The invention is based on the object of a computer-controlled device for determining and Validation of the selection of function locks made i to create program control, the calibration taking advantage of the advantages of integrated Commercially available circuits also have a particularly low cost in terms of circuitry with a larger number of function locks and addresses to be processed and easily integrated into existing standard key fields with the same technology without modification the device performing the address comparison can be integrated.

calls up several predetermined switches Sl to Sn for carrying out the specific additional programs or program parts. For this purpose, the computer 4 is connected via a specially provided control output 5 to a comparison address generator 6, which z. B. a freely programmable read-only memory integrated in the computer 4 with a number of memory locations corresponding to the maximum possible number of switches 51 to Sn of the keypad T can be assigned to a specific one of the switches 51 to Sn. Each storage location contains the information to its associated switches 51, ..., and Sn belonging code combination as the comparison address for retrieval via first outputs O ₁ -I by a _x -n associated

This problem is solved by the 35 second inputs «?, -! to Vn of the address comparison

claim 1 specified solution. An advantageous embodiment is mentioned in the dependent claim.

The advantage achieved by the invention is particularly to be seen in the fact that one for all function locks chers 1 are placed, which leads via a control signal depending on the respective comparison result Control line 7 is connected directly to computer 4. If one of the ver

A common query program can be used 30 identical address images. possible
Number of function locks are used, each

or 5 η generated address signal is taken over at the same time at second outputs a.ri to a ₂ -n of the comparison address generator 6 pending comparison selected function lock in the form of a single 35 address signal from the computer4 for further processing by the address comparator signal, that is, the signal given to this Address signal

because the computer directly receives the switching status of the

An exemplary embodiment of the invention is described in more detail below with reference to the drawings. It shows

F i g. 1 shows a device according to the invention in a block diagram,

F i g. 2 a further embodiment of the device in the block diagram,

F i g. 3 a code table,

Fig. 4 shows the circuit structure of a Address comparator, as shown in FIG. 2 is used.

The device according to the invention shown in FIG. 1 contains a most essential unit assigned additional program part executed.

In Fig. 2 shows a special embodiment of the device according to the invention, whereby already Devices described in FIG. 1 and shown here again have the same reference numerals, but with Index are provided. According to this embodiment, sixteen switches S1 'to 516' are provided, which are shown in two optionally controllable switch groups combined are, with all even-numbered switches 52, ... 516 'of the one and all odd-numbered Switches 51 ', ... SlS' are assigned to the other group. For this purpose, the inputs of the even-numbered Switch Sl ',. .. 515 'to a common

Address comparator 1 with first inputs e, -l to 50 connection 8 and the inputs of the odd-numbered

e _t -n, which are applied to assigned outputs a- \ to an of switches Sl to Sn , the electrical function locks assigned to the touch panel T of a computer-controlled data input device for the provision of additional programs or program parts individually in a known manner, ie to be closed. At the outputs a-1, ... or on each switch Sl, ... or Sn, there is a resistor Λ 1, ... or R η switch S 2 ', ... 516' on a common Connection 9 out. For the selection of the two switch groups, an electronic switching device U is provided, which is controlled by the comparison address generator Γ on instruction from the computer 4 'via a line 10. The switching device L has two npn transistors Tl and Tl, which together emitter (scnluß to 3 ') to the reference voltage 0 V are set. The collector of Π is mi

switched. The resistors / ?! to Rn are common to the already mentioned connection 8 and the collector

sam is connected to a positive reference voltage + U (log "L") of a direct voltage source (not shown) via a connection 2. Another connection 3, which carries a reference voltage of 0 V (log “0”) of the voltage source mentioned, also connects all inputs of the switches S1 to Sn with one another. If one of the switches Sl to Sn is closed, its output is fl-1,. . . or linked to from log "L" to logic "0" gevon Tl to terminal. 9 Both at connections 8 and 9 are also placed via a resistance R _c to positive operating voltage + U (at connection T) of the DC voltage source, not shown. Furthermore, a resistor R _B or R _B 1 is placed in the base line of each transistor TI and Tl. The resistor R _B 1 is connected to the output of an inverter / whose input ge

r.

common to the other end of the resistor R _B l is connected to the said line 10.

Of the switches S1 'to S16' already mentioned, there are two switches S1 ', S2' or S3 ', S4, ... with their outputs a'-l, a'-l or a'-3, a'- 4, ... to a common and-not element (NAND) Ul, Ul, ... or t / 8, the output of which is connected to an assigned first input Cj'-1, e ^ -2, ... or Cj'-8 of the address comparator 1 '. The switches Sl ', Sl' acting together on an and-not element t / l, Ul, ... or t / 8; S3 ', S4'; or SlS ', S16' generate the same address signals. Since there are only eight AND-not elements U 1 to i / 8, only eight different address signals (y code) are output, which are also assigned eight different comparison address signals in the BCD code.

The comparison address generator 6 'used in accordance with this exemplary embodiment (FIG. 2) generates comparison addresses in binary-coded form when activated via the control output 5 of the computer 4', which each have a first, the second input e, which characterizes the switch S1 'to S16' to be queried _{Contain s} ' -1 to e ₂ '-3 of the address equalizer 1' supplied address part and a second address part characterizing the respective switch group. _{According to this code, the first outputs O 1} '-1 to a _t ' -4 leading the comparison addresses to the address comparator 1 'are evaluated accordingly.

The output α, '- Ι is the value 1 (2 °), the output a _t ' -l is the value 2 (2 ¹ ), the output α, '- 3 is the value 4 (2 ² ) and the output Oj '-4 assigned the value 8 (2 ³ ). Since each of the two switch groups, which can be optionally controlled via the connection 8 or 9, each comprises eight of the sixteen provided switches Sl 'to S16', three of the total of four first outputs β, '- Ι to a _x ' -A are sufficient to transmit the total eight different binary-coded comparison addresses (first address part) to the address comparator Γ. The free fourth output fl / -4 of the comparison address generator 6 'is used for the control (second address part) of the switching device U and is connected to the line 10 for this purpose. Should the first switch group be queried with switches S1 ', S3', S5 '... and the associated address given by one of these switches S1', S3 '... in the closed state to the first inputs of the address comparator 1' is checked for validity remains, as the F i g. 3 shows that the output e, '- 4 log "0". The state log "0" of the connected line 10 makes the output of the inverter / log "L" (positive signal). The npn transistor T1 turns on and applies log "0" (reference voltage 0 V) to the terminal 9. For the second switch group with the switches S 2 ', S 4', S 6 '... the procedure is reversed.

In Fig. 4 shows the circuit structure of the address comparator 1 'used according to FIG. 2, which is known as a commercially available component (IC) under the designation 8-bit data selector multiplexer. 1/9 to U16 denotes a number of AND elements corresponding to the number of first inputs e, '- 1 to e,' - 8, the outputs of which are jointly led to an OR-non-element O , at whose output the already mentioned Control line T (Fig. 2) is connected, which in the event of a positive address comparison, e.g. B. e, '- 6, e ₂ ' -1 and e _s ' -3 == log "L" and all other inputs = log "0" a validity signal

ίο to the computer 4 'to take over the valid address (outputs a _z ' -l to a ₂ '-4). A specific first input e, '... is assigned directly to each of the AND elements i / 9 ... already mentioned. Furthermore, viewed in the counting direction of the AND elements t / 9 to 1/16, the 1st, 3rd, 5th and 7th UnJ element t / 9, t / 11, t / 13 and U 15 is above the input side a common inverter / 1 with the input e ₂ '-l, the 1st, 2nd, 5th and 6th AND element 1/9, U 10, 1/13 and 1/14 via a common inverter II with the Input e ₂ '-2 and Jas 1st, 2 .. 3rd and 4th AND element t / 9 to U 12 with the input e ₂ ' -3 also connected via a common third inverter / 3. Each of these inverters / I to / 3 is a further inverter / 4, / 5 or / 6 for the code-correct control of the AND elements t / 9 to t / 16

as downstream, of which the inverter / 4 each to a further input of the AND element t / 10, Uli, t / 14 and t / 16, the inverter / S each to U 11, U 12, UlS and t / 16 and / 6 is switched on at t / 13, t / 14, UlS and U 16, respectively. Furthermore, all AND elements / 9 to t / 16 are connected on the input side to a common conductor 11 for preparation, which during operation carries positive operating voltage (log "L") via an inverter stage / 7.

Due to this circuit structure of the address comparator 1 'described above ensures that a validity signal is always sent to the computer 4 'to accept an address signal is output when the supplied comparison address signal (binary number) matches that in the 1-out-of-8 code supplied by one of the switches Sl 'to S16' Awdress signal matches. Is the address signal coming from switches Sl 'to S16' not to be identified, d. i.e. if it is outside the permitted combination options of the 1-out-of-8 code lies, as can happen, for example, when two switches are pressed at the same time, so this validity signal is not given. Any given validity signal tells the calculator that the respectively controlled switch Sl ', ... closed

("On") is. The circuit of the other switches S1, ... remains unaffected.

The invention is not restricted solely to the exemplary embodiments shown. Instead of here Keypads shown Γ, 7 "with only 8 or 16 across the same number of function locks controlled switches Sl to S8 or Sl 'to S16' If units 1 and 4 are appropriately designed, they can also have a larger number of switches step, the switches individually (Fig. 1) or in groups

pen-wise (Fig. 2) are led to address comparators.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: The invention relates to a computer-controlled device according to the preamble of claim 1 Through the DT-AS! 5 74 994 is a device for program-controlled electronic data processing systems for identification and validation an address selection made known, in which a sequence control device in connection with a follow-up address register in the case of jump commands, the transition to special command addresses for the purpose of