DE2361823A1 - Read and stabilizing amplifier operation - uses two fed-back inverters consisting of switching and load transistors - Google Patents

Abstract

The read and stabilizing amplifier is designed according to a clocked flip-flop. The read signals from the transistor storage elements are passed to the control input of the switching transistors. The transistors inserted in the feedback path open the feedback paths before a read signal has been received and the operating point is set in the flip-flop paths. After a read signal has been received, the transistors in the feedback paths are again conductively controlled. The load transistors and the switching transistors are conductively controlled during the period when a read signal is applied to one of the inverters.

Description

2367823

SIEMENS AKTIENGESELLSCHAFT Munich, December 12th. 1973

Berlin and Munich Witteisbacherplatz 2

73/2167. ·

Method for operating a read and regeneration amplifier constructed in the manner of a clocked flip-flop.

The invention relates to a method for operating a type of clocked flip-flop Read and regeneration amplifier, which consists of two feedback inverters, each with a switching transistor and a Load transistor consists in which before the arrival of a read signal from a transistor storage element at the control input one of the switching transistors are separated by transistors inserted in each of the feedback branches, the feedback branches and the operating point in the flip-flop branches is set and in which, after the arrival of the read signal, those arranged in the feedback branches Transistors are again made conductive so that the flip-flop toggles into the position determined by the read signal.

Regeneration circuits for the stored signals or read signals from integrated one-transistor memory elements are known. Such a regeneration circuit results e.g. from ISSCC Digest of Technical Papers, pages 30 to 31, February 1973. The function of this regeneration amplifier is in the patent application P 22 .62 ΛΤ1..2 .... described. being The structure is also shown in FIG. The regeneration amplifier is designed in the manner of a clocked flip-flop. It consists of two feedback inverters, each with a switching transistor and a load transistor. The switching transistor one inverter is denoted by T1, the load transistor of one inverter is denoted by T3. The switching transistor the other inverter is named T2, the load transistor T4. From connection point 2 or 1 between Switching transistors T1 and T2 and load transistors T3 and Τ4

VPA 9/210/4015 Il / Pe -2-

509826/0375

each leads a feedback branch to the control input of the Switching transistor of the other inverter. A transistor T7 or T8 is inserted into the feedback branch. By these transistors T7 and T8, the feedback branches can be separated. For setting the operating point of a each flip-flop branch are transistors T5 and T6 between connected to the control input of the switching transistor T1 or T2 and the connection point 2 or 1 of the inverter. The load transistors are connected to a fixed voltage VDD, they are connected to their control inputs by a cycle <|> 1 controlled. By a clock φ 2, the transistors T5 and T6, through a Clock cj> 3 the transistors T7 and T8 operated. Bit lines DL1 and DL2, which lead to storage elements SE, are each connected to the control inputs of the switching transistors T1 and T2. Some memory elements SE are single-transistor memory elements shown.

The well-known function of this circuit is illustrated with the help of the Pulse diagram of Figure 2 described. Tensions are plotted against time t in it. Before a read signal e.g. appears on the bit line DL2, the feedback branches are separated by blocking the transistors T7 and T8 (the clock φ 3 is removed). On the other hand, the transistors T5 or To by applying the clock φ 2 in the conductive State brought. Since at the same time the load transistors T3 and T4 are controlled to be conductive by the clock φ 1, change the voltages LV1 and LV2 at points 1 and 2 in the manner shown in FIG. That is, the voltages LV1 and LV2 approach and reach the control inputs of the switching transistors T1 and T2 via the transistors T5 and Τ6. These are conductively controlled, so that at points 1 and 2 and at the control inputs of the switching transistors T1 and T2 set potentials determined by the ratio of the load transistors T3 and T4 and the transistors T5 and T6 is determined. Before a read signal is fed to the regeneration amplifier, i.e. before a memory

_ VPA 9/210/4015 -3-

50 9 8 26/0 3.7-5

element is controlled, the cycle Φ1 disappears at the load transistors T3 and T4, so that they are blocked will. Points 1 and 2 discharge to the threshold voltage, since transistors T 5 and T6 are conductive. The transistors T5 and T6 are then blocked. The voltage at the drops due to the shutdown faults Control inputs of the switching transistors T1, Τ2 below threshold voltage, i.e. block the switching transistors T1, Τ2.

It is assumed that a read signal is applied to the control input of the switching transistor T2 via the bit line DL2 will. Let it be a binary "1", meaning high potential. First of all, this read signal can be used by the regeneration amplifier do not affect it yet, as all transistors are blocked. The read signal also adds to the potential already present at the control input of the switching transistor T2. A clock φ is now fed to the load transistors T3 and T4 again and then the transistors T7 and T8 are grounded controlled conductive in the feedback branches and thus closed the feedback branches again. Only now can that The read signal at the switching transistor T2. Affect the flip-flop in such a way that the. Switching transistor T2 becomes conductive earlier than the switching transistor T1, which remains blocked as a result of the feedback. Accordingly, the Voltage LV1 decreases and voltage LV2 increases until the flip-flop goes into its stable state. The read signal is thereby amplified and then written back to this memory element to regenerate the read memory element SE.

In this known mode of operation of the one shown in FIG Regeneration amplifier is the read signal in the state in which it comes from the bit line, for switching the flip-flop used. The read signal must therefore have such a voltage value that it can activate the flip-flop even in the event of asymmetries can tilt into the correct position due to manufacturing tolerances. ·.

VPA 9/210/4015 - -4-

5098 2 6 / 037B

The object on which the invention is based is to provide a regeneration amplifier constructed in accordance with FIG to operate in such a way that the regeneration amplifier can still process read signals smaller than the stroke this is possible according to the known mode of operation. This object is achieved in that the load transistors and the switching transistors are turned on during the whole time during which the read signal is sent to one of the Inverter is applied, so that this inverter works as a preamplifier and preamplifies the read signal and that then the preamplified read signal is used to switch through the flip-flop in the position determined by the read signal.

In the invention, the read signal arriving via the bit line is not used to flip the flip-flop, Instead, the read signal supplied is first pre-amplified and then the pre-amplified read signal to flip the flip-flop used. This means that the inverter to which the read signal is fed is used as an amplifier.

The inventive mode of operation of the regeneration amplifier of FIG. 1 is explained with the aid of a pulse diagram of FIG. Again, tensions are plotted against time.

First the flip-flop is prepared for reading. In Fig. 3 this is the area A. During this preparation time the transistors T7 and T8 in the feedback branches are blocked by removing the pulse Cp 3 by applying it of a pulse φ 1 the load transistors T3 and T4 conductive controlled and by applying a pulse φ 2 the transistors T5 and T6 brought into the conductive state. It then arises at points 1 and 2 of the flip-flop and at the control inputs of the switching transistors T1 and T2

en

Voltage / on, by which the operating point of the inverter is determined will. The voltages LV at points 1 and 2 are

VPA 9/210/4015 -5-

5098 2 6/037 5

drawn in the last line of Fig.3. They have roughly the same value. After setting the operating points, the transistors T5 and T6 are again transferred to the locked state *

This is followed by the time in which a read signal comes out one of the memory elements SE is supplied to the control input of one of the switching transistors T1 or T2 of the inverters becomes (area B). It is assumed that the quad line WL1 is controlled and thus the memory element SE1 is selected. It is further assumed that a binary "1" is stored in the memory element SE1. Then arrives at the control input of the switching transistor T2 (see penultimate line of Figure 3) a voltage that the potential at the control input of transistor T2 is increased. Since at the same time the clock φ 1 at the load transistors T3 and T4 are present, they are in the conductive state and the inverter, consisting of the transistors T2 and T4, acts as a preamplifier. I.e. the read signal that is transmitted via the bit line DL2 has come, appears inverted and amplified at point 1. This is in the last line of FIG shown in curve 1. It is clearly too see how the potential decreases at point 1 «,

Only after the read signal has been preamplified will a clock pulse φ 3 is fed to the transistors T7 and T8 in the feedback branches; State transferred so that the circuit works as a flip-flop. The pre-amplified read signal at point 1 is effective via the feedback branch to the control input of the transistor T1 of the other inverter. This will be instant switched through, the potential at point 2 decreases very quickly. The potential at point 2 is in turn across the transistor T8 fed back to the control input of the switching transistor T2. The relationships just described are shown in area C of Fig.3. It can be seen how. '

VPA 9/210/4015 -6-

509826/0375

the potential at point 2 increases very quickly, while the potential at point 1 continues to decrease. Corresponding results from the. penultimate line of FIG. 3 "that the potential on the bit line DL1 decreases very sharply, on the other hand, the potential on the bit line DL2 is very strong increases. In the "period of time C, the memory element that has been read SE1 regenerates.

When reading a binary "0", the regeneration amplifier works in the same way. The potential sinks on Control input of the switching transistor T2 from. The potential at point 1 increases accordingly. This is a pre-amplification and negation of the read signal. By closing the feedback branches, the pre-amplified read signal again used to flip the flip-flop.

The areas D and E of FIG. 3 also show how the writing of a signal to a memory element takes place can. To write information into a memory element SE, the corresponding bit line DL the corresponding potential is applied from the outside. But it must be ensured that the regeneration amplifier this Potential cannot interfere. For this reason, the transistors T7 and T8 in the feedback branch are blocked. the Potentials at points 3 and 4 of the regeneration amplifier can then be influenced from outside. These relationships are shown in FIG. 3 by the dashed lines.

The inventive mode of operation ensures that the regeneration amplifier initially works as a preamplifier for the read signal applied and that the regeneration amplifier is connected to a flip-flop only after the read signal has been preamplified Regenerierverstärker a greater sensitivity for the read signals. the flip-flop abzunehmende the signal is larger. the result is greater allowable manufacturing tolerances for

VPA 9/210/4015 -7-

509826/0375

the flip-flop and, associated with it, a greater yield on functional circuits «, continue to enable smaller read signals a smaller area for the memory cells and thus a higher degree of integration.

The invention has been described on a regeneration amplifier, in which the operating point with the aid of two transistors can be set separately for each flip-flop branch can. Since the type of operating point setting for the invention is unimportant, it is only necessary that the The operating point is set, the invention is not in the manner shown in Figure 1 of the operating point setting limited.

The transistors in FIG. 1 are field effect transistors been used.

The structure of the memory from individual memory elements can done in a known manner.

1 claim
3 figures

VPA 9/210/4015 ■ -8-

509826/0375

Claims (1)

Claim Method for operating a read and regeneration amplifier constructed in the manner of a clocked flip-flop, which consists of two feedback inverters, each with a switching transistor and a load transistor, the Read signals from transistor storage elements are each fed to the control input of the switching transistors, in the case of the transistors inserted in the feedback branch before the arrival of a read signal Feedback branches are separated and the operating point is set in the flip-flop branches and at after the arrival of the read signal, the transistors arranged in the feedback branches are again turned on so that the flip-flop flips into the position determined by the read signal, characterized in that that the load transistors (T3, T4) and the switching transistors (T1, T2) during the time during which a Read signal is applied to one of the inverters, can be controlled conductive, so that this inverter as a preamplifier works and pre-amplifies the applied read signal and that then the pre-amplified read signal for through-connection of the flip-flop is used in the position determined by the read signal. VPA 9/210/4015 509826/0375