DE2348705A1 - Sixteen to eight bit code converter - converts twice sixteen code to eight bit binary with parity bit - Google Patents

Abstract

Each of the two (116) signals is converted by a separate diode matrix in the four bits of an eight bit code, so that the characteristic wire for the input phi of the (116) signal becomes unnecessary. The remaining 15 input wires in each matrix are connected with the four outputs for the binary code, so that in absence of a signal at one of the inputs, the signal phi appears at the output wires. Each matrix has a fifth output wire for the party bit, so connected with the 15 input wires, that a parity is always produced. The parity bit wire in each matrix is connected to an equivalence gate, at whose outout an odd parity always appears for both matrices.

Description

AKTIENGESELLSCHAFT Munich, February 2, 1973

Berlin and Munich Wittelsbacherplatz 2

73/6696

Facility for transcoding

The invention relates to a device for recoding a 2 χ (.j) code into an 8-Mt binary code with parity bits.

It is often necessary to convert the messages coming from a switching network in code 2 χ (..) into a binary code in a transcoder so that a downstream computer or other evaluation device can evaluate the information. A parity bit is always supplied, which is used to check whether the information has been transmitted correctly. As agreed, an odd parity bit is used, ά.tu a parity bit that is added to the ^!: £ < ⁿ i-su of an odd number in a bit.

However, one difficulty arises in this case »if none Input is addressed, as there is no for this Pail either Message occurs, which is a seventeenth piece of information for each of the two (..) codes or a zv / one hundred and fifty-seventh Information for the entire switching matrix means

The object of the present invention is therefore to provide a transcoder for transcoding 2 χ (.j) information to create an 8-bit binary code, which is also used for the Pail, for which no information is available at one of the inputs, supplies an odd parity bit.

To solve this problem, the device for recoding according to the invention is designed in such a way that each of the two ( \ ) pieces of information is stored in a separate diode

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matrix is converted into 4-bit of the 8-bit binary code in such a way that in each matrix the line characteristic of input 0 of the ('' ^ information is omitted, and that the fifteen input lines remaining in each matrix each have four output lines. for the binary code are coupled in such a way that the message 0 appears on the output lines without information at one of the inputs, and that a fifth line for the parity bit is provided in each matrix, which is coupled to the fifteen input lines so that parity is always even arises and that the line for the parity bit of each matrix is connected to an equivalence gate - at the output of which an odd parity always appears for both matrices together.

These measures give the advantage that, even if there is no information at the input, always binary information "O" and an odd parity bit is output.

The invention is explained in more detail with reference to FIGS. 1 and 2.

In FIG. 1, a block diagram consisting of the switching matrix 1 and the transferring device 2 is shown. The coupling matrix 1 has the property that its switching status is reported when it is queried. This query is made in such a way that an output line KA of the switching matrix is specified via special interrogation lines and the switching matrix via own message lines that coupling field input line KE reports that currently with the entered switching matrix output line KA is connected. With a switching matrix for a maximum of two hundred and fifty-six input and two hundred Fifty-six output lines are required for the query in the binary code, eight lines and another eight Lines for reporting. Each of these 8-bit pieces of information are monitored with an additional parity bit. the

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Messages are initially in the switching matrix in the code 2 χ (\ j) brought and then in a transcoder 2 in the 8-bit binary code implemented with parity bit.

FIG. 2 shows schematically the transcoder 2, which essentially consists of two identically structured diode matrices, of which, for reasons of simplicity, only the left is shown in more detail. In this case, the incoming sixteen lines are from left to right the (^^ information is shown, the information being respectively at one of the inputs 0-15 as ground potential can, while the four lines for the binary code are shown perpendicular to it, with the output at the bottom Rope of drawing lies. The line for the Wull entrance is drawn with dashed lines because, as will be explained later, it can be given away. In addition to these four lines, a further fifth line is drawn, which serves as a parity line for an even parity bit Pg. In addition, the links are made with the help of diodes of the input and output lines shown, which take place according to the following input scheme, where in the the top horizontal row the respective lines for the binary code and in the first vertical column the lines

16
are given for the (^) code. -

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8th 4th 2 1 Pg O 0 0 0 0 0 1 0 0 0 1 L. 2 0 0 1 0 I. 3 0 0 L. L. 0 4th 0 I. 0 0 I. 5 0 L. 0 L. 0 6th 0 L. L. 0 0 7th 0 L. L. L. 1 8th I. 0 0 0 I. 9 L. 0 0 0 10 L. 0 L. 0 0 11 L. 0 I. l I. 12th L. Ii 0 0 0 13th L. L. 0 I. I. 14th I. L. L. 0 L. 15th L. L. I. L. 0.

1 means the same. Ground and 0 each + voltage.

With the matrix and the scheme given above, one recognizes, however, that if none of the sixteen inputs is controlled with an "L", the message 0000 appears at the output, which would also appear if input 0 with an " L "is controlled. This means that this input and the line leading to it can be dispensed with, so that the message appearing at input 0 is set equal to the message "no message" for each of the diode matrices,

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The two parity lines of the diode matrices for the even-numbered parity bits Pg are then connected to the input of an equivalence gate, at its output due to The two other schemes given below emit an odd parity bit Pu for every eight bits will. In the diagram on the left, "g" means even-numbered and "u" means odd-numbered, while the diagram on the right means the desired one Represents linkage.

0 + O = LO ₊ L = OL ₊ O = O L ₊ L = L

P H
G ^p g P H
S. ^p u P H
U ^P u ^hP g = ^hp g =

Since this gate has a? "L" and when they meet an even-numbered item of information with an odd-numbered item of information should result in a "0", is used as a summary Gate uses an equivalence gate that has these properties.

1 claim

2 figures

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Claims (1)

Patent response r u c h Device for recoding a 2 χ (^) code into an 8-bit binary code with parity bit, characterized in that each of the two (^ -information is converted in a separate diode matrix into 4-bit of the 8-bit binary code that In each matrix the line characteristic for input 0 of the (^) information is omitted, and that the fifteen input lines remaining in each matrix are each coupled to four output lines for the binary code in such a way that the message 0 is sent to one of the inputs without any information appears on the output lines, and that in each matrix a fifth line is provided for the parity bit, which is coupled to the fifteen input lines, that parity always arises and that the line for the parity bit of each matrix is connected to an equivalence gate, on its Output for both matrices together always an odd parity appears. VPA 9/631/0008 509817/0924