DE2348323A1 - Multi-component semiconductor integrated cct. - has metal terminal contacts on mesa edge of individual ccts. - Google Patents
Multi-component semiconductor integrated cct. - has metal terminal contacts on mesa edge of individual ccts.Info
- Publication number
- DE2348323A1 DE2348323A1 DE19732348323 DE2348323A DE2348323A1 DE 2348323 A1 DE2348323 A1 DE 2348323A1 DE 19732348323 DE19732348323 DE 19732348323 DE 2348323 A DE2348323 A DE 2348323A DE 2348323 A1 DE2348323 A1 DE 2348323A1
- Authority
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- Germany
- Prior art keywords
- semiconductor
- semiconductor body
- edge
- contacts
- semiconductor surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000002184 metal Substances 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 238000010276 construction Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 7
- 238000002161 passivation Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 210000002105 tongue Anatomy 0.000 description 2
- 241000239290 Araneae Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Licentia Pa tent-Verwaltungs-GmbHLicentia Patent-Verwaltungs-GmbH
6 Frankfurt/Main, Theodor-Stern-Kai 16 Frankfurt / Main, Theodor-Stern-Kai 1
Ileilbronn, den 12. Sept. 1973 PT-Ma/sr - HN 73/32Ileilbronn, September 12, 1973 PT-Ma / sr - HN 73/32
Integrierte Festkörperschaltung mit einer Vielzahl von Bauelementen in einem gemeinsamen Halbleiterkört) erIntegrated solid-state circuit with a large number of components in a common semiconductor core) he
Die Ex-jfindung betrifft eine integrierte Festkörperschaltung mit einer Vielzahl von Bauelementen in einem gemeinsamen Hcilbleiterkürper und mit metallischen, für die drahtlose Kontaktierung vorgesehenen Anschlußkontakten an der Halbleiteroberfläche. The discovery relates to an integrated solid-state circuit with a large number of components in one common Semiconductor body and with metallic, for wireless Contacting provided connection contacts on the semiconductor surface.
Man geht mehr und mehr dazu über, llalbleiteranordnungen, insbesondere integrierte Schaltungen, drahtfrei zu kontaktieren. Dabei geht man von einem metallischen Kontaktierungsstreifen aus, der rahmenförmige Teile enthält. In das Innere der Kahmeη ragen vom Rahmen ausgehende, streifenförmige Kontaktierungsfinger, wobei jeweils ein Finger für den Anschluß an eine Jilektrode einer Halbleiteranordnung vorgesehen ist.There is more and more going on, semiconductor arrangements, in particular integrated circuits to contact without wires. This is based on a metallic contact strip which contains frame-shaped parts. In the interior of the Kahmeη protrude from the frame, strip-shaped contacting fingers, one finger in each case being provided for connection to an electrode of a semiconductor device.
509814/0559509814/0559
Die Halbleiteranordnung wird mit ihren über die Halbleiteroberfläche ragenden Metallanschlußkontakten so auf den Kontaktierungsstreifen aufgesetzt, daß die Kontakte auf der Halbleiteroberfläche mit je einem freien Ende eines zugeordneten Kontaktierungsfingers in Berührung gelangen. Danach werden in einem Arbeitsgang oder nacheinander alle Elektrodenanschlüsse mit den Kontaktierungsfingern durch Löten, Schweißen oder Thermokompression, elektrisch leitend verbunden. The semiconductor arrangement is with its over the semiconductor surface protruding metal connection contacts placed on the contacting strip that the contacts on the Semiconductor surface come into contact with one free end of an associated contacting finger. Thereafter are all electrode connections with the contact fingers by soldering in one operation or one after the other, Welding or thermocompression, electrically connected.
Bei dieser Art der Kontaktierung verlaufen die Kontaktierungsfinger zwangsläufig parallel zur Halbleiteroberfläche. Wenn die Halbleiteroberfläche nicht ausreichend mit einer Isolierschicht abgedeckt ist, bestellt daher die Gefahr; daß an diesen Stellen Kurzschlüsse zwischen der Halbleiterelementkante und den Kontaktierungsfingern auftreten.With this type of contact, the contact fingers run necessarily parallel to the semiconductor surface. If the semiconductor surface is insufficient with an insulating layer is covered, therefore ordered the danger; that at these points short circuits between the semiconductor element edge and the contacting fingers occur.
Bei den bisher üblichen Fertigungsmethoden konnten jedoch Kurzschlüsse nicht immer vermieden werden. Bei der* Herstellung der integrierten Schaltungen geht man von einer gemeinscimen Halbleiterscheibe aus, auf der sich in der Regel eine Vielzahl gleichartiger Halbleiterschaltungen befinden. Die Halbleiter-However, short circuits could not always be avoided with the production methods customary up to now. In the preparation of the integrated circuits are based on a common semiconductor wafer, on which there is usually a large number similar semiconductor circuits are located. The semiconductor
509814/0559509814/0559
scheibe muß daher in Einzelemcnte aufgeteilt werden. Bei einem neueren Verfahren werden die Halbleiterscheibeninit Hilfe eines gesteuerten' Laserstrahles zerteilt. Hierbei entstehen Kui-zschlußgefahrenstellen, wie sie zum besseren Verständnis in der Figur 1 dargestellt sind.disk must therefore be divided into individual parts. at In a more recent process, the semiconductor wafers are divided up with the aid of a controlled laser beam. Here arise Short-term danger points, as they are for a better understanding are shown in FIG.
In dieser Figur ist ein, nur einen Kontakt aufweisender, Teil eines Einzelelementes dargestellt. Die Halbleiterzone 1 ist über eine metallische Leitbahn 2, die sich über eine Oxydschicht 3 erstreckt mit einem Anschiußkontakt h verbuiiden. Dieser Anschlußkontakt h ist relativ dick und ragt über die die Halbleiteroberfläche bedeckenden Passivierungsschichten hinaus. Die Halbleiteroberfläche wird mit Ausnahme des Kontaktes k in der Kegel noch mit einer zusätzlichen Passivierungsschicht 5 bedeckt. Durch das Anritzen oder Zerteilen der Halbleiterscheibe in it Hilfe eines Laserstrahles entsteht am Rande des Einzelelementes ein Graben 6 mit einem aufgeworfenen Trenngrat 7· An der· äußeren übdr die Halbleiteroberfläche hochrangenden Spitze dieses Grates 7 ist die Halbleiteroberfläche frei zugänglich, da die Passivierungsschichten 3 und 5 nur bis zum Rand des Grates reichen. An dieser Stelle treten bevorzugt Kurzschlüsse zwischen dem Koutaktierungsfiiigcrn 8 und der Halbleitorzone 1 auf. Der Kontakticrungs·In this figure, a part of an individual element that has only one contact is shown. The semiconductor zone 1 is connected to a connection contact h via a metallic interconnect 2, which extends over an oxide layer 3. This connection contact h is relatively thick and protrudes beyond the passivation layers covering the semiconductor surface. With the exception of the contact k , the semiconductor surface is generally covered with an additional passivation layer 5. By scratching or dividing the semiconductor wafer with the help of a laser beam, a trench 6 with a raised separating burr 7 is created at the edge of the individual element only reach to the edge of the ridge. At this point, short circuits preferably occur between the contacting wire 8 and the semiconductor zone 1. The contact
509814/0559509814/0559
finger 8 .ist streifenförmig ausgebildet, mit dem Anschlußkontakt k verlötet oder angeschweißt und im allgemeinen ein Teil einer rahmenförmig ausgebildeteten Kontaktierungsspinne mit nach innen ragenden Kontaktierungsfingern, die wiederum auf einen für die Aufnahme des Halbleiterkö.rpers geeigneten Kortaktierungsstreifen befestigt iat.finger 8 .is strip-shaped, soldered or welded to the connection contact k and generally part of a frame-shaped contacting spider with inwardly protruding contacting fingers, which in turn are fastened to a contacting strip suitable for receiving the semiconductor body.
Der Erfindung liegt nun die Aufgabe zugrunde, die Kurzschlußgefahr zwischen dem Kontaktierungsfinger und der Halbleiteranordnung zu beseitigen. Diese Aufgabe wird erfindungsgemäß dadurch gelöst, daß der Rand, jedes, eine Einzelschaltung enthaltenden Halbleiterkörpers mesaför/pig abgestuft bzw. abgeschrägt ist, und daß die Abstufung bzw. Abschrägung mit einer Isolierschicht bedeckt ist.The invention is based on the problem of eliminating the risk of short circuits to eliminate between the contacting finger and the semiconductor arrangement. This object is achieved according to the invention solved in that the edge of each, a single circuit containing semiconductor body mesaför / pig stepped or beveled and that the slope is covered with an insulating layer.
Durch diese Maßnahme wird der äußere Rand des die Schaltung enthaltenden Halbleiterkörpers gegenüber der die Kontakte aufweisenden Halbleiteroberfläche so weit abgestuft, daß die streifenförmigen Kontaktierungsfinger nicht mehr den Raid des Halbleiterkörpers berühren können. Dann wird auch der beim Laserritzen entstehende Grat an der Außenkante so weit abgesetzt, daß für die Kontaktierungszungen keine Kurzschlußgefahr mehr besteht.As a result of this measure, the outer edge of the semiconductor body containing the circuit is opposite that of the contacts having semiconductor surface so far that the strip-shaped contacting fingers no longer the raid of the Can touch semiconductor body. Then the burr created by laser scoring is set off on the outer edge to such an extent that that there is no risk of short circuits for the contacting tongues there is more.
509814/0559509814/0559
BAD Qf%5GINALBAD Qf% 5GINAL
Früher versuchte man einer Kurzschlußgefahr dadurch zu entgehen, daß die Anschlußkontakte 5 (Fig· l) möglichst dick ausgebildet wurden, um auf diese Weise einen möglichst großen Abstand zwischen den Kontaktierungszungen und der Halbleiteroberfläche zu gewinnen. Diese Maßnahme ist teuer, da es sich neist um Goldkontakte handelt, und außerdem zeitraubend. Bei der erfindungsgemäßen Anordnung kommt man dagegen mit relativ dünnen Goldkontakten aus, da eine Kurzschlußgefahr nicht mehr besteht und nur noch gewährleistet sein muß, daß die Kontakte mit den Kontalctierungszinken sicher verlötet werden können.Previously an attempt was made to avoid the risk of a short circuit by making the connection contacts 5 (FIG. 1) as thick as possible were designed in this way as large a distance as possible between the contacting tongues and the semiconductor surface to win. This measure is expensive, since it is mostly gold contacts, and also time consuming. at the arrangement according to the invention, however, comes with relatively thin gold contacts, as there is no longer a risk of short circuits exists and only has to be ensured that the contacts can be safely soldered to the Kontalctierungszinken.
In der Figur 2 ist ein Ausschnitt einer Halbleiteranordnung dargestellt, bei der der äußere Rand mesaförmig abgestuft ist. Der Bereich der Stufe 9 ist mit einer die Kontakte abdeckenden Isolierschicht 5 passiviort, so daß im Bereich der Stufe kein Kurzschluß zwischen dem Kontaktierungsfinger 8 und der Ilalbleiterzone 1 auftreten kann. Die Isolierschicht besteht vorzugsweise aus pyrolytisch abgeschiedenem Silizium-FIG. 2 shows a section of a semiconductor arrangement shown, in which the outer edge is mesa-shaped stepped. The level 9 area is one of the contacts covering insulating layer 5 passiviort, so that in the area No short circuit between the contacting finger 8 and the semiconductor zone 1 can occur in the stage. The insulating layer consists preferably of pyrolytically deposited silicon
dioxyd oder aus Glas.dioxide or made of glass.
In der Figur 3 ist der Teil einer unzertrennten Halbleiterscheibe dargestellt, die jeweils nur einen Kontakt zweier benachbarter Schaltkreise und den dazwischenliegenden Trenngraben 10 umfasst. Vor oder nach der Herstellung der KontakteIn FIG. 3, the part of an unseparated semiconductor wafer is shown, which in each case comprises only one contact between two adjacent circuits and the separating trench 10 lying between them. Before or after making the contacts
5098U/05595098U / 0559
wird rait Hilfe der bekannten Fotolackmaslcierungs- und Ätztechnik, in die Halbleiterscheibe 10 ein Graben eingeätzt, der jeweils einen Bereich einer integrierten Festkö'rperschal-.tung umschließt. Dieser Graben weist bei einem bevorzugten Ausführungsbeispiel eine Tiefe von etwa kO ,um auf bei einer Breite von 8o ,um an der breitesten Stelle. Der zum Ritzen verwendete Laserstrahl hat eine Einflußbreite von etwa 40 ^um. Dieser Bereich ist in der Figur gestrichelt (ll) hervorgehoben. Der Trenngraben 10 wird vor dem Ritzen der Halbleiterscheibe mit dem Laserstrahl mit'einer Passivierungsschicht bedeckt, die sich beispielsweise bis zu den Anschlußkontakten k erstreckt. Zuvor wurde die Halbleiteroberfläche vorzugsweise mit den in den bereits vorangegangenen Figuren erwähnten Passivierungsschichten 3 und 5 versehen. Da nach dem Zerteilen der Halbleiterscheibe der abgeschrägte Randteil der Halbleiteranordnungen mit einer Jfeaüerschicht 12 passiviert ist, kann kein Kux'schluß mehr zwischen dem Kontakiierungsfinger und dem Halbleitermaterial 1 auftreten.With the aid of the known photoresist masking and etching technology, a trench is etched into the semiconductor wafer 10, which in each case encloses an area of an integrated solid-state circuit. In a preferred exemplary embodiment , this trench has a depth of approximately kΩ .mu.m and a width of 8o .mu.m at the widest point. The laser beam used for scribing has an influence width of about 40 μm. This area is highlighted in the figure with dashed lines (II). Before the semiconductor wafer is scratched with the laser beam, the separating trench 10 is covered with a passivation layer which extends, for example, as far as the connection contacts k . Previously, the semiconductor surface was preferably provided with the passivation layers 3 and 5 mentioned in the previous figures. Since the beveled edge part of the semiconductor arrangements is passivated with a junction layer 12 after the semiconductor wafer has been cut up, a connection between the contact finger and the semiconductor material 1 can no longer occur.
Die Höhendifferenz zwischen der die Kontakte aufweisenden Halbleiteroberfläche und dem äußersten Rand des Einzelelementes beträgt etwa 20 bis 40 «um. Durch die dadurch ermöglichte Reduzierung der Schichtdicke der Goldkontakte k erhält man Kontakte mit vergrößerter Haftfestigkeit, so daß auf diese Weise auch die Zahl der Ausfälle reduziert werden konnte·The difference in height between the semiconductor surface having the contacts and the outermost edge of the individual element is approximately 20 to 40 μm. As a result of the reduction in the layer thickness of the gold contacts k that is made possible, contacts with increased adhesive strength are obtained, so that the number of failures could also be reduced in this way.
5098U/05595098U / 0559
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19732348323 DE2348323A1 (en) | 1973-09-26 | 1973-09-26 | Multi-component semiconductor integrated cct. - has metal terminal contacts on mesa edge of individual ccts. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19732348323 DE2348323A1 (en) | 1973-09-26 | 1973-09-26 | Multi-component semiconductor integrated cct. - has metal terminal contacts on mesa edge of individual ccts. |
Publications (1)
Publication Number | Publication Date |
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DE2348323A1 true DE2348323A1 (en) | 1975-04-03 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE19732348323 Pending DE2348323A1 (en) | 1973-09-26 | 1973-09-26 | Multi-component semiconductor integrated cct. - has metal terminal contacts on mesa edge of individual ccts. |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2813968A1 (en) * | 1977-04-01 | 1978-10-12 | Nippon Electric Co | SEMI-CONDUCTOR ARRANGEMENT WITH CONTACT TUB CONNECTIONS |
DE3122740A1 (en) * | 1980-06-10 | 1982-03-18 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | SEMICONDUCTOR COMPONENT |
US5230823A (en) * | 1989-05-22 | 1993-07-27 | The Procter & Gamble Company | Light-duty liquid or gel dishwashing detergent composition containing an alkyl ethoxy carboxylate surfactant |
FR2799306A1 (en) * | 1999-10-04 | 2001-04-06 | Gemplus Card Int | IC chip, especially having conductive side faces, is insulated by depositing a low viscosity insulating material on an active face surface portion between connection bumps |
FR2800198A1 (en) * | 1999-10-26 | 2001-04-27 | Gemplus Card Int | Protection procedure for Integrated circuit chip, uses vacuum suction to spread insulating material between supporting layers holding chips |
WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
-
1973
- 1973-09-26 DE DE19732348323 patent/DE2348323A1/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2813968A1 (en) * | 1977-04-01 | 1978-10-12 | Nippon Electric Co | SEMI-CONDUCTOR ARRANGEMENT WITH CONTACT TUB CONNECTIONS |
US4188636A (en) * | 1977-04-01 | 1980-02-12 | Nippon Electric Co., Ltd. | Semiconductor device having bump terminal electrodes |
DE3122740A1 (en) * | 1980-06-10 | 1982-03-18 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | SEMICONDUCTOR COMPONENT |
US4539582A (en) * | 1980-06-10 | 1985-09-03 | Tokyo Shibaura Denki Kabushiki Kaisha | Anti-short bonding pad structure |
US5230823A (en) * | 1989-05-22 | 1993-07-27 | The Procter & Gamble Company | Light-duty liquid or gel dishwashing detergent composition containing an alkyl ethoxy carboxylate surfactant |
FR2799306A1 (en) * | 1999-10-04 | 2001-04-06 | Gemplus Card Int | IC chip, especially having conductive side faces, is insulated by depositing a low viscosity insulating material on an active face surface portion between connection bumps |
WO2001026151A1 (en) * | 1999-10-04 | 2001-04-12 | Gemplus | Method for insulating an integrated circuit chip by substance deposit on the active surface |
FR2800198A1 (en) * | 1999-10-26 | 2001-04-27 | Gemplus Card Int | Protection procedure for Integrated circuit chip, uses vacuum suction to spread insulating material between supporting layers holding chips |
WO2001031702A1 (en) * | 1999-10-26 | 2001-05-03 | Gemplus | Method for protecting integrated card chips by deposit of an electrically insulating layer by vacuum suction |
WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
FR2808920A1 (en) * | 2000-05-10 | 2001-11-16 | Gemplus Card Int | Method for protecting chips arranged on a wafer comprises cutting wafer to loosen chips, depositing electrically insulating layer on active surface and flanks of at least one chip, and clearing at least one opening in the insulating layer |
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