DE2347103A1 - Integrated semiconductor circuit - with ferromagnetic layers has substrate of semiconductor material - Google Patents

Abstract

The substrate has a structure of an integrated circuit and an insulating surface layer comprising storage cells made of ferromagnetic material and vapour-deposited track runs. The track runs are electrically insulated from each other, from the semiconductor material and from the magnetic layer. The substrate consists of silicon and the insulating surface layer consists of a coating of silicon oxide. The semiconductor slice is converted to a system of zones of different types of circuitry by masking and doping. Metallic track runs connect the storage cells to the integrated circuit components, the elements of the integrated circuits and the storage cells.

Description

Licentia Patent Verwaltungs-G.m.b.H.

6 Frankfurt / Main 70, Theodor-Stern-Kai 1

Jacobsohn / gö HN 69/78

1Q.9-1973

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"Integrated semiconductor circuit with ferromagnetic layers"

The invention relates to an integrated semiconductor circuit with ferromagnetic layers and a method their manufacture.

Circuits of this type are used, for example, for the construction of addressable information memories, shift registers, Counters or flip-flops are used. Today they are generally produced as thin-film memories, which makes it possible to reduce the access times of the core memory Ferrites with a rectangular magnetization loop, which are around 300 / usec, can be further reduced.

According to known methods thin-film memory are produced in such a way that thin magnetic layers on a suitable substrate, for example made of glass or ceramic, can be applied. The magnetic layers are deposited by vapor deposition, cathode sputtering or galvanic processes. The electrically conductive connection of these thin-film memory cells for example with modulation circuits or sense amplifiers was previously either due to the somewhat

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Conventional and expensive multichip technology with different substrates or - better - in a hybrid technology possible. In this hybrid technology, on the same substrate that carries the ferromagnetic memory cells, structured conductive metal layers, for example gold layers, vapor-deposited and onto these metal layers then unencapsulated integrated circuits mounted, z. B. in the "ceramic channel technology" or in screen printing circuits in the "flip-over technique" or in the "beam-lead technique" soldered on.

However, this method of the hybrid technique has the disadvantage that a plurality of conductive connection points must be made individually between the semiconductor components and the magnetic components. The contacts of the semiconductor chips must be connected individually and one after the other with the help of about 25 μm thick gold wires the parts of the structured gold layer are connected, which are interconnects of the magnetic components. This kind The contacting is time-consuming and, moreover, experience has shown that it is often the cause of a certain susceptibility to failure of the components.

The object of the invention is to provide an arrangement for an integrated semiconductor circuit with ferromagnetic layers and to specify a method for their production, whereby the production costs, in particular when making contact, be lowered. At the same time, however, a higher reliability of the elements should also be achieved and the source of errors the inadequate contacts are eliminated.

This object is achieved according to the invention in the case of an integrated semiconductor circuit with ferromagnetic layers solved in that the substrate consists of semiconductor material having an integrated circuit structure and is provided with an insulating surface layer on which memory cells made of ferromagnetic material are located

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and vapor-deposited conductor tracks that - if necessary - Electrically isolated from each other, from the semiconductor material and from the magnetic layer by insulating disks are. It is expedient to use silicon for the semiconductor material and silicon for the insulating surface layer Oxide layer, in particular a layer made of an oxide of silicon to choose.

To produce the circuit described, it is assumed that a semiconductor wafer is initially produced according to the known Process of integrated film and integrated semiconductor technology by masking and doping with impurities constituent elements is transformed into a system of areas of different conduction types. However then not all, as is customary in the case of the known "methods for producing a monolithic semiconductor circuit" Elements that are arranged on the common semiconductor single crystal, one below the other with the aid of a metal film contacted, but initially provided with an insulating oxide layer on which the memory cells are made of ferromagnetic Material applied, e.g. B. vaporized. Metallic interconnects are vapor-deposited on it, which in one Work step at the same time the connection of the memory cells with the integrated circuit parts, the connection of the elements of the integrated circuits with one another and the connections between the memory cells.

The arrangement and the method according to the invention achieve a high reliability of the circuits, because the vapor-deposited interconnects create a connection between magnetic and semiconductor components that is less prone to failure than was the case with the custom-made connections. At the same time it is practically a work step saved because the evaporation of the interconnects anyway for the connection of the elements of the integrated Circuits and for the manufacture of the memory cells is required. This is particularly beneficial

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from that the multitude of connections so far only in one could be produced consecutively in time, but in the method according to the invention all to be contacted Bodies can be connected simultaneously in a single production step.

Another advantage of the circuit according to the invention is seen in the fact that by suitable design of the selection circuits only one memory cell is activated for each memory cell. The same goes for the sense amplifiers, each of which can optionally be arranged in the immediate vicinity of the storage cells. This Advantage has an economic reason. This is because it is economical in the case of arrangements which correspond to the state of the art not responsible, for each individual memory cell z. B. a transistor on a glass plate as a substrate to solder. Even if many transistors were integrated in one semiconductor chip, the expense for the large number of the individual contacts to be made cannot be tolerated. The arrangement according to the invention, however, allows to provide each memory cell with additional semiconductor components without additional effort, whereby possibly special properties of the memory can be achieved and the circuit technology is easier to meet the respective requirements can be adjusted.

The arrangement enables the memory effect Construction of shift registers, counters or flip-flop circuits, which is not the stored one even with pulsed or switched off supply voltage or pulsed activation Lose information. This means that similar clocked arrangements are possible with bipolar transistors, such as them in MOS circuits. are known. The advantage is below other in the low power consumption.

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Claims (7)

- 5 - HH 69/78 Patent claims: Integrated semiconductor circuit with ferromagnetic see Layers, characterized in that the substrate consists of semiconductor material which has a structure of a integrated circuit and is provided with an insulating surface layer on which memory cells are located made of ferromagnetic material and vapor-deposited strip conductors, which - if necessary - through insulating washers are electrically isolated from each other, from the semiconductor material and from the magnetic layer. 2. Integrated semiconductor circuit according to claim 1, characterized in that the substrate consists of silicon. 3 integrated semiconductor circuit according to claim 1 or 2, characterized in that the insulating surface layer consists of an oxide layer. 4. Integrated semiconductor circuit according to claim 1 to 3, characterized in that the insulating surface layer consists of an oxide of silicon. 5. Method of manufacturing a semiconductor integrated circuit according to claim 1 to 4, characterized in that a semiconductor wafer initially according to the known per se Integrated technology method by masking and doping with impurity-forming elements in a system of areas of different conduction type and converted on the surface with an insulating Oxide layer is provided that on this oxide layer storage cells made of ferromagnetic material and then metallic interconnects for the simultaneous connection of the memory cells with the integrated circuit parts, for Connection of the elements of the integrated circuits and 509812/0953 - 6 - HN "69/78 applied to each other and to connect the storage cells will. 6. The method according to claim 5 _T, characterized in that the memory cells are vapor-deposited. 7. The method according to claim 5? characterized in that the metallic interconnects are vapor-deposited. 509812/0953