DE2340814C3 - Selection device for monolithically integrated storage arrangements - Google Patents

Description

3 4

Structure of a binary number from the characters 0 and L fen the AND gates at the output of this generator

equals. The address of a line thus indicates that ren are only clocked when all address

a whole word, which is why »word signals have run through the generators. Corresponding

address «speaks. The bits that make up the word must be the cycle time of the AND gates to the

are in the different columns; 5 outputs of the decoding device delayed

the address of a column is therefore also used until it is ensured that all

a "-j" bit address ". The consecutive numbering (addressing address signals through their assigned decoding level

ren) of rows and columns is expediently carried out with running.

Dual numbers, from which it follows that memory matrices in the state of the art and in good practice are to ^{contain these of the Repel 2 "rows and 2 m} columns, ie io delays with the aid of a delay line 2 ^{n + m} memory cells to all digits of the binary numbers It is now a matter of decoding the binary encrypted addresses, that is, they have not been decoded by means of switching radio, a delay circuit with portable TcIetionen with the rows or columns of the memory margin on the integrated semiconductor chip itself to be linked. It should be agreed that one set. The generation of the delay outside the row or column is selected when the trainer has the integrated chip The following disadvantages: The subordinate switching function supplies the output variable L. The delay line causes additional costs The inaccuracy of the delay, caused by the delay line itself, but above all the variable L deliver the inaccuracy of the delay to tions. Accordingly, both drivers come into consideration for decoding in the selecting memory chip. The AND function only provides the fen, increases the access time of the memory. The F jupt output variable L, therefore only selects the draw disadvantage is that the duration of the delay is dependent row or column if all input variables aj from the slowest true complement generator are also L at the same time. In the case of the NOR function or the slowest decoding stage of the selection, the same applies to the input variables 0, the device is determined. Therefore, in all of these there is still the task of providing an unnecessarily long delay to the individual positions in cases in which the most unfavorable conditions of the addresses coded as binary numbers are not present. By negating a non-function. 30 that the duration of the delay is determined by the long-so that the chip with the most throughput in the context of a selection in the most unfavorable environment, that is, unleading decoding, is determined. Thus, if one considers the most favorable supply voltage and, less favorably, decoding by means of NOR functions, the temperature has to be corrected, the higher value can be applied to the inputs of the NOR functions either the speed of faster chips in a more favorable reversal gebur.g are not exploited (if they are already 0) or via a non-function. These disadvantages are particularly fed in with integrated tion (if they are L ). The selection requires monolithic memory circuits in FET technology considerably for every binary digit of the coded address logic, since dynamic real-time real-complement generator that is used with the integration generators and decoding stages is often linked to the NOR function . Turn 40. These dynamic circuits have the advantage of low leakage conduction for the selection of a row from η - 4 rows, but the post-matrix one needs \ d η - ld 4 = 2 addresses. In part, that the mentioned delays relative to the implementation of this selection one needs η = 4 are large and undefined. The reason for this lies in the NOR-Gliedcr and 1 d η - ■ 2 real-Complcment-Ge in that with such circuits during the anneratoren. To increase the interference immunity, capacities are discharged and charged at the 45 control input of the real complement generators. between must. It is the object of the invention to specify a selection gate and the inputs of the decoding stages and a device of the type described, which guarantees the lowest possible access time of the memory in common to the outputs of the decoding stages clocked AND elements provided. This AND 50 does, does not require any special effort and elements are only then opened together, simultaneously with the selection device in the same time when all address signals are present. A manufacturing process can be achieved in that, according to the invention, this task will not simulate any unwanted selection for an interference signal. Selection device of the type described at the beginning of the address 55 assigned to each binary digit in that the output of one of the AND signals to be passed through begins at a member at the inputs of the real complement of the AND member at the input of a real corple generator via a replica of a real-compliment generator, runs via the real-complication generator with the clock inputs of the AND-nt-generator, via an AND element, then via a link at the outputs of the real-complcnttJccodicrstufc and finally connected via another AND generator 60 and that the outputs of the element at the output of the decoding stage. Since the signals AND gates at the two outputs of one of all the outputs of an address are always simultaneous by means of the Genuine Compl. Generators and AND gates at the output of the decoding stages can then be used to transmit the decoder calls that are linked.

the clocking must be delayed in relation to each other.

follow. Based on the cycle time of the AND gates in, dall dieTaktimpuisc without the interposition of a

at the entrance of the real-compliment generator to simulate a real-compliment generator

the clock inputs of the AND gates at the output of the Genuine compliment generators are created. A particularly advantageous embodiment consists in that each real complcmcnt generator has an input for one of the coded addresses lower and lower has an input for a high-order coded address and that the clock inputs of the AND gates at the outputs of all true compliance generators are controlled by the output of the AND gate for the high-order dccodiertc address.

With the selection device according to the invention, the necessary delay on the semiconductor chip self-generated. The required accuracy of the delay is achieved by the delay necessary logic circuits can be simulated in the delay circuit. Since the selection device and the delay-generating simulations are on one monolithic Halblcitcrchip are and due to their corresponding structure concurrent parameters exhibit, arises independently of the absolute manufacturing tolerances for all environmental conditions exactly the required delay, so that a very simple control of the memory with optimal access time.

Advantageous refinements of the invention are set out in the subclaims.

The invention is described below with reference to the exemplary embodiments shown in the drawing explained in more detail. It shows

F i g. 1 shows the block diagram of a preferred exemplary embodiment a selection device according to the invention,

F i g. 2 A is the block diagram of a true complement generator,

F i g. FIG. 2B shows the circuit diagram of an exemplary embodiment of the in the selection device according to FIG. 1 usable True complement generator according to FIG. 2 A including the AND gates on the two Outputs in FET technology,

3 A shows the block diagram of a simulation a true complement generator,

Fi g. 3 B shows the circuit diagram of an exemplary embodiment of the simulation according to FIG. 3 A ₁

F i g. 4 shows the circuit diagram of an exemplary embodiment of the in the selection device according to FIG. 1 usable and a decoding stage consisting of a NOR element including the AND element am Output in FET technology and

F i g. 5 shows the circuit diagram of an exemplary embodiment of the simulation of the decoding stage according to FIG. 4th

Since the basics of the selections in the operation of a matrix memory can be assumed to be generally known and are also briefly explained in the introduction to the description, the selection device according to the invention according to FIG. 1, for the sake of simplicity, is designed only for the decoding of four addresses, for example word lines WL1 to WL 4. For the operation of a two-dimensional matrix memory, such a splitting device must of course be provided both for the columns and for the rows. It should be noted that by decoding Id η addresses π selections can be carried out. The selection device requires true complement generators for this in a known manner, i.e. a true complement generator for each digit of the coded address and η decoding stages connected downstream of this, at the outputs of which the decoded ή addresses are formed ¹ . In the selection device according to F ₁ ig. 1, in which the four word lines WL1 to WL 4 are addressed, two true complement generators 2-1 and 2-2 and 4 NOR Dccodicrstufcn 4-1 to 4-4 are provided. In a known manner, the real complement generators and am are at each input and each output

ίο Output of the decoding stages AND elements 1-0 to 1-2 or 3-1 to 3-4 or 5-1 to 5-4 switched on. These AND gates serve as so-called catching glicder, which are then simultaneously durchgcschaltct with the help of a clock signal when their Signaling inputs all signals are pending. As is known, this measure serves to increase the immunity to interference. In the exemplary embodiment under consideration, the inputs of the AND gates 1-1 and 1-2 at the entrance of the real-complcmcnt-Gcncrators 2-1

ao and 2-2 supplied by a memory address register A 1 and A 2 are applied. The clock inputs of these two AND gates are connected to a common clock pulse source T. At the cycle time, addresses A 1 and A 2 are assigned to the two

as is supplied to the assigned true complement generators 2-1 and 2-2. The true complement generators each generate non-negated signals B1 and B 2 and negated signals ZfI and BZ. Each of these signals is applied to the input of an associated AND element 3-1 to 3-4. If all signals B are present, the AND gates 3-1 to 3-4 are switched through together. The determination of this point in time, which is the subject of the invention, will only be described below. The outputs of the AND gates 3-1 to 3-4 are now connected to the inputs of the decoding stages 4-1 to 4-4 in the known logic operation. In the example under consideration, these are NOR elements. The NOR function has the effect that, depending on the applied address A 1, A 2, an address signal is only ever generated at one of the outputs of the decoding stage. The outputs of the decoding device are again connected to the word lines WL1 to WL 4 to be selected via AND gates 5-1 to 5-4 serving as catch gates. The definition of the switching point in time of the decoded address signals C1 to C 4 via the AND gates 5-1 to 5-4 on the assigned word lines WL1 to WL 4 will likewise only be described below.

There is now the requirement to ensure the shortest possible access time for the memory to be addressed. Since the individual switching elements of the selection device necessarily have switching delays, it is necessary, based on the cycle time of the clock pulse T, to delay the switching time of the AND elements 3 at the output of the true complement generators 2 at least until all signals B Complement generators have gone through and are pending at the input of the AND gates 3. Appropriate; applies to the switching time of the AND gates J at the output of the decoder 4. This switching time must be delayed at least until all signals B have passed through the decoder 4 and are pending at the inputs of the AND gates 5. The required! Minimum delay times for the switching time

points are therefore always based on the slowest ringer power loss and where the Selection device or in the case of the invention is of particular importance, since it is timely, on semiconductor chips integrated memory- Hch control impulses delayed against each other, for the "slowest" chip. The time needed.

The advantages of the "faster" chips are being given away rcn. The minimum delay times must also be shown in the block diagram according to FIG. 1 to enable The addresses and signals are similarly labeled to one of the most unfavorable environmental influences, The considerative range can be increased. In addition, it is important to note what has already been done for the

From the block diagram according to FIG. 1 is now the block diagram of FIG. 1 is true that the signacrschcn, like an automatically optimal determination io Ic at the inputs and outputs the same in each case the Durchschaltzcitpunktc the AND gates achieved are designated.

will. The clock T is initially via an AND element. Fig. 2A shows the block diagram of the real-time

1-0 and then via a plement generator 2-1 integrated on the chip from FIG AND element exists. The inputs used to clock the AND gates 3 at the output of the two elements are used in each case from the true complement generator 2. The address A 1 originating from the address register as well as the pulse DCS 2 for clocking the AND gates 5 at the higher address CS, which is used for chip selection, the output of the decoder 4 is supplied by the pulse. The DCS 1 then derives from the address A 1 and automatically and optically outputs the non-negated signal B 1 and the signal BI that has never been negated according to the actual requirements. Fig. 2B shows that the negated as well as the speaking circuit diagram of the true complement gene non-negated output of the AND gates 3-1 and 3-2 rators including the AND gates 3-1 and 3-2 at the output of the true complement generator 2-1 at the two outputs. The transistors 7 * 1, Γ2 via a replica 40 »5 and Γ 3 integrated on the chip form the NAND element, while the Traneiner decoder stage with the clock inputs of the AND transistors TA, TS and Γ6 represent the AND element. Links 5 is connected. It shall be included both AND scarf The two each of transistors Tl and T 9 and obligations 3-1 and 3-2, as in a Se- T 8 and 7 "1O existing source follower provide each lesson process only one of these Elements represent an AND element and deliver the output signal at their output, 30 two signals B1 and 77 T. The two capacitances

At the input of the selection device, additional Cc and Ct are used to accelerate the source to the followers transmitting the addresses A 1 and A 2.

AND gates 1-1 and 1-2 that clocked with these. It is assumed that there are field-effect AND gates 1-0. This AND transistors is of the enhancement type. The result element is a high-order address CS with the following mode of action: During rest, the selection of the chip in question causes the chip selection pulse CS to act on earth, while the AND elements 1-1 and 1-2 have potential , as well as the delayed pulse DCSl. Sodie addresses Al and A2 exceeds the lower order with the transistors and Π, will wear so locked Γ5 that the selection of the word lines that the input for the address A 1 effect on a beauf the relevant chip. Since each 40 can have any level or change the level. Selection of the chip concerned, the AND element 1-0 Via the transistors T 3 and T 6, which provide an output signal, the input of the post-gate electrode is supplied with a charging pulse R , forming 20 at the output of this AND element - the rapid charging of the capacitors Cc and closed follows. Ct. This charge pulse R is at a level that

It should be pointed out that the supply voltage V is equal to 45 in the simulations. Therefore, the genes 20 and 40 are the AND gates 1 and 3, respectively, not after the transistors Γ3 and T6 lc ^: tcnd, so that the conduction must be formed, since their delay bc- satorcn Cc and Ct is applied to the voltage V-VT tliuhirch it is fully taken into account that they will load, where VT is the threshold voltage of the simulations via the outputs of these AND field effect transistors. Once the capacitors limbs are controlled. 50 are charged, the transistors Γ7 and Γ8 conduct,

The structure of the individual switching elements of the invention so that the outputs B1 and 271 at the potential according to the selection device is in principle kept by DCS1 , which in the idle state, as of subordinate importance, since a large number mentioned above, is equal to ground potential. The version of this type that can be integrated is therefore known and, when the transistors T 9 and Γ10 are in the conductive state, is given to the selection device according to the invention.

are reversible. It is only necessary that if the semiconductor chip is to be selected, it must

to adapt accordingly to the replicas. The previously the address A 1 a defined level true complement generators 2 lead thereby have taken one. First it is assumed that the Pe-AND / NAND or an OR / NOR function, which gel has the value of the supply voltage V; then lei decoding stages 4 a NOR or an AND function 60 th the transistors 72 and Γ 9. As soon as the selection is made. tion pulse CS to the value of the supply voltage V

In the following, special execution examples are switched on, the transistors 7 * 1 and TS, select a true complement generator and while the charging pulse R is switched to ground potential, so a simulation and a NOR decoding stage and that the transistors Γ 3 and Block T 6 . Thus, their simulation for a memory in FET technology 65, the capacitor Cc is described in more detail via the transistors Γ 2 and technology. From the function Π discharged while the capacitor Ct charged description it follows that this is dy- After the discharge of capacitor Cc namic circuits are involved, which block the transistors Γ 7 and Γ10, whereas the advantage

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transistors 78 and 79 conduct. Now the pulse R has switched to ground potential, the pulse DCSl blocks the value of the supply voltage V transistor 713. The input capacitance is thus switched. It is connected via transistor 78 to that of transistors 715 and 716 via the transi output for signal Z? 1 transmitted, with the disturbing 712 and 711 discharged, namely with dcrscl-Koiulcnsator C charged, ie the gate source voltage 5 ben time constants such as the supervising capacitor trodcn-Spanming of transistor 78 constant and the real complcmcnt generator Cc or Ct. If this remains correspondingly low-resistance. The output of said input capacitance to below the value for the signal BI is discharged via the transistor 79 to the threshold voltage VT , blocking the transi-earth potential. disturb 715 and 716 the latter gives the exit

If the address signal A 1 is selected on to for the delayed selection pulse DCSl to the ground potential. the transistors 72 and 79 block the charge. The resulting pulse DCSl is switched to the selection pulse CS again to the correspondingly designated input of the AND supply voltage V and the charging pulse R to earth members at the outputs of the true complement potential. Then conduct the transistors 71 and 75, the generator connected. This pulse therefore only switches while the transistors 73 and 76 are blocking. The 15 then to the value of the supply voltage V, if in the capacitor Cc remains charged, since transistor 72, true complement generator of one of the two Kon as mentioned, blocks, while the capacitor Ct capacitors Cc or Ct (simultaneously with its after over the transistor 75 to the potential of the address formation) is discharged, so that the output for the signal A 1 is discharged, which was assumed to be equal to the ground potential of signal BI or B 1 of the true complement generation. The transistors block the gate, which must remain at ground potential, through 78 and 79, while transistor 77 conducts. The transistor 77 and the transistor 78 is securely insulated from the now-connected to the supply voltage pulse DCS I selection pulse DCS I. is transferred to the output for the signal BI, the transistor 723 is used for fast shutdown

whereby the transistor 710 becomes conductive and holds the output of the pulse DCSl after the end of the selection, output for the signal B1 at ground potential. »5 It is received by the negated selection pulse CS

It is seen that in both cases, the controls in seconds, which is on the semiconductor chip by means of a weilcktion resulting level of the signal Bl is equal to the direct quick non-member of the selection level of the signal Al, while the signal BI pulse CS generated will.

assumes the complementary level. This is Fig. 4 shows the circuit of an embodiment

the desired effect of a true complement game of a decoder stage, including the AND generator. Element at the output, for example the NOR element

As already explained with reference to FIG. 1, the 4-1 and the AND element 5-1 from FIG. 1 are now, according to the invention, the true complement generator. In the case under consideration, this NOR element forms 4-1 gate simulated, in order to convert the signal CS to a correspondingly delayed pulse DCSl from the chip selection pulse from the signals B1 and B 2 at the output. From Fig. 3A such a simulation is developed WLl is switched. The transistors 731 20 can be seen. A NAND and 732 must be simulated in a known manner as the input element to which the selection pulse CS to be delayed transistors of the NOR element. The transistors 736 is supplied. The function of the NAND element and 737, whose gate electrode is followed by the charge pulse R for ' ^x -irHT element, 40, provide the necessary charging.

»» 'To get mpuls DCSl. manure. A transistor 738 is used to isolate

Au «. i I ₁ - li ^ iiu see a circuit example for the input and output. The AND gate becomes simulation 20. The NAND gate of the simulation is formed by transistors 739 and 740 and consists of transistors 711, 712 and 713. During the idle state, the Si

In this case, a transistor 714 takes into account the gnaleßl in real-45 and BL at the inputs Erdpoten's complement generator required delay TiAl as well the delayed selection pulse DCS 2. between the address pulses A and the selection Therefore, the transistors 731 and 732 as well as the impuls CS. The capacitor Cc is blocked by the on-transistor 739. The charge pulse R is on output capacitances of the transistors 715 and 716 a level which is equal to the supply voltage V. replicated. The non-member of the replica so therefore the transistors 736 and 737 are conductive, consists of the transistors 715, 716, 717 and so that the capacitor C and the stray capacitance Cg 718, whereby the capacitor Cr is charged to the voltage V-VT for acceleration with is switched on. Since the non-element is for reasons of logic, but not for reasons of ver. After charging, the transistor 738 blocks, delay is required, one strives to use an extremely 55 since its gate-source-electrode voltage down to a fast non-element. For this the value of the threshold voltage VT has decreased. The reason is to further increase the switching Since the capacitor C is charged, the speed of the non-element conducts a tran- transistor 740, so that the connected word transistors 719 to 722 with a capacitor Cg are at the potential of DCS 2 is held, standing circuit is additionally provided, via which 60, as mentioned above, is now equal to ground potential. the charge reversal of the capacitor Cr is controlled. If the memory chip is selected, the

The charge reversal of the capacitor Cr is in this case to the charging pulse R at ground potential, that is to say, the transids pre-disturb 736 and 737 the respective level of the selection pulse CS. Shall taken the word line. must be selected, ie charged, the

If the memory chip is selected, the Selek signals Bl and Bl remain at ground potential. The transmission pulse CS to the value of the supply voltage V transistors 731 and 732 must therefore be held at the same time, so first the transistor 712 is blocked and then the transistor TIl is charged so that the capacitances C and Cg are charged. Since then the loading remains. The transistor 740 thus remains conductive and

"<?

the simulation switching to the value of the supply voltage V is necessary, but not necessary

PulseDCS2 is transmitted on the word line. must contribute to the distortion is

Dabci may the voltage drop across transistor T 40 sought again the embodiment already in

the value of the threshold voltage VT does not exceed the fast inverter mentioned in connection with FIG. 3B

thiimit the transistor 739 remains blocked. So 5 used. This consists of the transistors 746

-the ^ capacitor.iC. remains charged, so that during up to 749 with the feedback capacitor Cr. the

of charging .dor. Word line the gate-source capacitor Cr is thereby via a transistor

Electrode voltage of transistor 740 constant charge or discharge 750 from the suction pulse CS,

and this is kept correspondingly low-resistance. The transistor 741 is used for rapid shutdown

The capacitor C loses during this advance of the pulse DCS2 after the selection has ended. He

No charge to the stray capacitance Cg, as it is controlled by the negated selection pulse US ,

Transistor 738, as mentioned above, blocks. the one on the chip by means of another fast

Should the connected word line not be selected from the non-negative selection pulse

are controlled, ie remain discharged, at least CS must be generated. The capacitor C is through the

at least one of the input transistors 731 or 732 15 input capacitance of the transistors 746 and 747

simulated conductive by a corresponding signal B1, B 2.

power will be. Then, the capacity C and the memory chip is selected, is corresponds Cg through the transistors 738 and 731 and 732 neither transistor 731 'or 732' conducting, discharged there. The transistor 740 blocks only after a discharge below the value of its inputs during the selection at the complete threshold voltage VT . These signals Then, when the pulse DCS2 SSL on the value of the corresponding to the input signal, / I2 of the V '·' - supply voltage V on, the transistor 739 is decoder, except that the latter always oie of various conductive and maintains the connected word line via real- Complement generators are supplied, transistor 738 and the conductive transistor or transients wall the former from the same true complement transistor 731, 732 to ground potential. “5 generators come from. This ensures that the

In Fig. 5 is a circuit example for a replica discharge of the input capacitance of the transistors

tion 40 of the specified NOR element is shown. 746 and 747 always takes place and takes the same length of time

It can be clearly seen that the transistors 731 ', like the discharge of the capacitance C of the slowest

732 ', 736', 737 ' and 738' the transistors 731, unselected NOR gate. Is said input

732, Γ36, 737 and 7'38 of the NOR element after 30 capacitance to below the value of the threshold voltage

Reproduce Fig. 4. The stray capacitance Cg of the NOR- VT is discharged, so the transistors 746 and block

Link is through the appropriate layout through the 747. Only then does the transistor 747 output

Stray capacity Cp simulated. The inputs of gang for the delayed selection pulse DCS2

731 'and 732' are the non-negated signal B1 free for charging. The resulting pulse DCSI

and the negated 2Π supplied. This means that at 35 is sent to the appropriately designated entrance de:

The output of the simulated NOR element is connected to each AND element at the output of the NOR element.

Selection no output signal is supplied. It is lays. The DCS 2 pulse then switches to the

So it is necessary that a replica has a non-value of the supply voltage V, if that is the slowest «

Element is switched up, which the delayed non-electrified NOR element in the Decodiereinrichtunj

Switch-on pulse DCS 2 of AND gates 5 at 40 (simultaneously with its simulation) is discharged, se

Output of the decoder 4 supplies (Fig. 1). that on the one hand no incorrect selection can occur unc

Since this non-member for logical reasons in the other hand, the pulse DCS 2 does not switch too late For this purpose 2 sheets of drawings

Claims (6)

the replica de; Decoding stage from one of the claims: NOR element with the following non-element is put together. 1. Sclcktionseinrichtung for monolithically integrated 7. Selcktionseinrichtung according to claims Gricrtc Spcichcranordnungcn, in which for every 5 surfaces 1 to 5, in which each decoding stage consists of one lliniirslelle of the coded addresses there is a real COM AND element, characterized in that plcmcnt generator is provided, the design of which is the simulation of the decoding stage from a inputs with assigned inputs of the decoding AND element with the following non-element. stages of a decoder are connected, is composed. and in the case of the "8th selection device according to the claims" to increase the immunity to interference the inputs and at the outputs of the real characters I to 7, characterized in that the Complement generators and replicas at the outputs with the actual selection the decoding stages are each integrated with a common clocked device. AND gates are inserted, with the timing via a central, all AND gates
common clock pulse source takes place whose clock- _______ pulses to the clock inputs of the AND gates
the inputs of the real complement generator Ren are connected, and with respect to the other The invention relates to a selection device AND gates according to the existing »o for monolithically integrated memory arrangements, in the case of switching delays in the signal path by using the delay means for each binary digit of the coded addresses, because - a true complement generator is provided, which is characterized by the fact that the output Outputs with assigned inputs of the decoding process of one of the AND gates (1-0) are connected to the input stages of a decoding device, and the true complement generators (2) via a _S in the case of the one to increase the interference immunity to the one (20) of a real complement and at the outputs of the real complement generator (2) with the clock inputs of the AND mcnt generators and at the outputs of the deco elements (3) at the outputs of the real complement dierstufe each jointly clocked AND member management generators (2) is connected and that the are inserted, the timing via a zen outputs of the AND members (3-1, 3-2) to the _{3O t RALC) all} AND gates common clock pulse two outputs one of the real-complement _{source erfo} i _gt> whose clock pulses to the clock inputs of generators (2-1) via a replica (40) _{of the} AND gates at the inputs of the real-Komeiner decoding stage ( 4) are connected to the clock inputs of generators's complement, and bezügder aND gates (5) _{of the} aND gates are respectively connected to the precursor (4) at the output of the decoding _{Lich to} t _he s. ₃₅ existing switching delays in the signal path 2. Selcktionseinrichtung according to claim 1, that the use of delay means are delayed, characterized in that the clock pulses without jj) _he basic structure of a selection device interposition of a replica of a real: _st for example in the De Gruyter textbook »Shah Complement Generators (2 ) to the clock inputs circular technologies for digital computing systems «from the AND gate (3) at the output of the real communication ₄₀ and G. Bai tinger, 1973, described. After that, plement generators (2) are created. the operation of a storage tank is equivalent to the 3. Selection device according to claims 1 continuous solution of the problem of a plurality or 2, characterized in that each real individual bistable memory cells have a certain her complement generator (2) to access an input to write a binary variable there to be able to read out the coded addresses (A) lower and 45 _{o the.} This is possible by assigning an input for a decoded address (CS) _to each memory cell with an address that has a high order and that the clock input expediently encoded in the form of a binary number of the AND gates (3) at the outputs _w i _r d. Before a memory cell can be accessed, the address command belonging to all the true complement generators (2) must be decoded, whereby the relevant cell is selected from the output of the AND element (1-0) for the de- 50. If a multi-coded address (CS) of a high order, controlled by a number of individual memory cells, is put together to form a larger supply unit, this is done for the intended purpose. 4. Selection device according to claim 1 moderately in the form of a matrix, d. H. in lines and or 3, in which each real-complcmcnt-Gcncrator columns. By using both the lines and the 55 columns are numbered consecutively from an AND and a NAND element, each memory is characterized in that the post-image cells are uniquely identified by the addresses Generation of the real supplement generator from one of the associated row and column, at their intersection NAND element with the following non-member to point it is located. When selected, they are made up of components is. half of the memory matrix a fully leaked memory 5. Selection device according to claim 1 60 cell, several semi-selected, namely within the or 3, in which each true complement genera- the same line and within the same column, as well as gate from an OR and a NOR element otherwise unsclektierte Storage cells. Each of the in consists, characterized in that after most cases of a flip-flop consisting of a NOR element with subsequent memory cells is composed of two stable states 0 or L the non-element is composed. 63 capable, so the smallest information unit (bit) can 6. Save training device according to the claims. A number of such FlipfiOjs can Chen 1 to S, in which each decoding stage consists of a larger information unit (word) store, NOR element, characterized in that they can have different lengths and in their