DE2335989B2 - Bucket chain control - Google Patents

Description

The invention is concerned with a problem that occurs with bucket chain circuits, such as those for example from "IEEE Journal of Solid-State Circuits", June 1969, pages 131 to 136, are known, such occurs Bucket chain circuits have a plurality of similar stages, each of which consists of one Transistor and a capacitor lying between its control connection and its collector connection exist and are connected in series in such a way that the collector connection of one is connected to the emitter connection of the next following transistor, wherein the control terminals of the even-numbered transistors from a first square-wave clock signal and the control connections of the odd-numbered transi disturb from a second rectangular and equal frequency clock signal are controlled, the effective pulses in the gaps between the effective pulses of the first clock signal lie. Such bucket chain circuits are in the

bo literature also referred to as shift register or delay line for analog signals.

The problem with such bucket chain circuits is that the DC voltage level in the course of the bucket chain circuit to higher or migrates from lower values, this DC voltage level being derived from the DC voltage applied to the input of a bucket chain circuit, the the signal to be delayed is superimposed, and the

Composed of the same component of the signal to be delayed. This drift of the DC voltage level is, for example, in isolated field effect transistors built-up bucket chain circuits due to the fact that at low clock frequencies a drift of the direct potential in the direction of the substrate potential caused by the reverse current of the diffused zones is, while on the other hand at high clock frequencies the DC voltage level in the opposite direction, due to surface conditions, migrates in bucket-chain circuits made up of bipolar transistors the base current of the transistors causes an effect corresponding to the latter the DC voltage level.

In bucket-chain circuits constructed from bipolar transistors, this problem is encountered according to the above-mentioned reference by so-called level regeneration circuits tried to solve, but with these circuits also the one to be delayed is tried Signal amplified. An application of this well-known principle in Eirnerketterschaltung from isolated In addition, field effect transistors only allow compensation for that caused by surface conditions Effect, while the DC voltage level drifts towards the substrate potential with the known Circuit cannot be prevented.

It is the object of the main patent to provide an improved DC voltage compensation circuit for bucket chain circuits specify, especially in the case of bucket chain circuits made up of isolated field effect transistors allowed to restore the drifted DC voltage level Level correction circuit the original DC voltage level automatic, d. H. in a self-regulating way. This task is carried out by Main patent achieved in that one input of a differential amplifier is the direct component of the potential at the collector connection of a bucket chain input near transistor and the other input of the DC component of the potential at the collector connection of a transistor remote from the bucket chain input is supplied, which two transistors are controlled by the same clock signal, and that one of the two output signals of the differential amplifier capacitive to the collector connection of one of the transistor remote from the bucket chain input preceding transistors is supplied.

In further investigations made by the inventor, it was surprisingly found that in addition to the im Main patent specified solution still another possible solution to the problem of the main patent gives. It is therefore the task of the present additional application, in the wake of the task of the main patent to specify this further solution. This solution specified in claim 1 is based on the knowledge of the inventor that it is not absolutely necessary to capacitively apply the correction signal to the bucket chain circuit but that it is possible to convert the correction signal of the differential amplifier into a proportional To derive a current pulse that can be fed galvanically to the bucket chain circuit.

Further developments and preferred exemplary embodiments of the invention are set out in the subclaims and are now identified together with the invention with reference to the one shown in the drawing Figures explained in more detail.

F i g. 1 shows the principle of the solution according to the invention;

F i g. 2 shows a level correction circuit for a consisting of p-channel insulating film field effect transistors Bucket chain switch;

Fig.3 shows a level correction circuit for a consisting of n-channel insulated gate field effect transistors Bucket chain control, and

FIG. 4 shows the principle of a two-stage self-regulating level correction circuit using the principle according to the invention.
In the upper half of FIG. 1 are schematic

ίο some stages of a conventional bucket chain circuit EK shown stages m, nl, η and n + shown 1 m the steps and π are in this case from the first clock signal Φ \ and steps n 1 and n + controlled by the second clock signal Φ7 1 Each clock signal consists of a rectangular uwi ^ leichfrequenten voltage on the SchaltungsnuRpurkt is related, wherein the amplitude of one clock signal is in the gap between the effective pulses of the other clock signal and vice versa. Here, the duty cycle of the clock signals can be 0.5; However, it is of course also possible to choose a pulse duty factor which deviates from this pulse duty factor in such a way that gaps occur between the effective pulses of the two clock signals, during which gaps occur

jo both clock signals are zero.

The mode of operation of such a bucket chain circuit is known to be that at the end of a Clock pulse every second stage, i.e. every odd-numbered or every even-numbered stage, a piece of signal information

j5 in the form of an im belonging to each level Capacitor contains stored amount of charge, while the capacitors of the intermediate Stages are discharged and therefore contain no information.

The principle on which the invention is based is the same? tension level regeneration or constant maintenance of the input DC voltage level consists of the potentials of a bucket chain input and the stage remote from the bucket chain input to the two after appropriate suppression of the signal component To feed the inputs of a differential amplifier and a current pulse proportional to its output signal one of the transistors preceding the transistor far away from the bucket chain entrance, galvanically in phase to feed.

In the schematic diagram according to FIG. 1, this stage preceding the stage η remote from the bucket chain input is the directly preceding stage n- 1. As the input-close stage m , the first delaying stage of the bucket chain circuit is preferably chosen, at the collector connection of whose transistor the DC potential still has its full setpoint , which ensures optimal control of the bucket chain circuit. Those to the collector; connections of the two transistor

Signals picked up from the stages m and η are each fed to the two inputs E \ and E _{2 of} the differential amplifier DVX via the high-value resistors Rc 1.

The high-resistance resistors in the main patent specified transistor jn serve.

Furthermore, the two inputs of the differential amplifier are each connected to the circuit zero point via the capacitor Cot, whereby the resistor

The value of Ra and the capacitance of the capacitor are chosen such that this RC combination acts as a low-pass filter for the signal frequencies of the bucket-chain circuit to be delayed. If the bucket chain circuit is implemented in an integrated form, the filter capacitors will usually not be able to be integrated because of their large area requirement, but will be connected from the outside to the integrated circuit. The low-pass filter associated with the bucket chain input can also be replaced by an adjustable DC bias of the differential amplifier input F: \ , whereby the DC potential at the beginning of the bucket chain circuit is simulated.

The two stages m and n. At which the input signals for the differential amplifier DVL are picked up, are both even-numbered stages that are controlled by the same clock signal Φ \ , so that this is guaranteed. that the two stages are always in the same state. Of course, two odd-numbered stages can also be used to pick up the input signals of the differential amplifier DV1, which would then be connected to the clock signal Φ2 .

| e depending on how the control electrodes of the additional transistors serving as high-ohmic resistors are activated, the mean DC potential averaged over all time intervals or the DC potential averaged only over the collector connection clock periods of the transistors of the stages m, η can be generated at the inputs of the differential amplifier. The last-mentioned mean DC voltage potential is naturally higher than the DC voltage potential averaged over all times and is therefore, under certain circumstances, better suited for turning on the amplifier transistors of the differential amplifier DVi.

In the schematic diagram according to FIG. 1, the output signal of the differential amplifier DVI is now fed to the controllable constant current source RSQ , the output current pulse i _r of which is fed to the step n-1 galvanically directly preceding the step π. The output of the controllable constant current source is galvanically connected via the emitter-collector path of the additional transistor T to the stage n- 1 of the bucket chain circuit EK , the control connection of the additional transistor T _{5 being} controlled by the second clock signal Φ2, i.e. by the same clock signal that also controls the stage to which the current pulse from the constant current source is fed galvanically.

The current pulse i _r supplied by the controllable constant current source is, as a good approximation, a linear function of the rfcegelpotentials U _n . Furthermore, the current pulse i for a certain control potential U _r a is zero, this control potential U _r o being defined by the fact that it occurs when there is no differential signal at the inputs of the differential amplifier, ie when the two input potentials are equal to each other. Finally, the polarity of the current pulse / V is reversed when the control potential U _{n runs} through U _r0 , so that the following applies as a good approximation:

where go essentially corresponds to the steepness of the transistor T _r.

! n F i g. 2 is an example of execution! of the invention shown, which is constructed from p-channel insulating-layer field effect transistors, which are preferably designed as an integrated circuit. The transistors now correspond to the number of stages given above
7m 7 " _{m +} i, 7" _{m +} 2, T "- \, T _n and T _{n +} 1.

These transistors are linked to the associated capacitors Cin of the type described above and connected in series. The potential U _m at the collector connection of the transistor T _n is fed to one input E \ and the potential U _n at the collector connection of the transistor T _{n is} fed to the other "input Ei" of the difference in amplifier DVI. The difference nm does not necessarily have to be an even number it is odd, in the case of clocked transistors as high-value resistors Ren , care must be taken to ensure that they are controlled by the same clock signal as

ii the transistor to which the resistor /? <·, -1 is connected. This differential amplifier consists of two amplifier transistors and two transistors connected as load resistors, which are jointly connected to the operating voltage Un \ . The emitter

.'Ii connections of the two amplifier transistors are connected together via a constant current transistor to the circuit zero point, while the control connection of the constant current transistor is connected to the constant voltage Um . The structure of the

r> differential amplifier DVl is thus of the usual type.

Day with respect to the collector potential difference U _n - Un between the transistors T _n and T _{m not} inverted The output signal of the differential amplifier DVI is now used as a control potential (wire control electrode of the

κι operated in emitter circuit transistor T _r supplied, which is complementary to the other transistors of the overall circuit. that is, this transistor is an n-channel insulating gate field effect transistor. Its emitter is at the negative potential Up, while its

The collector via the additional transistor T ₅ , which in turn is a p-channel insulating layer field effect transistor, is connected to the collector of the transistor T "- \ of the bucket-chain circuit EK. The control electrode of the additional transistor T ₅ is connected to the capacitor Cc ₅

4 (i connected to the second clock signal Φ ₂ and is also connected to the potential Uc via the high-resistance Rc _5,

At the collector connection of the transistor T _n -] there is also another p-channel operating in the emitter circuit.

■ n insulating-layer field effect transistor Ti connected, the control terminal of which is connected on the one hand to the clock signal Φ2 via the capacitor Cck, to the circuit zero point via the capacitor C _m and to the DC potential Uc, k via the high-resistance Rck .

Thus, the transistors T _n - 1, 7 " _s and 7 * are always turned on or blocked at the same times. The DC potentials Ua and ί / ct are dimensioned so that the transistors T _s and Tk are full during the corresponding half-periods of the clock signals If necessary, the transistor T _r can be blocked directly by the control potential U _r during the corresponding half-periods. If this is guaranteed, the additional transistor T _{s can be} dispensed with.

The clock pulse amplitude effective at the control connection of the additional transistor Tk is thus

U _cG = U _c

• (l / _r = full clock amplitude)

The equal potential Ugic and the clock pulse amplitude Ucc can be selected in this way, for example durcii

suitable dimensioning of the capacities Cck and Cm that the current flowing through the transistor 7 * / * just compensates the current flowing in the transistor T _r in the case of U _r - ίΛο! so that the control current pulse i _r becomes zero.

The sign of the current pulse i _r can be reversed by swapping the differential amplifier output.

The circuit of the controllable constant current source shown in Fig. 2 remains completely equivalent in its function if the transistor T is used as a p-channel insulating layer field effect transistor instead of a η-channel and the additional transistor Ty instead of a p-channel as η- Channel insulating layer field effect transistor executes and the potential U _n at the respective emitters is interchanged with the reference potential and vice versa. At the same time, the transistor must also be controlled from the other clock signal, that is to say the clock signal Φ \

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be adjusted. The addition of transistor T, can be replaced by an n-channel insulating-gate field effect transistor with a corresponding change in the control.

Of course, the differential amplifier DVi can also be constructed differently; for example, the constant current transistor of the differential amplifier DVX can be replaced by a complementary, that is to say n-channel, transistor which, however, must then be between the two load transistors and the direct potential Ud \ . Furthermore, the two parallel inverters of the differential amplifier halves can also be replaced by two inverters (CMOS inverters) implemented using complementary insulating layer field effect transistor technology. On the other hand, however, all transistors of the differential amplifier can also be replaced by complementary ones and the potentials exchanged.

In Fig. 3 shows an exemplary embodiment of the invention with n-channel insulating layer field effect transistors which, with regard to the choice of transistors, is thus completely complementary to the exemplary embodiment according to FIG. In particular, the transistor T _r in FIG. 3 is therefore a p-channel insulating layer field effect transistor. Furthermore, at all those circuit points at which in FIG. 2 is the potential of the circuit zero point (with the exception of the connection of the capacitor C _n , at the circuit zero point), in Fig. 3 the potential U _{n is} connected, while at all points at which the potential Upi or U _n is in Fig. 2, in Fig. 3 shows the potential of the circuit zero point. The explanation of Fig. 2 with regard to the modification

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, 1 ti / gi! \. Iir \ t.iti.i! vjvaajjtt £ ■ "lit uiliapl (, Vlintull TT tist:

also for the embodiment according to FIG. 3, so referring to the relevant details set out above can be referenced.

In Fig. 4 finally shows the principle of repeated equal-level regeneration. For this purpose, the control current pulse / Van is again galvanically fed to the required level χ above level n-1. Both control current pulses originate from the same controllable constant current source RSQ, which must only be provided once. In this case, the constant current source can be connected to the corresponding stages of the bucket chain circuit EK via decoupling resistors R.

In addition 4 Ulalt drawings

Claims (9)

Patent claims: 1. Bucket chain circuit with a plurality of similar stages, each consisting of a transistor and a capacitor lying between its control terminal and its collector terminal and connected in series in such a way that the collector terminal of one is connected to the emitter terminal of the next transistor, the control terminals of the even-numbered Transistors are controlled by a first rectangular clock signal and the control connections of the odd-numbered transistors are controlled by a second square-wave and constant frequency clock signal, the effective pulses of which lie in the gaps between the effective pulses of the first clock signal, whereby according to Patent 23 17 252 the uinen input of a differential amplification: the The direct component of the potential at the collector of a transistor near the bucket chain input and the other input is supplied with the direct component of the potential at the collector connection of a transistor remote from the bucket chain input, which two transistors are controlled by the same clock signal, and one of the two output signals of the differential amplifier is capacitively fed to the collector connection of one of the transistors preceding the transistor remote from the bucket chain input, characterized in that instead of one of the two output signals of the differential amplifier (DK1) a current pulse proportional to it (i _r ) not the collector connection of one of the transistors preceding the transistor (T _n ) which precedes the bucket chain input. apacitive, special is supplied galvanically 2. Bucket chain circuit according to claim 1, characterized in that the current pulse (i _r ) is generated by a constant current source (RSQ) controlled as a function of the output signal (U _r ) of the differential amplifier (DKl). 3. Bucket chain circuit according to claim 1 or 2, characterized in that the collector connection of the bucket chain input-near transistor (T _n ) and the collector connection of the bucket chain input remote transistor (T _n ) each have a high-resistance resistor (Rc \) m \ i the corresponding input of the differential amplifier (DKl) and are each connected to the circuit zero point via a filter capacitor (Cc \) of such a capacity that the resistor and filter capacitor act as a low-pass filter for the signal frequencies of the bucket-chain circuit to be delayed. 4. bucket chain circuit according to one of claims 1 to 3, characterized in that the output signal of the differential amplifier (DKl) proportional current pulse (i _r ) to the collector of the bucket chain input remote transistor (T _n ) directly preceding transistor (7 " _n -i) galvanically is fed. 5. bucket chain circuit according to claim 4, characterized in that with respect to the collector potential difference (U _n - meanwhile the bucket chain input remote (T _n ) and the bucket chain input near (Tm) transistor non-inverting output of the differential amplifier (DKl) with the input of the controlled constant current source (RSQ) is connected that its output via the Emitter-collector path of an additional transistor (Ts) is connected to the collector terminal of the directly preceding transistor (T "_ |) and that the control terminal of the additional transistor from the clock signal signal (Φι) of this transistor is controlled 6. bucket chain circuit according to one of claims 1 to 5, characterized in that the current pulse (i _r ) is equal to zero when the two input signals of the differential amplifier (DKl) ι ο are equal to each other. 7. bucket chain circuit according to claims 5 and 6, characterized in that the collector terminal of the directly preceding transistor (7i_i) in addition to the current pulse one of one is additional constant current source generated, constant and so adjustable additional current pulse is supplied that when the same input signals of the differential amplifier (DKl) the total current pulse is zero 8. Bucket chain circuit according to claim 7, characterized in that the constant current source consists of a transistor (T _r ) of conduction type complementary to the other transistors of the overall circuit and the additional constant current source a transistor (Tk) of the same type of conduction as the other transistors of the overall circuit and that the transistor of the additional constant current source is controlled by the clock signal (Φ2) of the immediately preceding transistor ( T _n - 1) 9. bucket chain circuit according to one of claims 1 to 8, characterized in that as Transistors integrated insulating-layer field effect transistors of the enhancement or depletion type and, as capacitors, corresponding integrated serve grated capacities.