DE2324780B2 - METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - Google Patents
METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENTInfo
- Publication number
- DE2324780B2 DE2324780B2 DE19732324780 DE2324780A DE2324780B2 DE 2324780 B2 DE2324780 B2 DE 2324780B2 DE 19732324780 DE19732324780 DE 19732324780 DE 2324780 A DE2324780 A DE 2324780A DE 2324780 B2 DE2324780 B2 DE 2324780B2
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- Prior art keywords
- electrode
- mesa
- semiconductor
- epitaxial layer
- projection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 230000007704 transition Effects 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 4
- 241000251730 Chondrichthyes Species 0.000 claims 1
- 238000002679 ablation Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000007858 starting material Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- -1 B. GaAs or GaP Chemical compound 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Description
Die Erfindung betrifft ein Verfahren zum Herstellen eines Halbleiterbauelements, nach dem Oberbegriff des Anspruchs 1.The invention relates to a method for producing a semiconductor component according to the preamble of Claim 1.
Eine solche Technik ist bei der Erzeugung von Mesa-Epitaxialtransistoren bzw. Mesaepitaxialdioden gebräuchlich (vgl. beispielsweise »The Solid-State Journal« März 1961, Seiten 33 bis 37). Der Übergang zwischen ursprünglichen scheibenförmigen Halbleiterkristall und der epitaktischen Schicht kann als pn-Übergang ausgebildet sein, in den meisten Fällen ist es jedoch ein nn + - oder ein pp + -Übergang.One such technique is in the production of mesa epitaxial transistors or mesa epitaxial diodes common (see, for example, "The Solid-State Journal" March 1961, pages 33 to 37). The transition between the original disc-shaped semiconductor crystal and the epitaxial layer can be used as pn junction be formed, in most cases it is however, there is an nn + or a pp + transition.
Bei der vorliegenden Erfindung handelt es sich um die Herstellung von sog. Dünnschichtelementen, bei denen also der Halbleiterkörper in Form einer dünnen Schicht zwischen zwei — mehr oder weniger flächenhaft ausgebildeten — Elektroden angeordnet ist. In der Regel ist dabei ein sich parallel zu der Kontaktfläche dieser Elektroden erstreckender Übergang zwischen Zonen unterschiedlicher Leitfähigkeit vorhanden. Beabsichtigt ist vor allem der Aufbau als Lawinendiode, als Schottkydiode, als Gunndiode oder als Varaktordiode, wobei z. B. mehrere dieser jeweiligen Halbleiterbauelemente in einem Halbleiterchip integriert sein können.The present invention concerns the production of so-called thin-film elements, in which So the semiconductor body in the form of a thin layer between two - more or less flat formed - electrodes are arranged. As a rule, one is parallel to the contact surface these electrodes extending transition between zones of different conductivity is present. Intended is mainly the construction as an avalanche diode, as a Schottky diode, as a Gunn diode or as a varactor diode, where z. B. several of these respective semiconductor components can be integrated in a semiconductor chip.
Bei der Herstellung solcher einzelner oder mehrerer, in einem Chip enthaltener Bauelemente wird vielfach von den schwieriger als Silizium- oder Germanium zu behandelnden Verbindungshalbleitern, z. B. GaAs oder GaP, Gebrauch gemacht. Die für die Entstehung solcher Dünnschichtdioden erforderlichen Prozesse führen leicht zu Rissen und sonstigen Beschädigungen der spröden Halbleiterkristalle, welche die Funktion der Elemente in Frage stellen. Außerdem treten leicht Ungenauigkeiten der geometrischen Abmessungen auf. Es ist Aufgabe der Erfindung, hier eine Abhilfe zu schaffen.In the production of such individual or multiple components contained in a chip, multiple of the compound semiconductors, which are more difficult to treat than silicon or germanium, e.g. B. GaAs or GaP, made use of it. The processes required for the creation of such thin-film diodes lead easy to cracks and other damage to the brittle semiconductor crystals, which the function of Question elements. In addition, inaccuracies in the geometric dimensions easily occur. It is the object of the invention to provide a remedy here.
Hierzu geht die Erfindung von einem Verfahren der eingangs definierten Art aus und sieht bei diesem erfindungsgemäß die im kennzeichnenden Teil des Anspruchs 1 genannten Maßnahmen vor.For this purpose, the invention is based on a method of the type defined at the outset and is based on this according to the invention, the measures mentioned in the characterizing part of claim 1.
Bevorzugt ist die erste Elektrode als gleichrichtende Elektrode, insbesondere mit Schottkykontakt im Falle der Herstellung einer Lawinenlaufzeitdiode ausgebildet. Auf diesen speziellen Fall wird sich die weitere Beschreibung der Erfindung bevorzugt richten. Im Falle der Erzeugung einer Gunndiode werden beide Elektroden als ohmsche Kontakte ausgebildet. Schließlich kann entweder der durch die Epitaxie erzeugte Übergang ein pn-Übergang sein, oder mindestens an einer der Elektroden zu einem pn-Übergang führen. Die ersteThe first electrode is preferred as a rectifying electrode, in particular with a Schottky contact in the case the manufacture of an avalanche transit time diode. In this special case the further will be Description of the invention preferably direct. In the case of the production of a Gunn diode, both electrodes designed as ohmic contacts. Finally, either the transition created by the epitaxy can be a be pn junction, or at least lead to a pn junction on one of the electrodes. The first
Elektrode wird immer als selbsttragende Schicht hoher Festigkeit ausgebildet, so daß sie in der Lage ist, die bei jcr weiteren Bearbeitung auftretenden mechanischen Beanspruchungen abzufangen. Die schließlich erhaltene Dicke des Bauelements entspricht ersichtlich höchstens nur der Höhe der ursprünglichen Mesa an der epitakiiselv?n Schicht.Electrode is always formed as a self-supporting layer of high strength so that it is able to trap the other at j c r machining occurring mechanical stresses. The thickness of the component finally obtained apparently corresponds at most only to the height of the original mesa at the epitakiiselv? N layer.
Die Erfindung wird anhand der F i g. 1 bis 5 näher beschrieben. Dabei soll eine Lawinenlaufz.eiidiode mit Sehottkykontakt hergestellt werden.The invention is illustrated by means of FIGS. 1 to 5 closer described. An avalanche detector should be included Sehottky contact can be established.
Ausgangspunkt bildet eine etwa 100 — 400 (im Stärke aufweisende η ' leitende Scheibe 1 aus Galliumarsenid (z. B. mit einer Dotierungskonzentration von mehr als \ΐ)'Λ cm l). an deren einen Oberflächensehe eine epitaktische Schicht 2 aus dem gleichen Material mit einer Dicke von etwa 2 μΐη abgeschieden wird. Die Dotierung der epitaktischen Schicht 2 wird auf etwa 2 · 10"' cm- ! eingestellt und besteht beispielsweise aus Zinn (Sn). Auf der epitaktischen Schicht 2 wird dann eine Fotolackmaske 3 aufgebracht, welche einen oder mehrere inselartige Bereiche der freien Oberfläche der epitaktischen Schicht 2 abdeckt. Beispielsweise sind diese insclartig ausgebildeten Fotolackmasken 3 nach einem ΙΟΟΟ-μιη-Raster angeordnet und weisen jeweils etwaö'iO um Durchmesser auf.The starting point is formed by an approximately 100-400 (η 'conductive disk 1 made of gallium arsenide with a thickness of η' (e.g. with a doping concentration of more than \ ΐ) ' Λ cm l ). on one surface of which an epitaxial layer 2 made of the same material with a thickness of about 2 μm is deposited. The doping of the epitaxial layer 2 is set to about 2 · 10 "cm- ! And consists, for example, of tin (Sn). A photoresist mask 3 is then applied to the epitaxial layer 2, which has one or more island-like areas of the free surface of the epitaxial Covering layer 2. For example, these inscl-like photoresist masks 3 are arranged according to a ΙΟΟΟ-μm grid and each have a diameter of approximately 10 μm.
Als Fotolack ist beispielsweise die Type AZ 1350 geeignet.Type AZ 1350 is an example of the photoresist suitable.
Mit Hilfe dieser Photolackiitzmaske 3 und eines geeigneten Är/mittels, z. B. wird nun der Halbleiterkörper an der mit der epitaktischen Schicht 2 versehenen Seite solange einer Äizbehandlung unterzogen, bis mindestens ein mesaartiger Vorsprung 4 entstanden ist, dessen Hohe größer als die Dicke der epitaktischen Schicht 2 gewählt wird. Infolgedessen erhält der mesaartige Vorsprung 4 an seiner Grundfläche einen Teil des ursprünglichen η '-Materials, das später die Entstehung des ohmschcn Kontaktes mit der zweiten Elektrode begünstigt (Fig.!).With the help of this photoresist mask 3 and a suitable arm / means, e.g. B. is now the semiconductor body on the side provided with the epitaxial layer 2 subjected to an etching treatment until at least one mesa-like projection 4 has arisen, the height of which is greater than the thickness of the epitaxial Layer 2 is chosen. As a result, the mesa-like projection 4 is given a on its base Part of the original η 'material which later became the Creation of the ohmic contact with the second electrode promotes (Fig.!).
Werden mehrere Elemente nebeneinander aus der gleichen Halbleiterscheibe erzeugt, so wird man mehrere mesaartige Vorsprünge 4 an derselben Seite der Halbleiterscheibe, also an der Oberfläche der epitakiischen Schicht 2 erzeugen, indem gleichzeitig mehrere insbesondere rasterartig angeordnete Photolackät/.masken 3 vorgesehen werden.If several elements are produced next to one another from the same semiconductor wafer, one becomes several mesa-like projections 4 on the same side of the semiconductor wafer, that is to say on the surface of the epitakiic layer 2 generate by simultaneously several photoresist / .masks, in particular arranged in a grid-like manner 3 are provided.
Nach erfolgtem Ätzvorgang wird die Photolackmaske Ϊ entfern! und die Anordnung zwecks Abrunden der Kaulen kin/, iiberäi/.i. Dann wird .lie mit dem mesaartigen Vorsprung 4 versehene Seite der Anordnung mit einer Schicht 5 aus dem Metall der ersten Elektrode bedeckt. Im Beispiclsfalle besteht diese aus Cr und soll einen Sehottkykontakt mi: dem n-leitenden Material an der Kuppe des mesaartigen Vorsprungs 4 bewirken. Falls erforderlich, wird zur Erzielung eines gleichrichtenden Kontaktes zwischen der ersten Elek trode 5 und dem Halbleiter, z. B. bei Herstellung eines pn-Obergangs, eine thermische Behandlung vorgesehen. Im Falle der Verwendung einer aufgedampften oder galvanisch erzeugten Cr-Schicht S wird diese zweckmäßig durch eine u csentlich dickere Ag-Schieht 6 verstärkt. Hs empfiehlt ■ ic!· die Gesamtstärke der ersten Plrktrode 5, 6 auf einen Wert von 20-300 um einzustellen. Dann zeichnet sich die Mesastruktur dei darunterliegenden Halbleiteroberfläche noch durch die Elektrode hindurch ab. Gegebenenfalls wird die freie Oberfläche der ersten Elektrode noch mit einer den späteren Einbau des Elements erleichternden Lot- oder sonstigen Bindeschicht, /. B. aus einer AuGe-Legierung bedeckt.After the etching process, the photoresist mask Ϊ is removed! and the arrangement for the purpose of rounding off the Kaulen kin /, iiberäi / .i. Then .lie with the Mesa-like projection 4 provided side of the arrangement with a layer 5 of the metal of the first Electrode covered. In the example it consists of Cr and is intended to have a Sehottky contact mi: the n-conductive material at the tip of the mesa-like projection 4 cause. If necessary, to achieve a rectifying contact between the first Elek trode 5 and the semiconductor, e.g. B. when producing a pn transition, a thermal treatment is provided. In the case of using a vapor-deposited or electroplated Cr layer S, this is expediently through a considerably thicker Ag layer 6 reinforced. Hs recommends ■ ic! · The total thickness of the first electrode 5, 6 to a value of 20-300 µm to adjust. Then the mesa structure emerges underlying semiconductor surface through the electrode. If necessary, the free Surface of the first electrode still with a soldering or soldering to facilitate the later installation of the element other binding layer, /. B. from an AuGe alloy covered.
Fs entspricht nun der Erfindung, wenn — wie aus Fig. 3 ersichtlich - der GaAs-Körper 1 an der der ersten Elektrode 5, 6 gegenüberliegenden Seite gleichförmig soweit abgetragen wird, bis die liefsien Stellen der ersten Elektrode in Form eines den mesaartigen Vorsprungs an seiner Basis rings umgebenden Metallringes an der Abtragungsseite sichtbar sind. Der verbliebene Halbleiterrest besteht dann nur noch aus dem ehemaligen mesaartigen Vorsprung und besteht an seiner Basis aus dem Rest der ehemaligen η ' Zone und an seiner Deckfläche aus dem Rest der ehemaligen epitaktischen Schicht. Hat man mehrere solche mesaartigen Vorsprünge 4 an der Halbleiteroberfläche nebeneinander erzeugt, so erhält man eine entsprechende Viel/ah! solcher von der ersten Elektrode umgebene (falbleiterreste, falls die Elektrode 5, 6 gleichförmig über die gesamte mit den mesaartigen Vorsprüngen versehene Oberflächenseite des GaAs-Körpers aufgebracht wurde. Dann wird jeder dieser Halbleitcrinseln zu je einem Halbleiterelement weiterverarbeitet. Schließlich wird nach Absolvierung aller noch anstehenden Prozesse die den Zusammenhalt noch gewährleistende erste Elektrode 5, 6 zwischen den einzelnen Elementen, z. B. durch Zersägen oder durch Atzen, aufgetrennt.Fs now corresponds to the invention if - as out 3 shows the GaAs body 1 on the side opposite the first electrode 5, 6 is removed uniformly until the left places of the first electrode are in the form of a den Mesa-like projection on its base all around the metal ring on the removal side are visible. The remaining semiconductor residue then consists only of the former mesa-like protrusion and consists at its base of the rest of the former η 'zone and at its top surface of the rest of the former epitaxial layer. There are several such mesa-like projections 4 on the semiconductor surface generated side by side, you get a corresponding amount / ah! such from the first electrode Surrounded (trap residues, if the electrode 5, 6 uniformly over the entire with the mesa-like Surface side of the GaAs body provided with protrusions was applied. Then everyone becomes this Semiconductor islands are further processed into one semiconductor element each. After all, after all pending processes have been completed, cohesion will still be achieved ensuring first electrode 5, 6 between the individual elements, for. B. by sawing or by Etching, separated.
Falls die Dicke des η · -leitenden Restes 1 des ehemaligen Kristalls 1 noch weiter reduziert werden soll, kann man die Grundfläche der erhaltenen Inseln noch der Einwirkung eines insbesondere die erste Elektrode nicht angreifenden Atzmittels aussetzen. Aus F i g. 3 ist bereits die von einem solchen Zwischenät/. prozeß herrührende reduzierte Dicke des dem ehemaligen mesaartigen Vorsprungs entsprechenden Halbleiterrest berücksichtigt.If the thickness of the η · -conductive residue 1 of the former crystal 1 can be further reduced If you want, you can still see the base of the preserved islands under the action of one in particular the first Do not expose the electrode to corrosive etching agents. From Fig. 3 is already that of such an intermediate /. Process resulting reduced thickness of the former mesa-like projection corresponding semiconductor remainder considered.
Es entspricht nun der Erfindung, wenn die freigelegte Grundfläche des noch vorhandenen Hnlbleiterrestes 4 mit einer das dort noch vorhandene η ■ -leitende Material sperrfrei kontaktierenden flächenhafi-.-n Elek trode 7 versehen wird, die zugleich als Ätzmaske geeignet ist. Falls die Elektrode 7 nicht ätzfest ist, wird sie zweckmäßig mit einer Ätzmaske abgedeckt, die z.udem überall etwas über den Rand der Elektrode 7 hinausragt, um eine Unterätz.img der Elektrode 7 /u vermeiden. Aber auch wenn die Elektrode 7 ätzfest ist, wird sie zweckmäßig aus dem gleichen Grund von einer an die Elektrode 7 ringsum dicht anschließenden ringförmigen Photolackschicht umgeben, so daß bei dem fertigen Bauelement die Elektrode nicht seitlich über den Halbleiterkörper des Elements hinausragt.It corresponds to the invention if the exposed base area of the remaining semiconductor remainder 4 is provided with an electrode 7 which contacts the remaining η ■ -conductive material without blocking and which is also suitable as an etching mask. If the electrode 7 is not etch-resistant, it is expediently covered with an etching mask, which also protrudes slightly over the edge of the electrode 7 in order to avoid under-etching of the electrode 7 / u . But even if the electrode 7 is etch-proof, it is expediently surrounded for the same reason by an annular photoresist layer closely adjoining the electrode 7, so that in the finished component the electrode does not protrude laterally beyond the semiconductor body of the element.
Zur Herstellung der die zweite Elektrode des herzustellenden Elements bildenden begrenzten Metallschicht kann man das Elektrodenmetall beispielsweise ganzflächig aufdampfen und dann mit Hilfe einer Photolackätzlechnik das überschüssige Flekirodenme tall an den unerwünschten Stellen wieder entfernen. Man kann es aber auch mit Hilfe einer entsprechenden Bedampftingsmaske im vornherein selektiv aufdampfen oder galvanisch aufbringen.For producing the limited metal layer forming the second electrode of the element to be produced you can vaporize the electrode metal, for example, over the entire area and then with the help of a Photo lacquer etching technique the excess flekirodenme tall at the unwanted places. But you can also do it with the help of an appropriate Vaporize mask selectively in advance or apply galvanically.
Zu bemerken ist noch, daß gegebenenfalls die Elektroden 5, fi bzw. 7 um ihre Funktionen erfüllen zu können, eingetempert werden müssen. Weiterhin ist festzustellen, daß die /.weite Flektrode 7 im Beispielsfalle immer nur den η ' leitenden Rest an der Grundfläche des noch vorhandenen Halbleiterrestes 4 kontaktiert. Die ohmsehe Elektrode 7 kann gegebenenfalls in ähnlicher Weise wie die Elektrode 5, 6 aus mehreren Schichten bestehen. Beispielsweise kann an das GaAsIt should also be noted that, if necessary, the electrodes 5, fi or 7 to fulfill their functions can, must be tempered. Furthermore, it should be noted that the /.wide Flektrode 7 in the example always only the η 'conductive remainder on the base of the remaining semiconductor residue 4 contacted. The ohmic electrode 7 can optionally in in a similar way to the electrode 5, 6 consist of several layers. For example, the GaAs
unmittelbar eine 12%ige Au-Ge-Schicht grenzen, die von einer Cr-Ni-Schicht und diese durch eine Au-Schicht abgedeckt ist. Ebenso kann auch die erste Elektrode 5, 6 noch weitere Schichten, z. B. eine den späteren Einbau des Elements erleichternden Schicht an der freien Oberfläche der Ag-Schicht 6 versehen werden. Der Durchmesser der zweiten Elektrode 7 kann beispielsweise 50-300 μηι betragen.immediately border a 12% Au-Ge layer, which is bordered by a Cr-Ni layer and this by an Au layer is covered. Likewise, the first electrode 5, 6 can also have further layers, e.g. B. a den Later installation of the element facilitating layer provided on the free surface of the Ag layer 6 will. The diameter of the second electrode 7 can be, for example, 50-300 μm.
Falls mehrere Elemente nebeneinander erzeugt werden, wird jedes Element seine eigene zweite Elektrode 7 erhalten, die von der allen Elementen gemeinsamen ersten Elektrode 5, 6 inselartig abgesondert ist.If several elements are created next to each other, each element becomes its own second Electrode 7, separated from the first electrode 5, 6, which is common to all elements, like an island is.
Der folgende Schritt des erfindungsgemäßen Verfahrens ist wiederum ein Ätzvorgang, mit dessen Hilfe der bisher bestehende Kurzschluß des n + n-Übergangs in dem noch verbliebenen Halbleiterrestkörper 4 beseitigt wird. Dabei wird unter Verwendung der Elektrode 7 als Ätzmaske (oder einer gesonderten Ätzmaske, ggf. auch vor dem Aufbringen der Elektrode 7) ringförmig Halbleitermaterial um die Elektrode 7 (bzw. die ihr entsprechende Ätzmaske) abgeätzt, bis dieser Kurzschluß durch die erste Elektrode 5, 6 beseitigt ist. Vorwiegend wird man noch darüber hinausgehend weiteres Halbleitermaterial abtragen, bis nur noch ein Kegelstumpf 9 verblieben ist, der an seiner Deckfläche von der ersten Elektrode 5,6 und an seiner Grundfläche von der ohmschen Elektrode 7 bedeckt und kontaktiert wird. Parallel zu den beiden Elektroden erstreckt sich der noch vorhandene Teil des ursprünglichen n+n-Übcrgangs quer durch den Kegelstumpf 9 (F i g. 4).The following step of the method according to the invention is again an etching process, with the aid of which the previously existing short circuit of the n + n junction in the remaining semiconductor body 4 is eliminated. In this case, using the electrode 7 as an etching mask (or a separate etching mask, possibly also before applying the electrode 7), ring-shaped semiconductor material around the electrode 7 (or the corresponding etching mask) is etched away until this short circuit through the first electrode 5, 6 is eliminated. In the main, further semiconductor material will be removed until only a truncated cone 9 remains, which is covered and contacted on its top surface by the first electrode 5, 6 and on its base surface by the ohmic electrode 7. The part of the original n + n transition that is still present extends parallel to the two electrodes transversely through the truncated cone 9 (FIG. 4).
Falls mehrere Elemente nebeneinander aus der Halbleiterscheibe hergestellt wurden, ist es nun an der Zeit, die erste Elektrode zwischen den einzelnen Elementen aufzutrennen, um diese selbständig zu machen. Dies ist durch die gestrichelte Linie in Fig.4 dargestellt. Schließlich wird das Element in ein Gehäuse in der üblichen Weise eingebaut. Dabei wird die Tatsache, daß die Elektrode 5, 6 robust ausgebildet werden kann, ausgenutzt, wenn man, wie aus Fig. 4 ersichtlich, diese Elektrode durch Thermokompression mittels eines nur mit dieser Elektrode in Berührung kommenden Stempels 11 (Fig. 5) mit einer für die Montage des Elements vorgesehenen metallischen Unterlage 12 verbindet. Gegebenenfalls kann auch eine andere Technik, z. B. Ultraschallötung oder -schweißung angewendet werden. Das eingebaute Element wird schließlich nochmals kurz überätzt und dann mit einem die Elektrode 7 kontaktierenden Anschluß, ζ. Β im Deckel des Gehäuses beim Verschluß, in bleibenden Kontakt gebracht.If several elements have been produced from the semiconductor wafer next to one another, it is now the turn of Time to separate the first electrode between the individual elements in order to independently close them do. This is indicated by the dashed line in Fig.4 shown. Finally, the element is installed in a housing in the usual manner. The The fact that the electrode 5, 6 can be made robust, is utilized when, as shown in FIG. 4 can be seen, this electrode by thermocompression by means of one only in contact with this electrode Coming stamp 11 (Fig. 5) with a provided for mounting the element metallic Pad 12 connects. Another technique, e.g. B. Ultrasonic soldering or welding be applied. The built-in element is then briefly overetched again and then with a terminal contacting the electrode 7, ζ. Β in the cover of the housing at the closure, in permanent Brought in contact.
Die Herstellung einer Gunndiode beispielsweise gestaltet sich ähnlich. Lediglich die Elektrode 5, 6 isi ebenfalls wie die zweite Elektrode 7 als ohmschei Kontakt ausgebildet. Bei der Herstellung einer Varak tordiode wird man andererseits dafür sorgen, daß die erste Elektrode mit dem Material der epitaktischer Schicht 2 einen pn-Kontakt bildet. Schließlich ist es aucl möglich, daß der Übergang zwischen der epitaktischer Schicht 2 und dem Ausgangskristall 1 ein pn-Überganj ist.The production of a Gunn diode, for example, is similar. Only the electrodes 5, 6 are also designed as an ohmic contact like the second electrode 7. When making a varak gate diode will on the other hand ensure that the first electrode with the material of the epitaxial Layer 2 forms a pn contact. Finally, it is also possible that the transition between the epitaxial Layer 2 and the starting crystal 1 is a pn transition.
Hierzu 1 Blatt Zeichnungen1 sheet of drawings
Claims (7)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2324780A DE2324780C3 (en) | 1973-05-16 | 1973-05-16 | Method for manufacturing a semiconductor component |
US469114A US3903592A (en) | 1973-05-16 | 1974-05-13 | Process for the production of a thin layer mesa type semiconductor device |
JP49053949A JPS5019370A (en) | 1973-05-16 | 1974-05-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE2324780A DE2324780C3 (en) | 1973-05-16 | 1973-05-16 | Method for manufacturing a semiconductor component |
Publications (3)
Publication Number | Publication Date |
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DE2324780A1 DE2324780A1 (en) | 1974-12-12 |
DE2324780B2 true DE2324780B2 (en) | 1977-12-01 |
DE2324780C3 DE2324780C3 (en) | 1978-07-27 |
Family
ID=5881127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE2324780A Expired DE2324780C3 (en) | 1973-05-16 | 1973-05-16 | Method for manufacturing a semiconductor component |
Country Status (3)
Country | Link |
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US (1) | US3903592A (en) |
JP (1) | JPS5019370A (en) |
DE (1) | DE2324780C3 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0043654A2 (en) * | 1980-07-01 | 1982-01-13 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Improvement in or relating to semiconductor diodes and their fabrication |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52116185A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Mesa-type semiconductor laser |
US4160992A (en) * | 1977-09-14 | 1979-07-10 | Raytheon Company | Plural semiconductor devices mounted between plural heat sinks |
US4373255A (en) * | 1979-06-19 | 1983-02-15 | The United States Of America As Represented By The Secretary Of The Air Force | Method of making oxide passivated mesa epitaxial diodes with integral plated heat sink |
US4740477A (en) * | 1985-10-04 | 1988-04-26 | General Instrument Corporation | Method for fabricating a rectifying P-N junction having improved breakdown voltage characteristics |
US5166769A (en) * | 1988-07-18 | 1992-11-24 | General Instrument Corporation | Passitvated mesa semiconductor and method for making same |
US4980315A (en) * | 1988-07-18 | 1990-12-25 | General Instrument Corporation | Method of making a passivated P-N junction in mesa semiconductor structure |
US6348739B1 (en) * | 1999-04-28 | 2002-02-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
US6686616B1 (en) * | 2000-05-10 | 2004-02-03 | Cree, Inc. | Silicon carbide metal-semiconductor field effect transistors |
US6906350B2 (en) | 2001-10-24 | 2005-06-14 | Cree, Inc. | Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure |
US6960490B2 (en) * | 2002-03-14 | 2005-11-01 | Epitactix Pty Ltd. | Method and resulting structure for manufacturing semiconductor substrates |
AUPS112202A0 (en) * | 2002-03-14 | 2002-04-18 | Commonwealth Scientific And Industrial Research Organisation | Semiconductor manufacture |
US6956239B2 (en) * | 2002-11-26 | 2005-10-18 | Cree, Inc. | Transistors having buried p-type layers beneath the source region |
US7238224B2 (en) * | 2004-10-29 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | Fluid-gas separator |
US20060091606A1 (en) * | 2004-10-28 | 2006-05-04 | Gary Paugh | Magnetic building game |
US7348612B2 (en) * | 2004-10-29 | 2008-03-25 | Cree, Inc. | Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same |
US7265399B2 (en) * | 2004-10-29 | 2007-09-04 | Cree, Inc. | Asymetric layout structures for transistors and methods of fabricating the same |
US7326962B2 (en) * | 2004-12-15 | 2008-02-05 | Cree, Inc. | Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same |
US8203185B2 (en) * | 2005-06-21 | 2012-06-19 | Cree, Inc. | Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods |
US7402844B2 (en) * | 2005-11-29 | 2008-07-22 | Cree, Inc. | Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods |
US7646043B2 (en) * | 2006-09-28 | 2010-01-12 | Cree, Inc. | Transistors having buried p-type layers coupled to the gate |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US3519506A (en) * | 1963-11-26 | 1970-07-07 | Int Rectifier Corp | High voltage semiconductor device |
US3765970A (en) * | 1971-06-24 | 1973-10-16 | Rca Corp | Method of making beam leads for semiconductor devices |
US3689993A (en) * | 1971-07-26 | 1972-09-12 | Texas Instruments Inc | Fabrication of semiconductor devices having low thermal inpedance bonds to heat sinks |
US3761783A (en) * | 1972-02-02 | 1973-09-25 | Sperry Rand Corp | Duel-mesa ring-shaped high frequency diode |
-
1973
- 1973-05-16 DE DE2324780A patent/DE2324780C3/en not_active Expired
-
1974
- 1974-05-13 US US469114A patent/US3903592A/en not_active Expired - Lifetime
- 1974-05-16 JP JP49053949A patent/JPS5019370A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0043654A2 (en) * | 1980-07-01 | 1982-01-13 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Improvement in or relating to semiconductor diodes and their fabrication |
EP0043654A3 (en) * | 1980-07-01 | 1982-09-22 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Improvement in or relating to semiconductor diodes and their fabrication |
Also Published As
Publication number | Publication date |
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DE2324780A1 (en) | 1974-12-12 |
DE2324780C3 (en) | 1978-07-27 |
JPS5019370A (en) | 1975-02-28 |
US3903592A (en) | 1975-09-09 |
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