DE2323661B2 - Digital arithmetic unit for determining the ignition angle in piston internal combustion engines - Google Patents

Description

The !! turn refers to a digital arithmetic unit for determining the ignition angle in piston-type internal combustion engines from the ratio of two pulse numbers.

The ignition angle η can be determined by comparing the times between the sampling times of two marks that revolve at the speed of the crankshaft of the internal combustion engine and enclosing a comparison angle // or between the ignition time and the scanning line point of the second mark //; or I _x can be determined. The cell spans I ₁ or / "are expediently measured by a number of pulses in a clock pulse sequence of the constant frequency / ₀ and are then available as pulse numbers z _v or 2 _a . The ignition angle u then corresponds to

and the angle of comparison) ji results in

where in is the angular velocity of the crankshaft. From the relationship

a I _x ' in _ I ₁ ' Jq -1

I ^s tß ' <" ¹ P ' Jq ^z p

can increase the ignition angle

can be calculated. The last equation shows that a computer is used to determine the ignition angle a division of two variable numbers of impulses and a multiplication of the quotient by a constant number.

A common digital dividing method consists in adding up the divisor until it becomes is equal to or greater than the dividend. The number of addition steps performed is then that Division result. In the present case, this result is still with a constant factor multiply.

The invention was based on the object of a dividing circuit for two variable pulse numbers specify, for which the result is multiplied by a constant factor at the same time and for which a dissolution subjects arising from this peculiarity is balanced.

This task is carried out with a digital arithmetic unit for determining the ignition angle in piston internal combustion machines from the ratio of two pulse numbers, with a numerator for the divisor, a first adder and summing memory connected in parallel to this. a counter for dividends, a

<l

In comparison to the comparison of the vote storage value and dividend counter value, a control circuit with additive pulse output and a result counter according to the invention is solved by adding a countdown counter with an additional factor of the pulse rate corresponding to the counter for the divisor and a / further adder and summation memory is done in parallel with the divider counter and overriding pulses from the / wide adder are fed to the lowest valence HiI of the first adder.

Using the inclusion of Untcrs ^<v lzer -. / Iiblers in the Mehrl'aehaddilion the divisor is a resolution error that would otherwise occur by the Unlerscl / unp the divisor avoided.

The result counter is useful around a one Proportion of the additional factor corresponding number of bits of least significant value expanded.

A costly optimization of the Reehen-WCrkh I am aware of the invention in that the divisor counter is reduced by as many I3ils higher "minorities as the scaler counter bits contains and the omitted bits of the divisor selector assigned part of the first adder and Mimmenspeichers replaced by a simple counter is. The transfer output of the remaining bits of the divisor counter is expedient in this case Part of the first adder to the bit with two-tier value of the omitted part of the first adder and summation memory replacing counter connected. The least significant bit the result counter can be omitted.

The most significant bit of the divisor counter and the most significant bit of the dividend counter is connected to the two inputs of a NOR gate, the output of which has blocking inputs of gate soundings for the dividend and divisor counting pulses.

The second low value bit of the counter replacing the missing part of the first adder and summation memory is controlled via the output of a NAND gate, one input of which is connected to the output of the part of the first adder assigned to the bits of the divisor counter that is still present and the other input to the Addierimpulsausgang the control circuit is connected ve ^r.

In a further development of the invention, the result counter is a presettable forward / backward counter. by choosing the angle of comparison of 32 corresponding to the additional factor Crank angle to an angle value of 20 crank angle μesct / t prior to the start of the arithmetic operation.

The invention is explained in more detail by six figures on Hund.

Fig.! Mc! ^{1 represents} a dividing cup according to the principle of multiple addition of the divisor:

fig 2 is a block diagram of a divider formwork according to the invention.

F ig 3 is a far '^"r e representation of a Dividicrschaltung according to the invention;

F i g. 4 shows an optimized dividing circuit according to the invention; in

Fig. 5 is the location of the measurement area and the Vcrgicichswinkcls // with regard to the above dead center shown:

Fig ft / eigt a forward-backward counter «ils I -.Result is counter.

In Fig. I two gate noises Tu and T // can be seen, the control input of which the time periods t and I ₁₁ limiting impulses are supplied, cattle, other inputs of the gate noises are not on one

The pulse generator shown is connected, which emits a pulse train of constant frequency / _ö , the output of the gate circuit Tn is connected to the counting input of a counter Zm and the output of the gate sounding T / I is connected to the counting input of a counter Z \\ .

ίο The counter Z // takes the divisor nuf, the counter Zn is intended for dividends. Inputs / II, / 12, A4, / 18 of a 4-bit full adder / I are connected to parallel outputs of the counter Z //. The sum outputs .VI, Sl. S4. SH of the adder are connected to preparation inputs of four summcnspe.ehcr flip-flops FF1, FF2, FF4 and FFS . Outputs of the flip-flops FFI ... FF8 are connected to / wide inputs ßl, Bl, ß4, / i8 of the adder Λ . In addition, the outputs of the flip-flops are connected to just as many inputs of a comparator V , the other inputs of which are occupied by parallel bit outputs of the counter Zu. Set inputs of the memory CR flip-flops FFI. . FF8 are connected in parallel to a line which emanates from a control circuit ST. A start pulse at the beginning of the division is entered into the control circuit .ST via an input; the control circuit .VT is connected to the generator of the pulse train frequencies / j _Q via a second input. A

third input of the control circuit .ST is connected to the output of the comparator V , which emits a pulse as soon as the outputs of the memory flip-flops are equal to or greater than the outputs of the counter Zn. via the control circuit .VT is also a result Counter Zc connected to the Frequcnzgeneraior for the clock pulse frequency / _Ö . A reset pulse can be fed to the reset inputs of all counters or flip-flops via a line.

The circuit according to FIG. 1, before the start of the division operation to be carried out, a reset pulse is supplied via the reset line, which brings the entire circuit into a defined starting position. All counters are set to zero, and the sum outputs of the adder and the outputs of the memory flip-flops also carry no signal. The result counter Ze is also set to zero. Thereupon, the counters Zu and Z _t i the times t, and / _{/ (} are counted in corresponding pulse _{numbers cn r 2} and z _p . On a start pulse at the corresponding input of the control circuit .VT this releases the first clock pulse from the clock pulse sequence c / « Tiiktimpuls gets into the result counter Zc and to the set inputs of the memory flip-flops. As a result, the signal from the Z.ihler / t which is present at the preparation inputs via the adder outputs is available at the outputs of the memory flip-flops jcl / t. .; an At the same time, these signals are applied to the corresponding inputs of the comparison and to the addition inputs Bi, Bl, B4, BH

(> o Summcnausgangscn of the adder .Vl, Sl.!> 4. 58 and Jamil also at the preparation inputs of the memory flip-flops FFI. FF2, FF4, FF8 is now the sum of the contents of the counter Z / l added once the next Clock pulse repeats the game.

which is continued until the sum of the .iiifaddierien divisor number is equal to or greater than the number di-r dividends. Then the comparator V outputs an Ause.int'simpnls to the control circuit .VT, which

then no more clock pulses can get to the Speichercr flip-flops and the result counter Ze . The result of the division calculation is recorded in this numerator. Using transfer inputs and outputs, 3e dividing units can be put together as desired. The dividing unit for the ignition angle measuring device was designed for 12 counter bits, that is, the pulse counters z _r and z _(l can be a maximum of 4096. The frequency f _Q der Clock pulse sequence was placed so that a resolution of 16 pulses per degree crank angle is not undercut even at the highest speed.

Bs can be seen that if the counters are the same, the counters Zu and ZjS are the result of division "I". The dividing mechanism shown in Fig. 1 must therefore still have a device that allows the quotient to be multiplied by the constant number corresponding to the comparison angle (l . Instead of multiplying the quotient by the factor //, the divisor can also be expressed by [I , / i is, as already mentioned, a constant number, so that the division can be carried out by a divider counter before the counter Z (I for the divisor.

However, this measure makes the resolution of the result considerably worse. The resolution

now only corresponds to "f.

A circuit which reduces this resolution error is shown in simplified form in FIG. The gates Tn and T>'> can be seen again, via which the clock pulse frequencies // y are fed once to the counter / «and, via the scaler counter, to the counter Zf. To the parallel bit outputs of the counter to coasters, however, adder Au and storage flip-flops are connected SPFF whose operation corresponds to that of FIG. I. An output for the input pulse from the adder Au is connected to a bit input of the adder A assigned to the divisor counter Z / i . The memory outputs of the adder A allocated memory are compared as in the sound transmission shown in FIG. I, on the Verglcichcr V with the Auslangen the dividend payer Zn.

The following consideration relates to the choice of a favorable value for the comparison angle / I. In order to be able to build the coaster counter Zu, through which / f is taken into account in the calculation, as simply as possible, a dual number, for example 2, 4, 8, 16, 32, 64, 128 etc., is used for / (.

In the case of an internal combustion engine, experience has shown that the entire ignition angle range does not exceed 60 crank angles. Taking into account the fact that the measuring method has the smallest error at a = //, it makes sense to place the first mark for the comparison angle in the middle of the range of the ignition angle, assuming that the ignition angle η with large probability wedge fluctuates mainly around a mean value. For these considerations, // = 32 '' crank angle was chosen for the comparison angle.

If the time dependency of the angular velocity m c | tiadratic, then the selected position of the comparison angle has a particularly favorable effect with regard to the entire ignition angle variation range. With a linear behavior of m, the error is always zero,

The first task of the coaster counter Zu is to achieve the multiplication of the quotient by your constant factor / I. If the dividing mechanism according to F ί g. 2, a resolution of the result of l ^c Kurhdwinkel is obtained. Here is an example. Let the number of pulses corresponding to the ignition angle be z “= 301I. The number of pulses corresponding to the comparison angle is Z ₁₁ = 3010. The number of pulses for the comparison angle is divided by 32 in the divider counter Zu, the result is

■ i? I °. = 94.0625.

If calculated using conventional methods, this would give a value for the crank angle of

η = 32.010653 "crank angle

result. In the result counter of the dividing mechanism on the other hand a value for the crank angle

u = 33 "crank angle

appear. The error that occurs is thus approximately Γ Kurbclwinkcl. This error can be reduced if the result is resolved higher, d. That is, the result is with a resolution factor G to multiply. The equation for the crank angle then reads

It is advisable to choose a factor G = 4 because 4 represents a dual number. Otherwise, the factor o is treated in the same way as the factor //, so instead of multiplying the quotient by a factor, a division or reduction of the divisor by the factor is carried out in the dividing unit. To simplify the further explanation, door / i · G = /; ' written. // '= 32 · 4 = 128. The divider counter for the factor / i' must therefore divide by 128. Now two 4-bit binary counters connected in series have a reduction of 256: I. If this economical combination is to be used, the result counter Ze would have to be extended by 3 bits, because the values 0.5 crank angle, 0.25 crank angle and 0.125 curb angles are added. The resolution error would then be 0.125 crank angle. In contrast, only a resolution of 1/4 'crank angle is necessary for determining the ignition angle, i.e. a reduction of 128. As can be seen from the explanations relating to FIG inexpensive combination of two 4-Bil binary Zählcrn is chosen for the Untcrsetzcr-Zählcr to.

In Fig. 3 shows a dividing mechanism according to FIG. 2 in greater detail, in particular the counters used are labeled with number dials assigned to the individual bits. It can be seen that the ijnlcrsclzcr-Zählcr is composed to two 4-bit Zählcrn, whose bit corresponds to the most significant number 128th The divisor counter Z / i consists of three 4-frame counters connected in series. The number 2048 is assigned to its highest significant bit. The dividend counter Zu also has the same structure. The result counter Ze consists of two consecutive 4-bit counters with an upstream additional bit for the lowest value, the 1/8 "crank angle

is equivalent to. Otherwise, the interconnection of the individual components of the dividing mechanism according to FIG. 3 corresponds to FIGS. 2 and ⁷ . I will explain connections, for a better understanding;) I will now use the equation for the crank angle

If the period of time / ,, or, j _{/ (is used} , the corresponding pulse numbers z _v or z ,, enter the dividend or divisor counters Z «or Z //. The content of the divisor counters v / iirde the Uniersel / er number cr Zm unlcr.wt / i, so that it can also be calculated for the crank angle

whereby

is. After selecting // .12 crank angle and the specified maximum measuring range for the ignition angle of 64 "," at most twice z " can be derived from folj / l, ώιΙ.Ί the HiIs of the Diwsor corresponding to the numbers 16 bin 204" -Zablcrs Z / i participate in the division process. The circuit can therefore be optimized because (J the mils corresponding to the numbers mentioned are omitted Adders and sum memory An occupancy of the memories can have been based on the omitted hiIs of the divisor-counter mehl, ijpenht'r / niialle could therefore only arise (through the Mbcr-Irai-'simpulsc of previous lower adder stages) but then the omitted counters assigned adders and sum memories are implemented by simple counters, a line of this kind is shown in Fig. 4. The I- ι g 4 largely corresponds to the I- ι μ ί ί-.s However, the two 4-bit numbers of the highest valency of the divisor-Zabicis ZjI are wtggelassert The adders and security memories assigned to these 4-Uit numbers in the circuit according to FIG replace! Znsat / hcli is provided by the NOR gate N (JIi, the two inputs of which are driven on the one hand by the most significant hit of the still forbidden 'feiles of the divisor payer A / t ttsui on the other hand by the most significant hit of the dividend payer / ". The output signal of the NOR -Gaiicrs is associated with z.usiitz.-liclien and Spcrreingiingen of the Toiscliallungen Tu and T / l , not shown in the figure.

■ This Schallungsnjiißnahrnc has to leave the purpose arbeilen the DiviclierwcrksliiridigiTiil oplimaler accuracy are \ In fact as long as the measured values ZiIhler cingczilhll until ent neither the divisor Zft'blerZ // or Dividcnden-Zilliler are to fully and thus their highest Bit is set. The NOR-, gate then signals the linde of the measuring wcrtaiimiihmc,

As weilcrcn Optirnierungsschritt g is in the circuit of F i. 4, the hit with the lowest value is to be omitted from the digits that replace the omitted adders and summation memories and the additional bit connected upstream of the result counter Zc. The only required resolution of 1/4 "crank angle is then achieved. The bit '/ lowest valency of the counters replacing the omitted adders and summation memories is expediently controlled via a NAND gate, one input of which is controlled by the transfer pulse of the adder with the highest valency and whose other input is connected to the clock pulses via the control circuit .S "/ ^1,

ίο The equation for the ignition angle π considered so far applies to the relative ignition angle. However, the absolute ignition angle is primarily of interest as a result of an ignition angle measurement. This depends on the relationship between the location of the terminal mark

/ 5 of the reference angle / J and the position of the real one top dead center of the machine. It has been found that piston internal combustion engines in general no late ignitions greater than 15 "after reach top dead center. Therefore, the second // mark is set to 20 "crank arms after the When top dead center is set, a relative ZUndwinkel is obtained which is always only in one quadrant. However, the absolute ignition angle is only obtained by subtracting this "lead angle" from 20 "crank angle obtainable.

The geometric relationships are shown in FIG. 5 can be seen, in which the top dead center OT is drawn in a circle representing the complete crankw / nkcl. The reference angle // extends from 20 "after the upper lot point to 12 before the upper loipunki. The possible measuring range for the ignition angle α extends over 64 'from the second mark of the reference angle // in the direction of the angular velocity >·>. The absolute ignition angle follows the equation

2t) crank

The electrical subtraction of 20 Kurbrlwinkcl is easy to use is one / cash Vorwiirts-RUckwiirtszahlcrs as Ergcbnis-Zählc »Ze / u realize this Ziihler is set to 20 crank angle before the start of the division. A counting flip-flop controls the counter in reverse, while a gate queries the result counter to determine whether it is zero. If the result of the division operation reaches zero, the ZiIhI-directional Fhp-Flop is knocked over and controls the result counter Zi- in the direction of the forward swirl

Such a counter is shown in FIG. 6. There are 4-digit counters that are mutually interconnected and that are transmitted by the control circuit ST via small rings located on their underside

% Clock pulses are applied. Further inputs are acted upon by a counting direction flip-flop FVR. From there, the Zühlrichtung the Ziihler% is controlled. A gate NAND2 accesses the zero point via its two inputs.

c, n signal controls together with a Rückselzimpuls the directional Plip-plop FFR, at the top of the i "Ziihler Bingiinge shown are for setting de" Zifhlers. It is indicated that the Ziihler is set to the ^u Number 20 The Nullpunktabgriff happens

f, ₅ via a minimum-minimum output of the numerator. % Setting to 20 ° Kurbelwinkcl will be within the RUckselzimpuls, at the same time the flip-flop Ziihlrichliings- hf FFR in the correct position tilts.

[irer / u A HIa (I drawings

509550/219

Claims (7)

Pnten claims. 1. Digital arithmetic unit for determining the ignition angle in Kolhen internal combustion engines from the ratio of two pulse numbers, with a counter for the divisor, a first adder and sum memory connected in parallel, a counter for dividends, a comparator for comparing the sum memory / crlc and dividend counting values, a control circuit with adding pulse output and a result counter, characterized in that the counter (Z / 0 for the divisor a sub-counter ZilhleriZ ») with a number of bits corresponding to an additional factor (//) of the pulse number ratio and a second adder is connected upstream (Au) and summation memory (SPFF) are connected in parallel to the divider counter (Zu) and carry pulses from the second adder (Au) are fed to the least significant bit of the first adder (A). 2. Digital arithmetic unit according to claim I, characterized in that the result counter (Ze) is expanded by a number of bits of the lowest significance corresponding to a proportion of the additional factor. 3. Digital arithmetic unit according to claim I or 2, characterized in that the divisor counter (ZfI) is shortened by as many bits of higher significance as the coaster counter (Zu) contains Biis and the omitted bits assigned part of the first adder (A ) and summation memory (SPFF) is replaced by a counter. 4. Digital arithmetic unit according to Claim 3, characterized in that the transfer output of the part assigned to the bits still present in the divisor counter (ZfI). of the first adder (A) is connected to the second least significant bit of the omitted part of the first adder (A) and summation memory (SPFF) c etzendcn counter and the least significant bit of the result counter (Ze) is omitted. 5. Digital arithmetic unit according to claim 3 or 4, characterized in that the highest value bit of the divisor counter (Ζ, Ι) and the highest value bit of the dividend counter (Zn) to the two inputs of a NOR gate (NOR) is connected, the output of which is connected to the blocking inputs of gate circuits (Tu, T / l) for the dividend and divisor counting pulses. 6. A digital arithmetic unit according to claim 3 or one of the subsequent claims, as "driven bit / as least significant of the replacing the entfallenen part of the first adder (A) and the sum memory (SPFF) counter on the output of a NAND Gattcrs (NAND) is, one input of which is connected to the carry output of the remaining bits of the divisor counter (Zi!) assigned part of the first adder and the other input is connected to the addicr pulse output of the control circuit (ST). 7. Digital arithmetic unit according to claim I or one of the following, characterized in that the result counter (Ze) is a vorcinstcllbarcr (settable) forward-backward counter, which is equal to the additional factor (//) corresponding Vcrgleiehswmkels of 32 "Kwrnelwinkel is set to 20 "Ktirbelwinkel before the start of the arithmetic operation,